7 /* ----- Ethernet Buffer definitions ----- */
10 unsigned long addr,size;
13 #define RBF_ADDR 0xfffffffc
14 #define RBF_OWNER (1<<0)
15 #define RBF_WRAP (1<<1)
16 #define RBF_BROADCAST (1<<31)
17 #define RBF_MULTICAST (1<<30)
18 #define RBF_UNICAST (1<<29)
19 #define RBF_EXTERNAL (1<<28)
20 #define RBF_UNKOWN (1<<27)
21 #define RBF_SIZE 0x07ff
22 #define RBF_LOCAL4 (1<<26)
23 #define RBF_LOCAL3 (1<<25)
24 #define RBF_LOCAL2 (1<<24)
25 #define RBF_LOCAL1 (1<<23)
27 #define RBF_FRAMEMAX 10
28 #define RBF_FRAMEMEM 0x200000
29 #define RBF_FRAMELEN 0x600
31 #define RBF_FRAMEBTD RBF_FRAMEMEM
32 #define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t))
34 /* stolen from mii.h */
35 /* Generic MII registers. */
37 #define MII_BMCR 0x00 /* Basic mode control register */
38 #define MII_BMSR 0x01 /* Basic mode status register */
39 #define BMSR_JCD 0x0002 /* Jabber detected */
40 #define BMSR_LSTATUS 0x0004 /* Link status */
41 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
42 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
43 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
44 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
46 #define MII_STS2_REG 17 /* Davicom specific */
47 #define MII_MDINTR_REG 21 /* Davicom specific */
49 #ifdef CONFIG_DRIVER_ETHER
51 #if (CONFIG_COMMANDS & CFG_CMD_NET)
55 int MII_ReadPhy(unsigned char addr, unsigned short *ret)
58 p_mac->EMAC_MAN = 0x60020000 | (addr << 18);
60 *ret = (unsigned short)p_mac->EMAC_MAN;
65 int MII_GetLinkSpeed(void)
67 unsigned short stat1, stat2;
70 if (!(ret = MII_ReadPhy(MII_BMSR, &stat1)))
76 printf("MII: jabber condition detected\n");
77 #endif /*jabber detected re-read the register*/
79 if (!(ret = MII_ReadPhy(MII_BMSR, &stat1)))
81 if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
83 printf("MII: no Link\n");
87 if (!(ret = MII_ReadPhy(MII_STS2_REG, &stat2)))
90 if ((stat1 & BMSR_100FULL) && (stat2 & 0x8000) )
92 /* set MII for 100BaseTX and Full Duplex */
93 p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
95 printf("MII: 100BaseTX and Full Duplex detected\n");
101 if ((stat1 & BMSR_10FULL) && (stat2 & 0x2000))
103 /* set MII for 10BaseT and Full Duplex */
104 p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD));
106 printf("MII: 10BaseT and Full Duplex detected\n");
111 if ((stat1 & BMSR_100HALF) && (stat2 & 0x4000))
113 /* set MII for 100BaseTX and Half Duplex */
114 p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD));
116 printf("MII: 100BaseTX and Hall Duplex detected\n");
121 if ((stat1 & BMSR_10HALF) && (stat2 & 0x1000))
123 /*set MII for 10BaseT and Half Duplex */
124 p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
126 printf("MII: 10BaseT and Hall Duplex detected\n");
135 int MDIO_StartupPhy(void)
139 if(p_mac->EMAC_SR & AT91C_EMAC_LINK)
141 printf("MDIO_StartupPhy: no link\n");
145 p_mac->EMAC_CTL |= AT91C_EMAC_MPE;
147 ret = MII_GetLinkSpeed();
150 printf("MDIO_StartupPhy: MII_GetLinkSpeed failed\n");
158 p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE;
167 int eth_init( bd_t *bd )
171 p_mac = AT91C_BASE_EMAC;
173 *AT91C_PIOA_PDR = AT91C_PA16_EMDIO |
174 AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1 | AT91C_PA12_ERX0 |
175 AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
176 AT91C_PA7_ETXCK_EREFCK; /* PIO Disable Register */
178 *AT91C_PIOB_PDR = AT91C_PB25_EF100 |
179 AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 |
180 AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
182 *AT91C_PIOB_BSR = AT91C_PB25_EF100 |
183 AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 |
184 AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; /* Select B Register */
185 *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
186 p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
188 rbfdt=(rbf_t *)RBF_FRAMEBTD;
189 for(i = 0; i < RBF_FRAMEMAX; i++)
191 rbfdt[i].addr=RBF_FRAMEBUF+RBF_FRAMELEN*i;
194 rbfdt[RBF_FRAMEMAX-1].addr|=RBF_WRAP;
197 if (!(ret = MDIO_StartupPhy()))
199 printf("MAC: error during MII initialization\n");
203 p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
204 | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]);
205 p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]);
207 p_mac->EMAC_RBQP = (long)(&rbfdt[0]);
208 p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
209 p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_RMII) & ~AT91C_EMAC_CLK;
210 p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE ;
215 int eth_send(volatile void *packet, int length)
217 while(!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ))
219 p_mac->EMAC_TAR = (long)packet;
220 p_mac->EMAC_TCR = length;
221 while(p_mac->EMAC_TCR & 0x7ff)
223 p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
231 if(!(rbfp->addr & RBF_OWNER))
234 size=rbfp->size & RBF_SIZE;
235 NetReceive((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
237 rbfp->addr &= ~RBF_OWNER;
238 if(rbfp->addr & RBF_WRAP)
243 p_mac->EMAC_RSR |= AT91C_EMAC_REC;
248 void eth_halt( void )