2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Terry Lv <r65388@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <linux/ctype.h>
16 #include <linux/errno.h>
18 #include <linux/bitops.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include "dwc_ahsata.h"
23 struct sata_port_regs {
47 struct sata_host_regs {
76 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
77 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
79 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
83 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
85 return base + 0x100 + (port * 0x80);
88 static int waiting_for_cmd_completed(u8 *offset,
96 ((status = readl(offset)) & sign) && i < timeout_msec;
100 return (i < timeout_msec) ? 0 : -1;
103 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
105 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
107 writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr));
108 writel(0x02060b14, &(host_mmio->oobr));
113 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
115 u32 tmp, cap_save, num_ports;
116 int i, j, timeout = 1000;
117 struct sata_port_regs *port_mmio = NULL;
118 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
119 int clk = mxc_get_clock(MXC_SATA_CLK);
121 cap_save = readl(&(host_mmio->cap));
122 cap_save |= SATA_HOST_CAP_SSS;
124 /* global controller reset */
125 tmp = readl(&(host_mmio->ghc));
126 if ((tmp & SATA_HOST_GHC_HR) == 0)
127 writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc));
129 while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR)
134 debug("controller reset failed (0x%x)\n", tmp);
139 writel(clk / 1000, &(host_mmio->timer1ms));
141 ahci_setup_oobr(uc_priv, 0);
143 writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc));
144 writel(cap_save, &(host_mmio->cap));
145 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
146 writel_with_flush((1 << num_ports) - 1,
150 * Determine which Ports are implemented by the DWC_ahsata,
151 * by reading the PI register. This bit map value aids the
152 * software to determine how many Ports are available and
153 * which Port registers need to be initialized.
155 uc_priv->cap = readl(&(host_mmio->cap));
156 uc_priv->port_map = readl(&(host_mmio->pi));
158 /* Determine how many command slots the HBA supports */
159 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
161 debug("cap 0x%x port_map 0x%x n_ports %d\n",
162 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
164 for (i = 0; i < uc_priv->n_ports; i++) {
165 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
166 port_mmio = uc_priv->port[i].port_mmio;
168 /* Ensure that the DWC_ahsata is in idle state */
169 tmp = readl(&(port_mmio->cmd));
172 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
173 * are all cleared, the Port is in an idle state.
175 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
176 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
179 * System software places a Port into the idle state by
180 * clearing P#CMD.ST and waiting for P#CMD.CR to return
183 tmp &= ~SATA_PORT_CMD_ST;
184 writel_with_flush(tmp, &(port_mmio->cmd));
187 * spec says 500 msecs for each bit, so
188 * this is slightly incorrect.
193 while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR)
198 debug("port reset failed (0x%x)\n", tmp);
204 tmp = readl(&(port_mmio->cmd));
205 writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd));
207 /* Wait for spin-up to finish */
209 while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD)
213 debug("Spin-Up can't finish!\n");
217 for (j = 0; j < 100; ++j) {
219 tmp = readl(&(port_mmio->ssts));
220 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
221 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
225 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
227 while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X)
231 debug("Can't find DIAG_X set!\n");
236 * For each implemented Port, clear the P#SERR
237 * register, by writing ones to each implemented\
240 tmp = readl(&(port_mmio->serr));
241 debug("P#SERR 0x%x\n",
243 writel(tmp, &(port_mmio->serr));
245 /* Ack any pending irq events for this port */
246 tmp = readl(&(host_mmio->is));
247 debug("IS 0x%x\n", tmp);
249 writel(tmp, &(host_mmio->is));
251 writel(1 << i, &(host_mmio->is));
253 /* set irq mask (enables interrupts) */
254 writel(DEF_PORT_IRQ, &(port_mmio->ie));
256 /* register linkup ports */
257 tmp = readl(&(port_mmio->ssts));
258 debug("Port %d status: 0x%x\n", i, tmp);
259 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
260 uc_priv->link_port_map |= (0x01 << i);
263 tmp = readl(&(host_mmio->ghc));
264 debug("GHC 0x%x\n", tmp);
265 writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc));
266 tmp = readl(&(host_mmio->ghc));
267 debug("GHC 0x%x\n", tmp);
272 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
274 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
275 u32 vers, cap, impl, speed;
279 vers = readl(&(host_mmio->vs));
281 impl = uc_priv->port_map;
283 speed = (cap & SATA_HOST_CAP_ISS_MASK)
284 >> SATA_HOST_CAP_ISS_OFFSET;
294 printf("AHCI %02x%02x.%02x%02x "
295 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
300 ((cap >> 8) & 0x1f) + 1,
309 cap & (1 << 31) ? "64bit " : "",
310 cap & (1 << 30) ? "ncq " : "",
311 cap & (1 << 28) ? "ilck " : "",
312 cap & (1 << 27) ? "stag " : "",
313 cap & (1 << 26) ? "pm " : "",
314 cap & (1 << 25) ? "led " : "",
315 cap & (1 << 24) ? "clo " : "",
316 cap & (1 << 19) ? "nz " : "",
317 cap & (1 << 18) ? "only " : "",
318 cap & (1 << 17) ? "pmp " : "",
319 cap & (1 << 15) ? "pio " : "",
320 cap & (1 << 14) ? "slum " : "",
321 cap & (1 << 13) ? "part " : "");
324 static int ahci_init_one(int pdev)
327 struct ahci_uc_priv *uc_priv = NULL;
329 uc_priv = malloc(sizeof(struct ahci_uc_priv));
330 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
333 uc_priv->host_flags = ATA_FLAG_SATA
339 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
341 /* initialize adapter */
342 rc = ahci_host_init(uc_priv);
346 ahci_print_info(uc_priv);
348 /* Save the uc_private struct to block device struct */
349 sata_dev_desc[pdev].priv = uc_priv;
357 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
358 unsigned char *buf, int buf_len)
360 struct ahci_ioports *pp = &(uc_priv->port[port]);
361 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
362 u32 sg_count, max_bytes;
365 max_bytes = MAX_DATA_BYTES_PER_SG;
366 sg_count = ((buf_len - 1) / max_bytes) + 1;
367 if (sg_count > AHCI_MAX_SG) {
368 printf("Error:Too much sg!\n");
372 for (i = 0; i < sg_count; i++) {
374 cpu_to_le32((u32)buf + i * max_bytes);
375 ahci_sg->addr_hi = 0;
376 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
381 buf_len -= max_bytes;
387 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
389 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
390 AHCI_CMD_SLOT_SZ * cmd_slot);
392 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
393 cmd_hdr->opts = cpu_to_le32(opts);
395 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
396 #ifdef CONFIG_PHYS_64BIT
397 pp->cmd_slot->tbl_addr_hi =
398 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
402 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
404 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
405 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
408 struct ahci_ioports *pp = &(uc_priv->port[port]);
409 struct sata_port_regs *port_mmio = pp->port_mmio;
411 int sg_count = 0, cmd_slot = 0;
413 cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci)));
414 if (32 == cmd_slot) {
415 printf("Can't find empty command slot!\n");
419 /* Check xfer length */
420 if (buf_len > MAX_BYTES_PER_TRANS) {
421 printf("Max transfer length is %dB\n\r",
422 MAX_BYTES_PER_TRANS);
426 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
428 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
429 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
432 flush_cache((ulong)buf, buf_len);
434 ahci_fill_cmd_slot(pp, cmd_slot, opts);
436 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
437 writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
439 if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
440 10000, 0x1 << cmd_slot)) {
441 printf("timeout exit!\n");
444 invalidate_dcache_range((int)(pp->cmd_slot),
445 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
446 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
447 pp->cmd_slot->status);
449 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
454 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
456 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
457 struct sata_fis_h2d *cfis = &h2d;
459 memset(cfis, 0, sizeof(struct sata_fis_h2d));
460 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
461 cfis->pm_port_c = 1 << 7;
462 cfis->command = ATA_CMD_SET_FEATURES;
463 cfis->features = SETFEATURES_XFER;
464 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
466 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
469 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
471 struct ahci_ioports *pp = &(uc_priv->port[port]);
472 struct sata_port_regs *port_mmio = pp->port_mmio;
475 int timeout = 10000000;
477 debug("Enter start port: %d\n", port);
478 port_status = readl(&(port_mmio->ssts));
479 debug("Port %d status: %x\n", port, port_status);
480 if ((port_status & 0xf) != 0x03) {
481 printf("No Link on this port!\n");
485 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
488 printf("No mem for table!\n");
492 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
493 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
496 * First item in chunk of DMA memory: 32-slot command table,
497 * 32 bytes each in size
499 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
500 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
501 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
504 * Second item: Received-FIS area, 256-Byte aligned
507 mem += AHCI_RX_FIS_SZ;
510 * Third item: data area for storing a single command
511 * and its scatter-gather table
514 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
516 mem += AHCI_CMD_TBL_HDR;
518 writel_with_flush(0x00004444, &(port_mmio->dmacr));
519 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
520 writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb));
521 writel_with_flush(pp->rx_fis, &(port_mmio->fb));
524 writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))),
527 /* Wait device ready */
528 while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR |
529 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
533 debug("Device not ready for BSY, DRQ and"
538 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
539 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
540 PORT_CMD_START, &(port_mmio->cmd));
542 debug("Exit start port %d\n", port);
547 static void dwc_ahsata_print_info(struct blk_desc *pdev)
549 printf("SATA Device Info:\n\r");
550 #ifdef CONFIG_SYS_64BIT_LBA
551 printf("S/N: %s\n\rProduct model number: %s\n\r"
552 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
553 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
555 printf("S/N: %s\n\rProduct model number: %s\n\r"
556 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
557 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
561 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
563 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
564 struct sata_fis_h2d *cfis = &h2d;
565 u8 port = uc_priv->hard_port_no;
567 memset(cfis, 0, sizeof(struct sata_fis_h2d));
569 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
570 cfis->pm_port_c = 0x80; /* is command */
571 cfis->command = ATA_CMD_ID_ATA;
573 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
575 ata_swap_buf_le16(id, ATA_ID_WORDS);
578 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
580 uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
581 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
582 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
585 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
586 u32 blkcnt, u8 *buffer, int is_write)
588 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
589 struct sata_fis_h2d *cfis = &h2d;
590 u8 port = uc_priv->hard_port_no;
595 memset(cfis, 0, sizeof(struct sata_fis_h2d));
597 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
598 cfis->pm_port_c = 0x80; /* is command */
599 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
600 cfis->device = ATA_LBA;
602 cfis->device |= (block >> 24) & 0xf;
603 cfis->lba_high = (block >> 16) & 0xff;
604 cfis->lba_mid = (block >> 8) & 0xff;
605 cfis->lba_low = block & 0xff;
606 cfis->sector_count = (u8)(blkcnt & 0xff);
608 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
609 ATA_SECT_SIZE * blkcnt, is_write) > 0)
615 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
617 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
618 struct sata_fis_h2d *cfis = &h2d;
619 u8 port = uc_priv->hard_port_no;
621 memset(cfis, 0, sizeof(struct sata_fis_h2d));
623 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
624 cfis->pm_port_c = 0x80; /* is command */
625 cfis->command = ATA_CMD_FLUSH;
627 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
630 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
631 lbaint_t blkcnt, u8 *buffer, int is_write)
633 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
634 struct sata_fis_h2d *cfis = &h2d;
635 u8 port = uc_priv->hard_port_no;
640 memset(cfis, 0, sizeof(struct sata_fis_h2d));
642 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
643 cfis->pm_port_c = 0x80; /* is command */
645 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
648 cfis->lba_high_exp = (block >> 40) & 0xff;
649 cfis->lba_mid_exp = (block >> 32) & 0xff;
650 cfis->lba_low_exp = (block >> 24) & 0xff;
651 cfis->lba_high = (block >> 16) & 0xff;
652 cfis->lba_mid = (block >> 8) & 0xff;
653 cfis->lba_low = block & 0xff;
654 cfis->device = ATA_LBA;
655 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
656 cfis->sector_count = blkcnt & 0xff;
658 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
659 ATA_SECT_SIZE * blkcnt, is_write) > 0)
665 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
667 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
668 struct sata_fis_h2d *cfis = &h2d;
669 u8 port = uc_priv->hard_port_no;
671 memset(cfis, 0, sizeof(struct sata_fis_h2d));
673 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
674 cfis->pm_port_c = 0x80; /* is command */
675 cfis->command = ATA_CMD_FLUSH_EXT;
677 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
680 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
682 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
683 uc_priv->flags |= SATA_FLAG_WCACHE;
684 if (ata_id_has_flush(id))
685 uc_priv->flags |= SATA_FLAG_FLUSH;
686 if (ata_id_has_flush_ext(id))
687 uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
690 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
691 lbaint_t blkcnt, const void *buffer,
702 max_blks = ATA_MAX_SECTORS_LBA48;
705 if (blks > max_blks) {
706 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
712 addr += ATA_SECT_SIZE * max_blks;
714 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
719 addr += ATA_SECT_SIZE * blks;
726 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
727 lbaint_t blkcnt, const void *buffer,
738 max_blks = ATA_MAX_SECTORS;
740 if (blks > max_blks) {
741 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
747 addr += ATA_SECT_SIZE * max_blks;
749 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
754 addr += ATA_SECT_SIZE * blks;
761 int init_sata(int dev)
765 struct ahci_uc_priv *uc_priv = NULL;
767 #if defined(CONFIG_MX6)
768 if (!is_mx6dq() && !is_mx6dqp())
771 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
772 printf("The sata index %d is out of ranges\n\r", dev);
778 uc_priv = sata_dev_desc[dev].priv;
779 linkmap = uc_priv->link_port_map;
782 printf("No port device detected!\n");
786 for (i = 0; i < uc_priv->n_ports; i++) {
787 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
788 if (ahci_port_start(uc_priv, (u8)i)) {
789 printf("Can not start port %d\n", i);
792 uc_priv->hard_port_no = i;
800 int reset_sata(int dev)
802 struct ahci_uc_priv *uc_priv;
803 struct sata_host_regs *host_mmio;
805 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
806 printf("The sata index %d is out of ranges\n\r", dev);
810 uc_priv = sata_dev_desc[dev].priv;
812 /* not initialized, so nothing to reset */
815 host_mmio = uc_priv->mmio_base;
816 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
817 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
823 int sata_port_status(int dev, int port)
825 struct sata_port_regs *port_mmio;
826 struct ahci_uc_priv *uc_priv = NULL;
828 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
831 if (sata_dev_desc[dev].priv == NULL)
834 uc_priv = sata_dev_desc[dev].priv;
835 port_mmio = uc_priv->port[port].port_mmio;
837 return readl(&(port_mmio->ssts)) & SATA_PORT_SSTS_DET_MASK;
841 * SATA interface between low level driver and command layer
843 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
845 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
848 if (sata_dev_desc[dev].lba48)
849 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt,
852 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt,
857 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
860 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
861 u32 flags = uc_priv->flags;
863 if (sata_dev_desc[dev].lba48) {
864 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
866 if ((flags & SATA_FLAG_WCACHE) &&
867 (flags & SATA_FLAG_FLUSH_EXT))
868 dwc_ahsata_flush_cache_ext(uc_priv);
870 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
872 if ((flags & SATA_FLAG_WCACHE) &&
873 (flags & SATA_FLAG_FLUSH))
874 dwc_ahsata_flush_cache(uc_priv);
879 int scan_sata(int dev)
881 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
882 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
883 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
886 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
887 u8 port = uc_priv->hard_port_no;
888 struct blk_desc *pdev = &(sata_dev_desc[dev]);
890 id = (u16 *)memalign(ARCH_DMA_MINALIGN,
891 roundup(ARCH_DMA_MINALIGN,
892 (ATA_ID_WORDS * 2)));
894 printf("id malloc failed\n\r");
898 /* Identify device to get information */
899 dwc_ahsata_identify(uc_priv, id);
902 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
903 memcpy(pdev->product, serial, sizeof(serial));
905 /* Firmware version */
906 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
907 memcpy(pdev->revision, firmware, sizeof(firmware));
910 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
911 memcpy(pdev->vendor, product, sizeof(product));
914 n_sectors = ata_id_n_sectors(id);
915 pdev->lba = (u32)n_sectors;
917 pdev->type = DEV_TYPE_HARDDISK;
918 pdev->blksz = ATA_SECT_SIZE;
921 /* Check if support LBA48 */
922 if (ata_id_has_lba48(id)) {
924 debug("Device support LBA48\n\r");
927 /* Get the NCQ queue depth from device */
928 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
929 uc_priv->flags |= ata_id_queue_depth(id);
931 /* Get the xfer mode from device */
932 dwc_ahsata_xfer_mode(uc_priv, id);
934 /* Get the write cache status from device */
935 dwc_ahsata_init_wcache(uc_priv, id);
937 /* Set the xfer mode to highest speed */
938 ahci_set_feature(uc_priv, port);
942 dwc_ahsata_print_info(&sata_dev_desc[dev]);