2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference on libata and ahci drvier in kernel
14 #include <asm/processor.h>
15 #include <asm/errno.h>
20 #include <linux/ctype.h>
23 static int ata_io_flush(u8 port);
25 struct ahci_probe_ent *probe_ent = NULL;
26 hd_driveid_t *ataid[AHCI_MAX_PORTS];
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 10000
42 #define WAIT_MS_DATAIO 5000
43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 4
46 static inline u32 ahci_port_base(u32 base, u32 port)
48 return base + 0x100 + (port * 0x80);
52 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
53 unsigned int port_idx)
55 base = ahci_port_base(base, port_idx);
57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR;
62 #define msleep(a) udelay(a * 1000)
64 static void ahci_dcache_flush_range(unsigned begin, unsigned len)
66 const unsigned long start = begin;
67 const unsigned long end = start + len;
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
70 flush_dcache_range(start, end);
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
78 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
80 const unsigned long start = begin;
81 const unsigned long end = start + len;
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
84 invalidate_dcache_range(start, end);
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
94 AHCI_PORT_PRIV_DMA_SZ);
97 static int waiting_for_cmd_completed(volatile u8 *offset,
104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
107 return (i < timeout_msec) ? 0 : -1;
111 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
113 #ifndef CONFIG_SCSI_AHCI_PLAT
114 pci_dev_t pdev = probe_ent->dev;
116 unsigned short vendor;
118 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
119 u32 tmp, cap_save, cmd;
121 volatile u8 *port_mmio;
124 debug("ahci_host_init: start\n");
126 cap_save = readl(mmio + HOST_CAP);
127 cap_save &= ((1 << 28) | (1 << 17));
128 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
130 /* global controller reset */
131 tmp = readl(mmio + HOST_CTL);
132 if ((tmp & HOST_RESET) == 0)
133 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
135 /* reset must complete within 1 second, or
136 * the hardware should be considered fried.
141 tmp = readl(mmio + HOST_CTL);
143 debug("controller reset failed (0x%x)\n", tmp);
146 } while (tmp & HOST_RESET);
148 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
149 writel(cap_save, mmio + HOST_CAP);
150 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
152 #ifndef CONFIG_SCSI_AHCI_PLAT
153 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
155 if (vendor == PCI_VENDOR_ID_INTEL) {
157 pci_read_config_word(pdev, 0x92, &tmp16);
159 pci_write_config_word(pdev, 0x92, tmp16);
162 probe_ent->cap = readl(mmio + HOST_CAP);
163 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
164 port_map = probe_ent->port_map;
165 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
167 debug("cap 0x%x port_map 0x%x n_ports %d\n",
168 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
170 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
171 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
173 for (i = 0; i < probe_ent->n_ports; i++) {
174 if (!(port_map & (1 << i)))
176 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
177 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
178 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
180 /* make sure port is not active */
181 tmp = readl(port_mmio + PORT_CMD);
182 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
183 PORT_CMD_FIS_RX | PORT_CMD_START)) {
184 debug("Port %d is active. Deactivating.\n", i);
185 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
186 PORT_CMD_FIS_RX | PORT_CMD_START);
187 writel_with_flush(tmp, port_mmio + PORT_CMD);
189 /* spec says 500 msecs for each bit, so
190 * this is slightly incorrect.
195 /* Add the spinup command to whatever mode bits may
196 * already be on in the command register.
198 cmd = readl(port_mmio + PORT_CMD);
199 cmd |= PORT_CMD_FIS_RX;
200 cmd |= PORT_CMD_SPIN_UP;
201 writel_with_flush(cmd, port_mmio + PORT_CMD);
203 /* Bring up SATA link.
204 * SATA link bringup time is usually less than 1 ms; only very
205 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
208 while (j < WAIT_MS_LINKUP) {
209 tmp = readl(port_mmio + PORT_SCR_STAT);
210 if ((tmp & 0xf) == 0x3)
215 if (j == WAIT_MS_LINKUP) {
216 printf("SATA link %d timeout.\n", i);
219 debug("SATA link ok.\n");
222 /* Clear error status */
223 tmp = readl(port_mmio + PORT_SCR_ERR);
225 writel(tmp, port_mmio + PORT_SCR_ERR);
227 debug("Spinning up device on SATA port %d... ", i);
230 while (j < WAIT_MS_SPINUP) {
231 tmp = readl(port_mmio + PORT_TFDATA);
232 if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ)))
237 printf("Target spinup took %d ms.\n", j);
238 if (j == WAIT_MS_SPINUP)
243 tmp = readl(port_mmio + PORT_SCR_ERR);
244 debug("PORT_SCR_ERR 0x%x\n", tmp);
245 writel(tmp, port_mmio + PORT_SCR_ERR);
247 /* ack any pending irq events for this port */
248 tmp = readl(port_mmio + PORT_IRQ_STAT);
249 debug("PORT_IRQ_STAT 0x%x\n", tmp);
251 writel(tmp, port_mmio + PORT_IRQ_STAT);
253 writel(1 << i, mmio + HOST_IRQ_STAT);
255 /* set irq mask (enables interrupts) */
256 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
258 /* register linkup ports */
259 tmp = readl(port_mmio + PORT_SCR_STAT);
260 debug("SATA port %d status: 0x%x\n", i, tmp);
261 if ((tmp & 0xf) == 0x03)
262 probe_ent->link_port_map |= (0x01 << i);
265 tmp = readl(mmio + HOST_CTL);
266 debug("HOST_CTL 0x%x\n", tmp);
267 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
268 tmp = readl(mmio + HOST_CTL);
269 debug("HOST_CTL 0x%x\n", tmp);
270 #ifndef CONFIG_SCSI_AHCI_PLAT
271 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
272 tmp |= PCI_COMMAND_MASTER;
273 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
279 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
281 #ifndef CONFIG_SCSI_AHCI_PLAT
282 pci_dev_t pdev = probe_ent->dev;
285 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
286 u32 vers, cap, cap2, impl, speed;
290 vers = readl(mmio + HOST_VERSION);
291 cap = probe_ent->cap;
292 cap2 = readl(mmio + HOST_CAP2);
293 impl = probe_ent->port_map;
295 speed = (cap >> 20) & 0xf;
305 #ifdef CONFIG_SCSI_AHCI_PLAT
308 pci_read_config_word(pdev, 0x0a, &cc);
311 else if (cc == 0x0106)
313 else if (cc == 0x0104)
318 printf("AHCI %02x%02x.%02x%02x "
319 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
324 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
330 cap & (1 << 31) ? "64bit " : "",
331 cap & (1 << 30) ? "ncq " : "",
332 cap & (1 << 28) ? "ilck " : "",
333 cap & (1 << 27) ? "stag " : "",
334 cap & (1 << 26) ? "pm " : "",
335 cap & (1 << 25) ? "led " : "",
336 cap & (1 << 24) ? "clo " : "",
337 cap & (1 << 19) ? "nz " : "",
338 cap & (1 << 18) ? "only " : "",
339 cap & (1 << 17) ? "pmp " : "",
340 cap & (1 << 16) ? "fbss " : "",
341 cap & (1 << 15) ? "pio " : "",
342 cap & (1 << 14) ? "slum " : "",
343 cap & (1 << 13) ? "part " : "",
344 cap & (1 << 7) ? "ccc " : "",
345 cap & (1 << 6) ? "ems " : "",
346 cap & (1 << 5) ? "sxs " : "",
347 cap2 & (1 << 2) ? "apst " : "",
348 cap2 & (1 << 1) ? "nvmp " : "",
349 cap2 & (1 << 0) ? "boh " : "");
352 #ifndef CONFIG_SCSI_AHCI_PLAT
353 static int ahci_init_one(pci_dev_t pdev)
358 memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
360 probe_ent = malloc(sizeof(struct ahci_probe_ent));
361 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
362 probe_ent->dev = pdev;
364 probe_ent->host_flags = ATA_FLAG_SATA
369 probe_ent->pio_mask = 0x1f;
370 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
372 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
373 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
376 * JMicron-specific fixup:
377 * make sure we're in AHCI mode
379 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
380 if (vendor == 0x197b)
381 pci_write_config_byte(pdev, 0x41, 0xa1);
383 /* initialize adapter */
384 rc = ahci_host_init(probe_ent);
388 ahci_print_info(probe_ent);
397 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
399 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
401 struct ahci_ioports *pp = &(probe_ent->port[port]);
402 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
406 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
407 if (sg_count > AHCI_MAX_SG) {
408 printf("Error:Too much sg!\n");
412 for (i = 0; i < sg_count; i++) {
414 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
415 ahci_sg->addr_hi = 0;
416 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
417 (buf_len < MAX_DATA_BYTE_COUNT
419 : (MAX_DATA_BYTE_COUNT - 1)));
421 buf_len -= MAX_DATA_BYTE_COUNT;
428 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
430 pp->cmd_slot->opts = cpu_to_le32(opts);
431 pp->cmd_slot->status = 0;
432 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
433 pp->cmd_slot->tbl_addr_hi = 0;
437 #ifdef CONFIG_AHCI_SETFEATURES_XFER
438 static void ahci_set_feature(u8 port)
440 struct ahci_ioports *pp = &(probe_ent->port[port]);
441 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
442 u32 cmd_fis_len = 5; /* five dwords */
446 memset(fis, 0, sizeof(fis));
449 fis[2] = ATA_CMD_SETF;
450 fis[3] = SETFEATURES_XFER;
451 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
453 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
454 ahci_fill_cmd_slot(pp, cmd_fis_len);
455 ahci_dcache_flush_sata_cmd(pp);
456 writel(1, port_mmio + PORT_CMD_ISSUE);
457 readl(port_mmio + PORT_CMD_ISSUE);
459 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
460 WAIT_MS_DATAIO, 0x1)) {
461 printf("set feature error on port %d!\n", port);
467 static int ahci_port_start(u8 port)
469 struct ahci_ioports *pp = &(probe_ent->port[port]);
470 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
474 debug("Enter start port: %d\n", port);
475 port_status = readl(port_mmio + PORT_SCR_STAT);
476 debug("Port %d status: %x\n", port, port_status);
477 if ((port_status & 0xf) != 0x03) {
478 printf("No Link on this port!\n");
482 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
485 printf("No mem for table!\n");
489 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
490 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
493 * First item in chunk of DMA memory: 32-slot command table,
494 * 32 bytes each in size
497 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
498 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
499 mem += (AHCI_CMD_SLOT_SZ + 224);
502 * Second item: Received-FIS area
504 pp->rx_fis = virt_to_phys((void *)mem);
505 mem += AHCI_RX_FIS_SZ;
508 * Third item: data area for storing a single command
509 * and its scatter-gather table
511 pp->cmd_tbl = virt_to_phys((void *)mem);
512 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
514 mem += AHCI_CMD_TBL_HDR;
516 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
518 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
520 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
522 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
523 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
524 PORT_CMD_START, port_mmio + PORT_CMD);
526 debug("Exit start port %d\n", port);
532 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
533 int buf_len, u8 is_write)
536 struct ahci_ioports *pp = &(probe_ent->port[port]);
537 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
542 debug("Enter %s: for port %d\n", __func__, port);
544 if (port > probe_ent->n_ports) {
545 printf("Invalid port number %d\n", port);
549 port_status = readl(port_mmio + PORT_SCR_STAT);
550 if ((port_status & 0xf) != 0x03) {
551 debug("No Link on port %d!\n", port);
555 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
557 sg_count = ahci_fill_sg(port, buf, buf_len);
558 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
559 ahci_fill_cmd_slot(pp, opts);
561 ahci_dcache_flush_sata_cmd(pp);
562 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
564 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
566 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
567 WAIT_MS_DATAIO, 0x1)) {
568 printf("timeout exit!\n");
572 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
573 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
579 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
582 for (i = 0; i < len / 2; i++)
583 target[i] = swab16(src[i]);
584 return (char *)target;
588 static void dump_ataid(hd_driveid_t *ataid)
590 debug("(49)ataid->capability = 0x%x\n", ataid->capability);
591 debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
592 debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
593 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
594 debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
595 debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
596 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
597 debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
598 debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
599 debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
600 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
601 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
602 debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
603 debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
604 debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
609 * SCSI INQUIRY command operation.
611 static int ata_scsiop_inquiry(ccb *pccb)
616 0x5, /* claim SPC-3 version compatibility */
624 /* Clean ccb data buffer */
625 memset(pccb->pdata, 0, pccb->datalen);
627 memcpy(pccb->pdata, hdr, sizeof(hdr));
629 if (pccb->datalen <= 35)
632 memset(fis, 0, sizeof(fis));
633 /* Construct the FIS */
634 fis[0] = 0x27; /* Host to device FIS. */
635 fis[1] = 1 << 7; /* Command FIS. */
636 fis[2] = ATA_CMD_IDENT; /* Command byte. */
638 /* Read id from sata */
640 if (!(tmpid = malloc(sizeof(hd_driveid_t))))
643 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,
644 sizeof(hd_driveid_t), 0)) {
645 debug("scsi_ahci: SCSI inquiry command failure.\n");
651 ataid[port] = (hd_driveid_t *) tmpid;
653 memcpy(&pccb->pdata[8], "ATA ", 8);
654 ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
655 ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
657 dump_ataid(ataid[port]);
663 * SCSI READ10/WRITE10 command operation.
665 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
670 u8 *user_buffer = pccb->pdata;
671 u32 user_buffer_size = pccb->datalen;
673 /* Retrieve the base LBA number from the ccb structure. */
674 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
675 lba = be32_to_cpu(lba);
678 * And the number of blocks.
680 * For 10-byte and 16-byte SCSI R/W commands, transfer
681 * length 0 means transfer 0 block of data.
682 * However, for ATA R/W commands, sector count 0 means
683 * 256 or 65536 sectors, not 0 sectors as in SCSI.
685 * WARNING: one or two older ATA drives treat 0 as 0...
687 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
689 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
690 is_write ? "write" : "read", (unsigned)lba, blocks);
693 memset(fis, 0, sizeof(fis));
694 fis[0] = 0x27; /* Host to device FIS. */
695 fis[1] = 1 << 7; /* Command FIS. */
696 /* Command byte (read/write). */
697 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
700 u16 now_blocks; /* number of blocks per iteration */
701 u32 transfer_size; /* number of bytes per iteration */
703 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
705 transfer_size = ATA_BLOCKSIZE * now_blocks;
706 if (transfer_size > user_buffer_size) {
707 printf("scsi_ahci: Error: buffer too small.\n");
711 /* LBA48 SATA command but only use 32bit address range within
712 * that. The next smaller command range (28bit) is too small.
714 fis[4] = (lba >> 0) & 0xff;
715 fis[5] = (lba >> 8) & 0xff;
716 fis[6] = (lba >> 16) & 0xff;
717 fis[7] = 1 << 6; /* device reg: set LBA mode */
718 fis[8] = ((lba >> 24) & 0xff);
719 fis[3] = 0xe0; /* features */
721 /* Block (sector) count */
722 fis[12] = (now_blocks >> 0) & 0xff;
723 fis[13] = (now_blocks >> 8) & 0xff;
725 /* Read/Write from ahci */
726 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
727 user_buffer, user_buffer_size,
729 debug("scsi_ahci: SCSI %s10 command failure.\n",
730 is_write ? "WRITE" : "READ");
734 /* If this transaction is a write, do a following flush.
735 * Writes in u-boot are so rare, and the logic to know when is
736 * the last write and do a flush only there is sufficiently
737 * difficult. Just do a flush after every write. This incurs,
738 * usually, one extra flush when the rare writes do happen.
741 if (-EIO == ata_io_flush(pccb->target))
744 user_buffer += transfer_size;
745 user_buffer_size -= transfer_size;
746 blocks -= now_blocks;
755 * SCSI READ CAPACITY10 command operation.
757 static int ata_scsiop_read_capacity10(ccb *pccb)
762 if (!ataid[pccb->target]) {
763 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
765 "\tPlease run SCSI commmand INQUIRY firstly!\n");
769 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
770 if (cap == 0xfffffff) {
771 unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;
772 if (cap48[2] || cap48[3]) {
775 cap = (le16_to_cpu(cap48[1]) << 16) |
776 (le16_to_cpu(cap48[0]));
780 cap = cpu_to_be32(cap);
781 memcpy(pccb->pdata, &cap, sizeof(cap));
783 block_size = cpu_to_be32((u32)512);
784 memcpy(&pccb->pdata[4], &block_size, 4);
791 * SCSI READ CAPACITY16 command operation.
793 static int ata_scsiop_read_capacity16(ccb *pccb)
798 if (!ataid[pccb->target]) {
799 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
801 "\tPlease run SCSI commmand INQUIRY firstly!\n");
805 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
806 if (cap == 0xfffffff) {
807 memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));
808 cap = le64_to_cpu(cap);
811 cap = cpu_to_be64(cap);
812 memcpy(pccb->pdata, &cap, sizeof(cap));
814 block_size = cpu_to_be64((u64)512);
815 memcpy(&pccb->pdata[8], &block_size, 8);
822 * SCSI TEST UNIT READY command operation.
824 static int ata_scsiop_test_unit_ready(ccb *pccb)
826 return (ataid[pccb->target]) ? 0 : -EPERM;
830 int scsi_exec(ccb *pccb)
834 switch (pccb->cmd[0]) {
836 ret = ata_scsiop_read_write(pccb, 0);
839 ret = ata_scsiop_read_write(pccb, 1);
841 case SCSI_RD_CAPAC10:
842 ret = ata_scsiop_read_capacity10(pccb);
844 case SCSI_RD_CAPAC16:
845 ret = ata_scsiop_read_capacity16(pccb);
848 ret = ata_scsiop_test_unit_ready(pccb);
851 ret = ata_scsiop_inquiry(pccb);
854 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
859 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
867 void scsi_low_level_init(int busdevfunc)
872 #ifndef CONFIG_SCSI_AHCI_PLAT
873 ahci_init_one(busdevfunc);
876 linkmap = probe_ent->link_port_map;
878 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
879 if (((linkmap >> i) & 0x01)) {
880 if (ahci_port_start((u8) i)) {
881 printf("Can not start port %d\n", i);
884 #ifdef CONFIG_AHCI_SETFEATURES_XFER
885 ahci_set_feature((u8) i);
891 #ifdef CONFIG_SCSI_AHCI_PLAT
892 int ahci_init(u32 base)
897 memset(ataid, 0, sizeof(ataid));
899 probe_ent = malloc(sizeof(struct ahci_probe_ent));
900 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
902 probe_ent->host_flags = ATA_FLAG_SATA
907 probe_ent->pio_mask = 0x1f;
908 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
910 probe_ent->mmio_base = base;
912 /* initialize adapter */
913 rc = ahci_host_init(probe_ent);
917 ahci_print_info(probe_ent);
919 linkmap = probe_ent->link_port_map;
921 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
922 if (((linkmap >> i) & 0x01)) {
923 if (ahci_port_start((u8) i)) {
924 printf("Can not start port %d\n", i);
927 #ifdef CONFIG_AHCI_SETFEATURES_XFER
928 ahci_set_feature((u8) i);
938 * In the general case of generic rotating media it makes sense to have a
939 * flush capability. It probably even makes sense in the case of SSDs because
940 * one cannot always know for sure what kind of internal cache/flush mechanism
941 * is embodied therein. At first it was planned to invoke this after the last
942 * write to disk and before rebooting. In practice, knowing, a priori, which
943 * is the last write is difficult. Because writing to the disk in u-boot is
944 * very rare, this flush command will be invoked after every block write.
946 static int ata_io_flush(u8 port)
949 struct ahci_ioports *pp = &(probe_ent->port[port]);
950 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
951 u32 cmd_fis_len = 5; /* five dwords */
955 fis[0] = 0x27; /* Host to device FIS. */
956 fis[1] = 1 << 7; /* Command FIS. */
957 fis[2] = ATA_CMD_FLUSH_EXT;
959 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
960 ahci_fill_cmd_slot(pp, cmd_fis_len);
961 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
963 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
964 WAIT_MS_FLUSH, 0x1)) {
965 debug("scsi_ahci: flush command timeout on port %d.\n", port);
973 void scsi_bus_reset(void)
979 void scsi_print_error(ccb * pccb)
981 /*The ahci error info can be read in the ahci driver*/