2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * with the reference on libata and ahci drvier in kernel
31 #include <asm/processor.h>
32 #include <asm/errno.h>
37 #include <linux/ctype.h>
40 struct ahci_probe_ent *probe_ent = NULL;
41 hd_driveid_t *ataid[AHCI_MAX_PORTS];
43 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
46 * Some controllers limit number of blocks they can read at once. Contemporary
47 * SSD devices work much faster if the read size is aligned to a power of 2.
48 * Let's set default to 128 and allowing to be overwritten if needed.
50 #ifndef MAX_SATA_BLOCKS_READ
51 #define MAX_SATA_BLOCKS_READ 0x80
54 static inline u32 ahci_port_base(u32 base, u32 port)
56 return base + 0x100 + (port * 0x80);
60 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
61 unsigned int port_idx)
63 base = ahci_port_base(base, port_idx);
65 port->cmd_addr = base;
66 port->scr_addr = base + PORT_SCR;
70 #define msleep(a) udelay(a * 1000)
72 static int waiting_for_cmd_completed(volatile u8 *offset,
79 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
82 return (i < timeout_msec) ? 0 : -1;
86 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
88 #ifndef CONFIG_SCSI_AHCI_PLAT
89 pci_dev_t pdev = probe_ent->dev;
91 unsigned short vendor;
93 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
96 volatile u8 *port_mmio;
98 debug("ahci_host_init: start\n");
100 cap_save = readl(mmio + HOST_CAP);
101 cap_save &= ((1 << 28) | (1 << 17));
102 cap_save |= (1 << 27);
104 /* global controller reset */
105 tmp = readl(mmio + HOST_CTL);
106 if ((tmp & HOST_RESET) == 0)
107 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
109 /* reset must complete within 1 second, or
110 * the hardware should be considered fried.
115 tmp = readl(mmio + HOST_CTL);
117 debug("controller reset failed (0x%x)\n", tmp);
120 } while (tmp & HOST_RESET);
122 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
123 writel(cap_save, mmio + HOST_CAP);
124 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
126 #ifndef CONFIG_SCSI_AHCI_PLAT
127 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
129 if (vendor == PCI_VENDOR_ID_INTEL) {
131 pci_read_config_word(pdev, 0x92, &tmp16);
133 pci_write_config_word(pdev, 0x92, tmp16);
136 probe_ent->cap = readl(mmio + HOST_CAP);
137 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
138 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
140 debug("cap 0x%x port_map 0x%x n_ports %d\n",
141 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
143 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
144 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
146 for (i = 0; i < probe_ent->n_ports; i++) {
147 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
148 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
149 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
151 /* make sure port is not active */
152 tmp = readl(port_mmio + PORT_CMD);
153 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
154 PORT_CMD_FIS_RX | PORT_CMD_START)) {
155 debug("Port %d is active. Deactivating.\n", i);
156 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
157 PORT_CMD_FIS_RX | PORT_CMD_START);
158 writel_with_flush(tmp, port_mmio + PORT_CMD);
160 /* spec says 500 msecs for each bit, so
161 * this is slightly incorrect.
166 debug("Spinning up port %d... ", i);
167 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
171 tmp = readl(port_mmio + PORT_SCR_STAT);
172 if ((tmp & 0xf) == 0x3)
182 tmp = readl(port_mmio + PORT_SCR_ERR);
183 debug("PORT_SCR_ERR 0x%x\n", tmp);
184 writel(tmp, port_mmio + PORT_SCR_ERR);
186 /* ack any pending irq events for this port */
187 tmp = readl(port_mmio + PORT_IRQ_STAT);
188 debug("PORT_IRQ_STAT 0x%x\n", tmp);
190 writel(tmp, port_mmio + PORT_IRQ_STAT);
192 writel(1 << i, mmio + HOST_IRQ_STAT);
194 /* set irq mask (enables interrupts) */
195 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
197 /* register linkup ports */
198 tmp = readl(port_mmio + PORT_SCR_STAT);
199 debug("Port %d status: 0x%x\n", i, tmp);
200 if ((tmp & 0xf) == 0x03)
201 probe_ent->link_port_map |= (0x01 << i);
204 tmp = readl(mmio + HOST_CTL);
205 debug("HOST_CTL 0x%x\n", tmp);
206 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
207 tmp = readl(mmio + HOST_CTL);
208 debug("HOST_CTL 0x%x\n", tmp);
209 #ifndef CONFIG_SCSI_AHCI_PLAT
210 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
211 tmp |= PCI_COMMAND_MASTER;
212 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
218 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
220 #ifndef CONFIG_SCSI_AHCI_PLAT
221 pci_dev_t pdev = probe_ent->dev;
224 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
225 u32 vers, cap, cap2, impl, speed;
229 vers = readl(mmio + HOST_VERSION);
230 cap = probe_ent->cap;
231 cap2 = readl(mmio + HOST_CAP2);
232 impl = probe_ent->port_map;
234 speed = (cap >> 20) & 0xf;
244 #ifdef CONFIG_SCSI_AHCI_PLAT
247 pci_read_config_word(pdev, 0x0a, &cc);
250 else if (cc == 0x0106)
252 else if (cc == 0x0104)
257 printf("AHCI %02x%02x.%02x%02x "
258 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
263 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
269 cap & (1 << 31) ? "64bit " : "",
270 cap & (1 << 30) ? "ncq " : "",
271 cap & (1 << 28) ? "ilck " : "",
272 cap & (1 << 27) ? "stag " : "",
273 cap & (1 << 26) ? "pm " : "",
274 cap & (1 << 25) ? "led " : "",
275 cap & (1 << 24) ? "clo " : "",
276 cap & (1 << 19) ? "nz " : "",
277 cap & (1 << 18) ? "only " : "",
278 cap & (1 << 17) ? "pmp " : "",
279 cap & (1 << 16) ? "fbss " : "",
280 cap & (1 << 15) ? "pio " : "",
281 cap & (1 << 14) ? "slum " : "",
282 cap & (1 << 13) ? "part " : "",
283 cap & (1 << 7) ? "ccc " : "",
284 cap & (1 << 6) ? "ems " : "",
285 cap & (1 << 5) ? "sxs " : "",
286 cap2 & (1 << 2) ? "apst " : "",
287 cap2 & (1 << 1) ? "nvmp " : "",
288 cap2 & (1 << 0) ? "boh " : "");
291 #ifndef CONFIG_SCSI_AHCI_PLAT
292 static int ahci_init_one(pci_dev_t pdev)
297 memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
299 probe_ent = malloc(sizeof(struct ahci_probe_ent));
300 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
301 probe_ent->dev = pdev;
303 probe_ent->host_flags = ATA_FLAG_SATA
308 probe_ent->pio_mask = 0x1f;
309 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
311 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
312 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
315 * JMicron-specific fixup:
316 * make sure we're in AHCI mode
318 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
319 if (vendor == 0x197b)
320 pci_write_config_byte(pdev, 0x41, 0xa1);
322 /* initialize adapter */
323 rc = ahci_host_init(probe_ent);
327 ahci_print_info(probe_ent);
336 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
338 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
340 struct ahci_ioports *pp = &(probe_ent->port[port]);
341 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
345 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
346 if (sg_count > AHCI_MAX_SG) {
347 printf("Error:Too much sg!\n");
351 for (i = 0; i < sg_count; i++) {
353 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
354 ahci_sg->addr_hi = 0;
355 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
356 (buf_len < MAX_DATA_BYTE_COUNT
358 : (MAX_DATA_BYTE_COUNT - 1)));
360 buf_len -= MAX_DATA_BYTE_COUNT;
367 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
369 pp->cmd_slot->opts = cpu_to_le32(opts);
370 pp->cmd_slot->status = 0;
371 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
372 pp->cmd_slot->tbl_addr_hi = 0;
376 static void ahci_set_feature(u8 port)
378 struct ahci_ioports *pp = &(probe_ent->port[port]);
379 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
380 u32 cmd_fis_len = 5; /* five dwords */
387 fis[2] = ATA_CMD_SETF;
388 fis[3] = SETFEATURES_XFER;
389 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
391 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
392 ahci_fill_cmd_slot(pp, cmd_fis_len);
393 writel(1, port_mmio + PORT_CMD_ISSUE);
394 readl(port_mmio + PORT_CMD_ISSUE);
396 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
397 printf("set feature error on port %d!\n", port);
402 static int ahci_port_start(u8 port)
404 struct ahci_ioports *pp = &(probe_ent->port[port]);
405 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
409 debug("Enter start port: %d\n", port);
410 port_status = readl(port_mmio + PORT_SCR_STAT);
411 debug("Port %d status: %x\n", port, port_status);
412 if ((port_status & 0xf) != 0x03) {
413 printf("No Link on this port!\n");
417 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
420 printf("No mem for table!\n");
424 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
425 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
428 * First item in chunk of DMA memory: 32-slot command table,
429 * 32 bytes each in size
431 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
432 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
433 mem += (AHCI_CMD_SLOT_SZ + 224);
436 * Second item: Received-FIS area
439 mem += AHCI_RX_FIS_SZ;
442 * Third item: data area for storing a single command
443 * and its scatter-gather table
446 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
448 mem += AHCI_CMD_TBL_HDR;
449 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
451 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
453 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
455 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
456 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
457 PORT_CMD_START, port_mmio + PORT_CMD);
459 debug("Exit start port %d\n", port);
465 static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
469 struct ahci_ioports *pp = &(probe_ent->port[port]);
470 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
475 debug("Enter get_ahci_device_data: for port %d\n", port);
477 if (port > probe_ent->n_ports) {
478 printf("Invaild port number %d\n", port);
482 port_status = readl(port_mmio + PORT_SCR_STAT);
483 if ((port_status & 0xf) != 0x03) {
484 debug("No Link on port %d!\n", port);
488 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
490 sg_count = ahci_fill_sg(port, buf, buf_len);
491 opts = (fis_len >> 2) | (sg_count << 16);
492 ahci_fill_cmd_slot(pp, opts);
494 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
496 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
497 printf("timeout exit!\n");
500 debug("get_ahci_device_data: %d byte transferred.\n",
501 pp->cmd_slot->status);
507 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
510 for (i = 0; i < len / 2; i++)
511 target[i] = swab16(src[i]);
512 return (char *)target;
516 static void dump_ataid(hd_driveid_t *ataid)
518 debug("(49)ataid->capability = 0x%x\n", ataid->capability);
519 debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
520 debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
521 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
522 debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
523 debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
524 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
525 debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
526 debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
527 debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
528 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
529 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
530 debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
531 debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
532 debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
537 * SCSI INQUIRY command operation.
539 static int ata_scsiop_inquiry(ccb *pccb)
544 0x5, /* claim SPC-3 version compatibility */
552 /* Clean ccb data buffer */
553 memset(pccb->pdata, 0, pccb->datalen);
555 memcpy(pccb->pdata, hdr, sizeof(hdr));
557 if (pccb->datalen <= 35)
561 /* Construct the FIS */
562 fis[0] = 0x27; /* Host to device FIS. */
563 fis[1] = 1 << 7; /* Command FIS. */
564 fis[2] = ATA_CMD_IDENT; /* Command byte. */
566 /* Read id from sata */
568 if (!(tmpid = malloc(sizeof(hd_driveid_t))))
571 if (get_ahci_device_data(port, (u8 *) & fis, 20,
572 tmpid, sizeof(hd_driveid_t))) {
573 debug("scsi_ahci: SCSI inquiry command failure.\n");
579 ataid[port] = (hd_driveid_t *) tmpid;
581 memcpy(&pccb->pdata[8], "ATA ", 8);
582 ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
583 ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
585 dump_ataid(ataid[port]);
591 * SCSI READ10 command operation.
593 static int ata_scsiop_read10(ccb * pccb)
598 u8 *user_buffer = pccb->pdata;
599 u32 user_buffer_size = pccb->datalen;
601 /* Retrieve the base LBA number from the ccb structure. */
602 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
603 lba = be32_to_cpu(lba);
606 * And the number of blocks.
608 * For 10-byte and 16-byte SCSI R/W commands, transfer
609 * length 0 means transfer 0 block of data.
610 * However, for ATA R/W commands, sector count 0 means
611 * 256 or 65536 sectors, not 0 sectors as in SCSI.
613 * WARNING: one or two older ATA drives treat 0 as 0...
615 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
617 debug("scsi_ahci: read %d blocks starting from lba 0x%x\n",
618 (unsigned)lba, blocks);
622 fis[0] = 0x27; /* Host to device FIS. */
623 fis[1] = 1 << 7; /* Command FIS. */
624 fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
627 u16 now_blocks; /* number of blocks per iteration */
628 u32 transfer_size; /* number of bytes per iteration */
630 now_blocks = min(MAX_SATA_BLOCKS_READ, blocks);
632 transfer_size = ATA_BLOCKSIZE * now_blocks;
633 if (transfer_size > user_buffer_size) {
634 printf("scsi_ahci: Error: buffer too small.\n");
638 /* LBA address, only support LBA28 in this driver */
639 fis[4] = (lba >> 0) & 0xff;
640 fis[5] = (lba >> 8) & 0xff;
641 fis[6] = (lba >> 16) & 0xff;
642 fis[7] = ((lba >> 24) & 0xf) | 0xe0;
644 /* Block (sector) count */
645 fis[12] = (now_blocks >> 0) & 0xff;
646 fis[13] = (now_blocks >> 8) & 0xff;
649 if (get_ahci_device_data(pccb->target, (u8 *) &fis, sizeof(fis),
650 user_buffer, user_buffer_size)) {
651 debug("scsi_ahci: SCSI READ10 command failure.\n");
654 user_buffer += transfer_size;
655 user_buffer_size -= transfer_size;
656 blocks -= now_blocks;
665 * SCSI READ CAPACITY10 command operation.
667 static int ata_scsiop_read_capacity10(ccb *pccb)
671 if (!ataid[pccb->target]) {
672 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
674 "\tPlease run SCSI commmand INQUIRY firstly!\n");
678 cap = be32_to_cpu(ataid[pccb->target]->lba_capacity);
679 memcpy(pccb->pdata, &cap, sizeof(cap));
681 pccb->pdata[4] = pccb->pdata[5] = 0;
682 pccb->pdata[6] = 512 >> 8;
683 pccb->pdata[7] = 512 & 0xff;
690 * SCSI TEST UNIT READY command operation.
692 static int ata_scsiop_test_unit_ready(ccb *pccb)
694 return (ataid[pccb->target]) ? 0 : -EPERM;
698 int scsi_exec(ccb *pccb)
702 switch (pccb->cmd[0]) {
704 ret = ata_scsiop_read10(pccb);
707 ret = ata_scsiop_read_capacity10(pccb);
710 ret = ata_scsiop_test_unit_ready(pccb);
713 ret = ata_scsiop_inquiry(pccb);
716 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
721 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
729 void scsi_low_level_init(int busdevfunc)
734 #ifndef CONFIG_SCSI_AHCI_PLAT
735 ahci_init_one(busdevfunc);
738 linkmap = probe_ent->link_port_map;
740 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
741 if (((linkmap >> i) & 0x01)) {
742 if (ahci_port_start((u8) i)) {
743 printf("Can not start port %d\n", i);
746 ahci_set_feature((u8) i);
751 #ifdef CONFIG_SCSI_AHCI_PLAT
752 int ahci_init(u32 base)
757 memset(ataid, 0, sizeof(ataid));
759 probe_ent = malloc(sizeof(struct ahci_probe_ent));
760 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
762 probe_ent->host_flags = ATA_FLAG_SATA
767 probe_ent->pio_mask = 0x1f;
768 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
770 probe_ent->mmio_base = base;
772 /* initialize adapter */
773 rc = ahci_host_init(probe_ent);
777 ahci_print_info(probe_ent);
779 linkmap = probe_ent->link_port_map;
781 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
782 if (((linkmap >> i) & 0x01)) {
783 if (ahci_port_start((u8) i)) {
784 printf("Can not start port %d\n", i);
787 ahci_set_feature((u8) i);
795 void scsi_bus_reset(void)
801 void scsi_print_error(ccb * pccb)
803 /*The ahci error info can be read in the ahci driver*/