2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * with the reference on libata and ahci drvier in kernel
31 #include <asm/processor.h>
32 #include <asm/errno.h>
37 #include <linux/ctype.h>
40 struct ahci_probe_ent *probe_ent = NULL;
41 hd_driveid_t *ataid[AHCI_MAX_PORTS];
43 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
46 * Some controllers limit number of blocks they can read/write at once.
47 * Contemporary SSD devices work much faster if the read/write size is aligned
48 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
51 #ifndef MAX_SATA_BLOCKS_READ_WRITE
52 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
55 static inline u32 ahci_port_base(u32 base, u32 port)
57 return base + 0x100 + (port * 0x80);
61 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
62 unsigned int port_idx)
64 base = ahci_port_base(base, port_idx);
66 port->cmd_addr = base;
67 port->scr_addr = base + PORT_SCR;
71 #define msleep(a) udelay(a * 1000)
73 static void ahci_dcache_flush_range(unsigned begin, unsigned len)
75 const unsigned long start = begin;
76 const unsigned long end = start + len;
78 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
79 flush_dcache_range(start, end);
83 * SATA controller DMAs to physical RAM. Ensure data from the
84 * controller is invalidated from dcache; next access comes from
87 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
89 const unsigned long start = begin;
90 const unsigned long end = start + len;
92 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
93 invalidate_dcache_range(start, end);
97 * Ensure data for SATA controller is flushed out of dcache and
98 * written to physical memory.
100 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
102 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
103 AHCI_PORT_PRIV_DMA_SZ);
106 static int waiting_for_cmd_completed(volatile u8 *offset,
113 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
116 return (i < timeout_msec) ? 0 : -1;
120 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
122 #ifndef CONFIG_SCSI_AHCI_PLAT
123 pci_dev_t pdev = probe_ent->dev;
125 unsigned short vendor;
127 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
130 volatile u8 *port_mmio;
132 debug("ahci_host_init: start\n");
134 cap_save = readl(mmio + HOST_CAP);
135 cap_save &= ((1 << 28) | (1 << 17));
136 cap_save |= (1 << 27);
138 /* global controller reset */
139 tmp = readl(mmio + HOST_CTL);
140 if ((tmp & HOST_RESET) == 0)
141 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
143 /* reset must complete within 1 second, or
144 * the hardware should be considered fried.
149 tmp = readl(mmio + HOST_CTL);
151 debug("controller reset failed (0x%x)\n", tmp);
154 } while (tmp & HOST_RESET);
156 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
157 writel(cap_save, mmio + HOST_CAP);
158 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
160 #ifndef CONFIG_SCSI_AHCI_PLAT
161 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
163 if (vendor == PCI_VENDOR_ID_INTEL) {
165 pci_read_config_word(pdev, 0x92, &tmp16);
167 pci_write_config_word(pdev, 0x92, tmp16);
170 probe_ent->cap = readl(mmio + HOST_CAP);
171 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
172 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
174 debug("cap 0x%x port_map 0x%x n_ports %d\n",
175 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
177 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
178 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
180 for (i = 0; i < probe_ent->n_ports; i++) {
181 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
182 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
183 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
185 /* make sure port is not active */
186 tmp = readl(port_mmio + PORT_CMD);
187 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
188 PORT_CMD_FIS_RX | PORT_CMD_START)) {
189 debug("Port %d is active. Deactivating.\n", i);
190 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
191 PORT_CMD_FIS_RX | PORT_CMD_START);
192 writel_with_flush(tmp, port_mmio + PORT_CMD);
194 /* spec says 500 msecs for each bit, so
195 * this is slightly incorrect.
200 debug("Spinning up port %d... ", i);
201 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
205 tmp = readl(port_mmio + PORT_SCR_STAT);
206 if ((tmp & 0xf) == 0x3)
216 tmp = readl(port_mmio + PORT_SCR_ERR);
217 debug("PORT_SCR_ERR 0x%x\n", tmp);
218 writel(tmp, port_mmio + PORT_SCR_ERR);
220 /* ack any pending irq events for this port */
221 tmp = readl(port_mmio + PORT_IRQ_STAT);
222 debug("PORT_IRQ_STAT 0x%x\n", tmp);
224 writel(tmp, port_mmio + PORT_IRQ_STAT);
226 writel(1 << i, mmio + HOST_IRQ_STAT);
228 /* set irq mask (enables interrupts) */
229 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
231 /* register linkup ports */
232 tmp = readl(port_mmio + PORT_SCR_STAT);
233 debug("Port %d status: 0x%x\n", i, tmp);
234 if ((tmp & 0xf) == 0x03)
235 probe_ent->link_port_map |= (0x01 << i);
238 tmp = readl(mmio + HOST_CTL);
239 debug("HOST_CTL 0x%x\n", tmp);
240 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
241 tmp = readl(mmio + HOST_CTL);
242 debug("HOST_CTL 0x%x\n", tmp);
243 #ifndef CONFIG_SCSI_AHCI_PLAT
244 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
245 tmp |= PCI_COMMAND_MASTER;
246 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
252 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
254 #ifndef CONFIG_SCSI_AHCI_PLAT
255 pci_dev_t pdev = probe_ent->dev;
258 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
259 u32 vers, cap, cap2, impl, speed;
263 vers = readl(mmio + HOST_VERSION);
264 cap = probe_ent->cap;
265 cap2 = readl(mmio + HOST_CAP2);
266 impl = probe_ent->port_map;
268 speed = (cap >> 20) & 0xf;
278 #ifdef CONFIG_SCSI_AHCI_PLAT
281 pci_read_config_word(pdev, 0x0a, &cc);
284 else if (cc == 0x0106)
286 else if (cc == 0x0104)
291 printf("AHCI %02x%02x.%02x%02x "
292 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
297 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
303 cap & (1 << 31) ? "64bit " : "",
304 cap & (1 << 30) ? "ncq " : "",
305 cap & (1 << 28) ? "ilck " : "",
306 cap & (1 << 27) ? "stag " : "",
307 cap & (1 << 26) ? "pm " : "",
308 cap & (1 << 25) ? "led " : "",
309 cap & (1 << 24) ? "clo " : "",
310 cap & (1 << 19) ? "nz " : "",
311 cap & (1 << 18) ? "only " : "",
312 cap & (1 << 17) ? "pmp " : "",
313 cap & (1 << 16) ? "fbss " : "",
314 cap & (1 << 15) ? "pio " : "",
315 cap & (1 << 14) ? "slum " : "",
316 cap & (1 << 13) ? "part " : "",
317 cap & (1 << 7) ? "ccc " : "",
318 cap & (1 << 6) ? "ems " : "",
319 cap & (1 << 5) ? "sxs " : "",
320 cap2 & (1 << 2) ? "apst " : "",
321 cap2 & (1 << 1) ? "nvmp " : "",
322 cap2 & (1 << 0) ? "boh " : "");
325 #ifndef CONFIG_SCSI_AHCI_PLAT
326 static int ahci_init_one(pci_dev_t pdev)
331 memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
333 probe_ent = malloc(sizeof(struct ahci_probe_ent));
334 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
335 probe_ent->dev = pdev;
337 probe_ent->host_flags = ATA_FLAG_SATA
342 probe_ent->pio_mask = 0x1f;
343 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
345 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
346 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
349 * JMicron-specific fixup:
350 * make sure we're in AHCI mode
352 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
353 if (vendor == 0x197b)
354 pci_write_config_byte(pdev, 0x41, 0xa1);
356 /* initialize adapter */
357 rc = ahci_host_init(probe_ent);
361 ahci_print_info(probe_ent);
370 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
372 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
374 struct ahci_ioports *pp = &(probe_ent->port[port]);
375 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
379 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
380 if (sg_count > AHCI_MAX_SG) {
381 printf("Error:Too much sg!\n");
385 for (i = 0; i < sg_count; i++) {
387 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
388 ahci_sg->addr_hi = 0;
389 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
390 (buf_len < MAX_DATA_BYTE_COUNT
392 : (MAX_DATA_BYTE_COUNT - 1)));
394 buf_len -= MAX_DATA_BYTE_COUNT;
401 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
403 pp->cmd_slot->opts = cpu_to_le32(opts);
404 pp->cmd_slot->status = 0;
405 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
406 pp->cmd_slot->tbl_addr_hi = 0;
410 #ifdef CONFIG_AHCI_SETFEATURES_XFER
411 static void ahci_set_feature(u8 port)
413 struct ahci_ioports *pp = &(probe_ent->port[port]);
414 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
415 u32 cmd_fis_len = 5; /* five dwords */
419 memset(fis, 0, sizeof(fis));
422 fis[2] = ATA_CMD_SETF;
423 fis[3] = SETFEATURES_XFER;
424 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
426 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
427 ahci_fill_cmd_slot(pp, cmd_fis_len);
428 ahci_dcache_flush_sata_cmd(pp);
429 writel(1, port_mmio + PORT_CMD_ISSUE);
430 readl(port_mmio + PORT_CMD_ISSUE);
432 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
433 printf("set feature error on port %d!\n", port);
439 static int ahci_port_start(u8 port)
441 struct ahci_ioports *pp = &(probe_ent->port[port]);
442 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
446 debug("Enter start port: %d\n", port);
447 port_status = readl(port_mmio + PORT_SCR_STAT);
448 debug("Port %d status: %x\n", port, port_status);
449 if ((port_status & 0xf) != 0x03) {
450 printf("No Link on this port!\n");
454 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
457 printf("No mem for table!\n");
461 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
462 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
465 * First item in chunk of DMA memory: 32-slot command table,
466 * 32 bytes each in size
469 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
470 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
471 mem += (AHCI_CMD_SLOT_SZ + 224);
474 * Second item: Received-FIS area
476 pp->rx_fis = virt_to_phys((void *)mem);
477 mem += AHCI_RX_FIS_SZ;
480 * Third item: data area for storing a single command
481 * and its scatter-gather table
483 pp->cmd_tbl = virt_to_phys((void *)mem);
484 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
486 mem += AHCI_CMD_TBL_HDR;
488 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
490 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
492 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
494 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
495 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
496 PORT_CMD_START, port_mmio + PORT_CMD);
498 debug("Exit start port %d\n", port);
504 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
505 int buf_len, u8 is_write)
508 struct ahci_ioports *pp = &(probe_ent->port[port]);
509 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
514 debug("Enter %s: for port %d\n", __func__, port);
516 if (port > probe_ent->n_ports) {
517 printf("Invalid port number %d\n", port);
521 port_status = readl(port_mmio + PORT_SCR_STAT);
522 if ((port_status & 0xf) != 0x03) {
523 debug("No Link on port %d!\n", port);
527 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
529 sg_count = ahci_fill_sg(port, buf, buf_len);
530 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
531 ahci_fill_cmd_slot(pp, opts);
533 ahci_dcache_flush_sata_cmd(pp);
534 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
536 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
538 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
539 printf("timeout exit!\n");
543 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
544 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
550 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
553 for (i = 0; i < len / 2; i++)
554 target[i] = swab16(src[i]);
555 return (char *)target;
559 static void dump_ataid(hd_driveid_t *ataid)
561 debug("(49)ataid->capability = 0x%x\n", ataid->capability);
562 debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
563 debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
564 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
565 debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
566 debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
567 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
568 debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
569 debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
570 debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
571 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
572 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
573 debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
574 debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
575 debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
580 * SCSI INQUIRY command operation.
582 static int ata_scsiop_inquiry(ccb *pccb)
587 0x5, /* claim SPC-3 version compatibility */
595 /* Clean ccb data buffer */
596 memset(pccb->pdata, 0, pccb->datalen);
598 memcpy(pccb->pdata, hdr, sizeof(hdr));
600 if (pccb->datalen <= 35)
603 memset(fis, 0, sizeof(fis));
604 /* Construct the FIS */
605 fis[0] = 0x27; /* Host to device FIS. */
606 fis[1] = 1 << 7; /* Command FIS. */
607 fis[2] = ATA_CMD_IDENT; /* Command byte. */
609 /* Read id from sata */
611 if (!(tmpid = malloc(sizeof(hd_driveid_t))))
614 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,
615 sizeof(hd_driveid_t), 0)) {
616 debug("scsi_ahci: SCSI inquiry command failure.\n");
622 ataid[port] = (hd_driveid_t *) tmpid;
624 memcpy(&pccb->pdata[8], "ATA ", 8);
625 ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
626 ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
628 dump_ataid(ataid[port]);
634 * SCSI READ10/WRITE10 command operation.
636 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
641 u8 *user_buffer = pccb->pdata;
642 u32 user_buffer_size = pccb->datalen;
644 /* Retrieve the base LBA number from the ccb structure. */
645 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
646 lba = be32_to_cpu(lba);
649 * And the number of blocks.
651 * For 10-byte and 16-byte SCSI R/W commands, transfer
652 * length 0 means transfer 0 block of data.
653 * However, for ATA R/W commands, sector count 0 means
654 * 256 or 65536 sectors, not 0 sectors as in SCSI.
656 * WARNING: one or two older ATA drives treat 0 as 0...
658 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
660 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
661 is_write ? "write" : "read", (unsigned)lba, blocks);
664 memset(fis, 0, sizeof(fis));
665 fis[0] = 0x27; /* Host to device FIS. */
666 fis[1] = 1 << 7; /* Command FIS. */
667 /* Command byte (read/write). */
668 fis[2] = is_write ? ATA_CMD_WR_DMA : ATA_CMD_RD_DMA;
671 u16 now_blocks; /* number of blocks per iteration */
672 u32 transfer_size; /* number of bytes per iteration */
674 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
676 transfer_size = ATA_BLOCKSIZE * now_blocks;
677 if (transfer_size > user_buffer_size) {
678 printf("scsi_ahci: Error: buffer too small.\n");
682 /* LBA address, only support LBA28 in this driver */
683 fis[4] = (lba >> 0) & 0xff;
684 fis[5] = (lba >> 8) & 0xff;
685 fis[6] = (lba >> 16) & 0xff;
686 fis[7] = ((lba >> 24) & 0xf) | 0xe0;
688 /* Block (sector) count */
689 fis[12] = (now_blocks >> 0) & 0xff;
690 fis[13] = (now_blocks >> 8) & 0xff;
692 /* Read/Write from ahci */
693 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
694 user_buffer, user_buffer_size,
696 debug("scsi_ahci: SCSI %s10 command failure.\n",
697 is_write ? "WRITE" : "READ");
700 user_buffer += transfer_size;
701 user_buffer_size -= transfer_size;
702 blocks -= now_blocks;
711 * SCSI READ CAPACITY10 command operation.
713 static int ata_scsiop_read_capacity10(ccb *pccb)
718 if (!ataid[pccb->target]) {
719 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
721 "\tPlease run SCSI commmand INQUIRY firstly!\n");
725 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
726 if (cap == 0xfffffff) {
727 unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;
728 if (cap48[2] || cap48[3]) {
731 cap = (le16_to_cpu(cap48[1]) << 16) |
732 (le16_to_cpu(cap48[0]));
736 cap = cpu_to_be32(cap);
737 memcpy(pccb->pdata, &cap, sizeof(cap));
739 block_size = cpu_to_be32((u32)512);
740 memcpy(&pccb->pdata[4], &block_size, 4);
747 * SCSI READ CAPACITY16 command operation.
749 static int ata_scsiop_read_capacity16(ccb *pccb)
754 if (!ataid[pccb->target]) {
755 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
757 "\tPlease run SCSI commmand INQUIRY firstly!\n");
761 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
762 if (cap == 0xfffffff) {
763 memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));
764 cap = le64_to_cpu(cap);
767 cap = cpu_to_be64(cap);
768 memcpy(pccb->pdata, &cap, sizeof(cap));
770 block_size = cpu_to_be64((u64)512);
771 memcpy(&pccb->pdata[8], &block_size, 8);
778 * SCSI TEST UNIT READY command operation.
780 static int ata_scsiop_test_unit_ready(ccb *pccb)
782 return (ataid[pccb->target]) ? 0 : -EPERM;
786 int scsi_exec(ccb *pccb)
790 switch (pccb->cmd[0]) {
792 ret = ata_scsiop_read_write(pccb, 0);
795 ret = ata_scsiop_read_write(pccb, 1);
797 case SCSI_RD_CAPAC10:
798 ret = ata_scsiop_read_capacity10(pccb);
800 case SCSI_RD_CAPAC16:
801 ret = ata_scsiop_read_capacity16(pccb);
804 ret = ata_scsiop_test_unit_ready(pccb);
807 ret = ata_scsiop_inquiry(pccb);
810 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
815 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
823 void scsi_low_level_init(int busdevfunc)
828 #ifndef CONFIG_SCSI_AHCI_PLAT
829 ahci_init_one(busdevfunc);
832 linkmap = probe_ent->link_port_map;
834 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
835 if (((linkmap >> i) & 0x01)) {
836 if (ahci_port_start((u8) i)) {
837 printf("Can not start port %d\n", i);
840 #ifdef CONFIG_AHCI_SETFEATURES_XFER
841 ahci_set_feature((u8) i);
847 #ifdef CONFIG_SCSI_AHCI_PLAT
848 int ahci_init(u32 base)
853 memset(ataid, 0, sizeof(ataid));
855 probe_ent = malloc(sizeof(struct ahci_probe_ent));
856 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
858 probe_ent->host_flags = ATA_FLAG_SATA
863 probe_ent->pio_mask = 0x1f;
864 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
866 probe_ent->mmio_base = base;
868 /* initialize adapter */
869 rc = ahci_host_init(probe_ent);
873 ahci_print_info(probe_ent);
875 linkmap = probe_ent->link_port_map;
877 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
878 if (((linkmap >> i) & 0x01)) {
879 if (ahci_port_start((u8) i)) {
880 printf("Can not start port %d\n", i);
883 #ifdef CONFIG_AHCI_SETFEATURES_XFER
884 ahci_set_feature((u8) i);
893 void scsi_bus_reset(void)
899 void scsi_print_error(ccb * pccb)
901 /*The ahci error info can be read in the ahci driver*/