2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference on libata and ahci drvier in kernel
15 #include <asm/processor.h>
16 #include <asm/errno.h>
22 #include <linux/ctype.h>
25 static int ata_io_flush(u8 port);
27 struct ahci_probe_ent *probe_ent = NULL;
28 u16 *ataid[AHCI_MAX_PORTS];
30 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
33 * Some controllers limit number of blocks they can read/write at once.
34 * Contemporary SSD devices work much faster if the read/write size is aligned
35 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
38 #ifndef MAX_SATA_BLOCKS_READ_WRITE
39 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
42 /* Maximum timeouts for each event */
43 #define WAIT_MS_SPINUP 20000
44 #define WAIT_MS_DATAIO 10000
45 #define WAIT_MS_FLUSH 5000
46 #define WAIT_MS_LINKUP 200
48 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
50 return base + 0x100 + (port * 0x80);
54 static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
55 unsigned int port_idx)
57 base = ahci_port_base(base, port_idx);
59 port->cmd_addr = base;
60 port->scr_addr = base + PORT_SCR;
64 #define msleep(a) udelay(a * 1000)
66 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
68 const unsigned long start = begin;
69 const unsigned long end = start + len;
71 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
72 flush_dcache_range(start, end);
76 * SATA controller DMAs to physical RAM. Ensure data from the
77 * controller is invalidated from dcache; next access comes from
80 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
82 const unsigned long start = begin;
83 const unsigned long end = start + len;
85 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
86 invalidate_dcache_range(start, end);
90 * Ensure data for SATA controller is flushed out of dcache and
91 * written to physical memory.
93 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
95 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
96 AHCI_PORT_PRIV_DMA_SZ);
99 static int waiting_for_cmd_completed(void __iomem *offset,
106 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
109 return (i < timeout_msec) ? 0 : -1;
112 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
116 void __iomem *port_mmio = probe_ent->port[port].port_mmio;
119 * Bring up SATA link.
120 * SATA link bringup time is usually less than 1 ms; only very
121 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
123 while (j < WAIT_MS_LINKUP) {
124 tmp = readl(port_mmio + PORT_SCR_STAT);
125 tmp &= PORT_SCR_STAT_DET_MASK;
126 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
134 #ifdef CONFIG_SUNXI_AHCI
135 /* The sunxi AHCI controller requires this undocumented setup */
136 static void sunxi_dma_init(void __iomem *port_mmio)
138 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
142 int ahci_reset(void __iomem *base)
145 u32 __iomem *host_ctl_reg = base + HOST_CTL;
146 u32 tmp = readl(host_ctl_reg); /* global controller reset */
148 if ((tmp & HOST_RESET) == 0)
149 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
152 * reset must complete within 1 second, or
153 * the hardware should be considered fried.
157 tmp = readl(host_ctl_reg);
159 } while ((i > 0) && (tmp & HOST_RESET));
162 printf("controller reset failed (0x%x)\n", tmp);
169 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
171 #ifndef CONFIG_SCSI_AHCI_PLAT
172 # ifdef CONFIG_DM_PCI
173 struct udevice *dev = probe_ent->dev;
174 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
176 pci_dev_t pdev = probe_ent->dev;
177 unsigned short vendor;
181 void __iomem *mmio = probe_ent->mmio_base;
182 u32 tmp, cap_save, cmd;
184 void __iomem *port_mmio;
187 debug("ahci_host_init: start\n");
189 cap_save = readl(mmio + HOST_CAP);
190 cap_save &= ((1 << 28) | (1 << 17));
191 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
193 ret = ahci_reset(probe_ent->mmio_base);
197 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
198 writel(cap_save, mmio + HOST_CAP);
199 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
201 #ifndef CONFIG_SCSI_AHCI_PLAT
202 # ifdef CONFIG_DM_PCI
203 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
206 dm_pci_read_config16(dev, 0x92, &tmp16);
207 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
210 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
212 if (vendor == PCI_VENDOR_ID_INTEL) {
214 pci_read_config_word(pdev, 0x92, &tmp16);
216 pci_write_config_word(pdev, 0x92, tmp16);
220 probe_ent->cap = readl(mmio + HOST_CAP);
221 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
222 port_map = probe_ent->port_map;
223 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
225 debug("cap 0x%x port_map 0x%x n_ports %d\n",
226 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
228 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
229 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
231 for (i = 0; i < probe_ent->n_ports; i++) {
232 if (!(port_map & (1 << i)))
234 probe_ent->port[i].port_mmio = ahci_port_base(mmio, i);
235 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
236 ahci_setup_port(&probe_ent->port[i], mmio, i);
238 /* make sure port is not active */
239 tmp = readl(port_mmio + PORT_CMD);
240 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
241 PORT_CMD_FIS_RX | PORT_CMD_START)) {
242 debug("Port %d is active. Deactivating.\n", i);
243 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
244 PORT_CMD_FIS_RX | PORT_CMD_START);
245 writel_with_flush(tmp, port_mmio + PORT_CMD);
247 /* spec says 500 msecs for each bit, so
248 * this is slightly incorrect.
253 #ifdef CONFIG_SUNXI_AHCI
254 sunxi_dma_init(port_mmio);
257 /* Add the spinup command to whatever mode bits may
258 * already be on in the command register.
260 cmd = readl(port_mmio + PORT_CMD);
261 cmd |= PORT_CMD_SPIN_UP;
262 writel_with_flush(cmd, port_mmio + PORT_CMD);
264 /* Bring up SATA link. */
265 ret = ahci_link_up(probe_ent, i);
267 printf("SATA link %d timeout.\n", i);
270 debug("SATA link ok.\n");
273 /* Clear error status */
274 tmp = readl(port_mmio + PORT_SCR_ERR);
276 writel(tmp, port_mmio + PORT_SCR_ERR);
278 debug("Spinning up device on SATA port %d... ", i);
281 while (j < WAIT_MS_SPINUP) {
282 tmp = readl(port_mmio + PORT_TFDATA);
283 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
286 tmp = readl(port_mmio + PORT_SCR_STAT);
287 tmp &= PORT_SCR_STAT_DET_MASK;
288 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
293 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
294 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
295 debug("SATA link %d down (COMINIT received), retrying...\n", i);
300 printf("Target spinup took %d ms.\n", j);
301 if (j == WAIT_MS_SPINUP)
306 tmp = readl(port_mmio + PORT_SCR_ERR);
307 debug("PORT_SCR_ERR 0x%x\n", tmp);
308 writel(tmp, port_mmio + PORT_SCR_ERR);
310 /* ack any pending irq events for this port */
311 tmp = readl(port_mmio + PORT_IRQ_STAT);
312 debug("PORT_IRQ_STAT 0x%x\n", tmp);
314 writel(tmp, port_mmio + PORT_IRQ_STAT);
316 writel(1 << i, mmio + HOST_IRQ_STAT);
318 /* register linkup ports */
319 tmp = readl(port_mmio + PORT_SCR_STAT);
320 debug("SATA port %d status: 0x%x\n", i, tmp);
321 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
322 probe_ent->link_port_map |= (0x01 << i);
325 tmp = readl(mmio + HOST_CTL);
326 debug("HOST_CTL 0x%x\n", tmp);
327 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
328 tmp = readl(mmio + HOST_CTL);
329 debug("HOST_CTL 0x%x\n", tmp);
330 #ifndef CONFIG_SCSI_AHCI_PLAT
331 # ifdef CONFIG_DM_PCI
332 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
333 tmp |= PCI_COMMAND_MASTER;
334 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
336 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
337 tmp |= PCI_COMMAND_MASTER;
338 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
345 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
347 #ifndef CONFIG_SCSI_AHCI_PLAT
348 # ifdef CONFIG_DM_PCI
349 struct udevice *dev = probe_ent->dev;
351 pci_dev_t pdev = probe_ent->dev;
355 void __iomem *mmio = probe_ent->mmio_base;
356 u32 vers, cap, cap2, impl, speed;
360 vers = readl(mmio + HOST_VERSION);
361 cap = probe_ent->cap;
362 cap2 = readl(mmio + HOST_CAP2);
363 impl = probe_ent->port_map;
365 speed = (cap >> 20) & 0xf;
375 #ifdef CONFIG_SCSI_AHCI_PLAT
378 # ifdef CONFIG_DM_PCI
379 dm_pci_read_config16(dev, 0x0a, &cc);
381 pci_read_config_word(pdev, 0x0a, &cc);
385 else if (cc == 0x0106)
387 else if (cc == 0x0104)
392 printf("AHCI %02x%02x.%02x%02x "
393 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
398 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
404 cap & (1 << 31) ? "64bit " : "",
405 cap & (1 << 30) ? "ncq " : "",
406 cap & (1 << 28) ? "ilck " : "",
407 cap & (1 << 27) ? "stag " : "",
408 cap & (1 << 26) ? "pm " : "",
409 cap & (1 << 25) ? "led " : "",
410 cap & (1 << 24) ? "clo " : "",
411 cap & (1 << 19) ? "nz " : "",
412 cap & (1 << 18) ? "only " : "",
413 cap & (1 << 17) ? "pmp " : "",
414 cap & (1 << 16) ? "fbss " : "",
415 cap & (1 << 15) ? "pio " : "",
416 cap & (1 << 14) ? "slum " : "",
417 cap & (1 << 13) ? "part " : "",
418 cap & (1 << 7) ? "ccc " : "",
419 cap & (1 << 6) ? "ems " : "",
420 cap & (1 << 5) ? "sxs " : "",
421 cap2 & (1 << 2) ? "apst " : "",
422 cap2 & (1 << 1) ? "nvmp " : "",
423 cap2 & (1 << 0) ? "boh " : "");
426 #ifndef CONFIG_SCSI_AHCI_PLAT
427 # ifdef CONFIG_DM_PCI
428 static int ahci_init_one(struct udevice *dev)
430 static int ahci_init_one(pci_dev_t dev)
436 probe_ent = malloc(sizeof(struct ahci_probe_ent));
438 printf("%s: No memory for probe_ent\n", __func__);
442 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
443 probe_ent->dev = dev;
445 probe_ent->host_flags = ATA_FLAG_SATA
450 probe_ent->pio_mask = 0x1f;
451 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
454 probe_ent->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
458 * JMicron-specific fixup:
459 * make sure we're in AHCI mode
461 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
462 if (vendor == 0x197b)
463 dm_pci_write_config8(dev, 0x41, 0xa1);
465 probe_ent->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
469 * JMicron-specific fixup:
470 * make sure we're in AHCI mode
472 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
473 if (vendor == 0x197b)
474 pci_write_config_byte(dev, 0x41, 0xa1);
477 debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
478 /* initialize adapter */
479 rc = ahci_host_init(probe_ent);
483 ahci_print_info(probe_ent);
492 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
494 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
496 struct ahci_ioports *pp = &(probe_ent->port[port]);
497 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
501 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
502 if (sg_count > AHCI_MAX_SG) {
503 printf("Error:Too much sg!\n");
507 for (i = 0; i < sg_count; i++) {
509 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
510 ahci_sg->addr_hi = 0;
511 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
512 (buf_len < MAX_DATA_BYTE_COUNT
514 : (MAX_DATA_BYTE_COUNT - 1)));
516 buf_len -= MAX_DATA_BYTE_COUNT;
523 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
525 pp->cmd_slot->opts = cpu_to_le32(opts);
526 pp->cmd_slot->status = 0;
527 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
528 #ifdef CONFIG_PHYS_64BIT
529 pp->cmd_slot->tbl_addr_hi =
530 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
534 static int wait_spinup(void __iomem *port_mmio)
539 start = get_timer(0);
541 tf_data = readl(port_mmio + PORT_TFDATA);
542 if (!(tf_data & ATA_BUSY))
544 } while (get_timer(start) < WAIT_MS_SPINUP);
549 static int ahci_port_start(u8 port)
551 struct ahci_ioports *pp = &(probe_ent->port[port]);
552 void __iomem *port_mmio = pp->port_mmio;
556 debug("Enter start port: %d\n", port);
557 port_status = readl(port_mmio + PORT_SCR_STAT);
558 debug("Port %d status: %x\n", port, port_status);
559 if ((port_status & 0xf) != 0x03) {
560 printf("No Link on this port!\n");
564 mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
567 printf("%s: No mem for table!\n", __func__);
571 /* Aligned to 2048-bytes */
572 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
573 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
576 * First item in chunk of DMA memory: 32-slot command table,
577 * 32 bytes each in size
580 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
581 debug("cmd_slot = %p\n", pp->cmd_slot);
582 mem += (AHCI_CMD_SLOT_SZ + 224);
585 * Second item: Received-FIS area
587 pp->rx_fis = virt_to_phys((void *)mem);
588 mem += AHCI_RX_FIS_SZ;
591 * Third item: data area for storing a single command
592 * and its scatter-gather table
594 pp->cmd_tbl = virt_to_phys((void *)mem);
595 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
597 mem += AHCI_CMD_TBL_HDR;
599 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
601 writel_with_flush((unsigned long)pp->cmd_slot,
602 port_mmio + PORT_LST_ADDR);
604 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
606 #ifdef CONFIG_SUNXI_AHCI
607 sunxi_dma_init(port_mmio);
610 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
611 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
612 PORT_CMD_START, port_mmio + PORT_CMD);
614 debug("Exit start port %d\n", port);
617 * Make sure interface is not busy based on error and status
618 * information from task file data register before proceeding
620 return wait_spinup(port_mmio);
624 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
625 int buf_len, u8 is_write)
628 struct ahci_ioports *pp = &(probe_ent->port[port]);
629 void __iomem *port_mmio = pp->port_mmio;
634 debug("Enter %s: for port %d\n", __func__, port);
636 if (port > probe_ent->n_ports) {
637 printf("Invalid port number %d\n", port);
641 port_status = readl(port_mmio + PORT_SCR_STAT);
642 if ((port_status & 0xf) != 0x03) {
643 debug("No Link on port %d!\n", port);
647 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
649 sg_count = ahci_fill_sg(port, buf, buf_len);
650 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
651 ahci_fill_cmd_slot(pp, opts);
653 ahci_dcache_flush_sata_cmd(pp);
654 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
656 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
658 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
659 WAIT_MS_DATAIO, 0x1)) {
660 printf("timeout exit!\n");
664 ahci_dcache_invalidate_range((unsigned long)buf,
665 (unsigned long)buf_len);
666 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
672 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
675 for (i = 0; i < len / 2; i++)
676 target[i] = swab16(src[i]);
677 return (char *)target;
681 * SCSI INQUIRY command operation.
683 static int ata_scsiop_inquiry(ccb *pccb)
685 static const u8 hdr[] = {
688 0x5, /* claim SPC-3 version compatibility */
694 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
697 /* Clean ccb data buffer */
698 memset(pccb->pdata, 0, pccb->datalen);
700 memcpy(pccb->pdata, hdr, sizeof(hdr));
702 if (pccb->datalen <= 35)
705 memset(fis, 0, sizeof(fis));
706 /* Construct the FIS */
707 fis[0] = 0x27; /* Host to device FIS. */
708 fis[1] = 1 << 7; /* Command FIS. */
709 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
711 /* Read id from sata */
714 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
715 ATA_ID_WORDS * 2, 0)) {
716 debug("scsi_ahci: SCSI inquiry command failure.\n");
721 ataid[port] = malloc(ATA_ID_WORDS * 2);
723 printf("%s: No memory for ataid[port]\n", __func__);
730 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
731 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
733 memcpy(&pccb->pdata[8], "ATA ", 8);
734 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
735 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
745 * SCSI READ10/WRITE10 command operation.
747 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
752 u8 *user_buffer = pccb->pdata;
753 u32 user_buffer_size = pccb->datalen;
755 /* Retrieve the base LBA number from the ccb structure. */
756 if (pccb->cmd[0] == SCSI_READ16) {
757 memcpy(&lba, pccb->cmd + 2, 8);
758 lba = be64_to_cpu(lba);
761 memcpy(&temp, pccb->cmd + 2, 4);
762 lba = be32_to_cpu(temp);
766 * Retrieve the base LBA number and the block count from
769 * For 10-byte and 16-byte SCSI R/W commands, transfer
770 * length 0 means transfer 0 block of data.
771 * However, for ATA R/W commands, sector count 0 means
772 * 256 or 65536 sectors, not 0 sectors as in SCSI.
774 * WARNING: one or two older ATA drives treat 0 as 0...
776 if (pccb->cmd[0] == SCSI_READ16)
777 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
779 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
781 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
782 is_write ? "write" : "read", blocks, lba);
785 memset(fis, 0, sizeof(fis));
786 fis[0] = 0x27; /* Host to device FIS. */
787 fis[1] = 1 << 7; /* Command FIS. */
788 /* Command byte (read/write). */
789 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
792 u16 now_blocks; /* number of blocks per iteration */
793 u32 transfer_size; /* number of bytes per iteration */
795 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
797 transfer_size = ATA_SECT_SIZE * now_blocks;
798 if (transfer_size > user_buffer_size) {
799 printf("scsi_ahci: Error: buffer too small.\n");
804 * LBA48 SATA command but only use 32bit address range within
805 * that (unless we've enabled 64bit LBA support). The next
806 * smaller command range (28bit) is too small.
808 fis[4] = (lba >> 0) & 0xff;
809 fis[5] = (lba >> 8) & 0xff;
810 fis[6] = (lba >> 16) & 0xff;
811 fis[7] = 1 << 6; /* device reg: set LBA mode */
812 fis[8] = ((lba >> 24) & 0xff);
813 #ifdef CONFIG_SYS_64BIT_LBA
814 if (pccb->cmd[0] == SCSI_READ16) {
815 fis[9] = ((lba >> 32) & 0xff);
816 fis[10] = ((lba >> 40) & 0xff);
820 fis[3] = 0xe0; /* features */
822 /* Block (sector) count */
823 fis[12] = (now_blocks >> 0) & 0xff;
824 fis[13] = (now_blocks >> 8) & 0xff;
826 /* Read/Write from ahci */
827 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
828 user_buffer, transfer_size,
830 debug("scsi_ahci: SCSI %s10 command failure.\n",
831 is_write ? "WRITE" : "READ");
835 /* If this transaction is a write, do a following flush.
836 * Writes in u-boot are so rare, and the logic to know when is
837 * the last write and do a flush only there is sufficiently
838 * difficult. Just do a flush after every write. This incurs,
839 * usually, one extra flush when the rare writes do happen.
842 if (-EIO == ata_io_flush(pccb->target))
845 user_buffer += transfer_size;
846 user_buffer_size -= transfer_size;
847 blocks -= now_blocks;
856 * SCSI READ CAPACITY10 command operation.
858 static int ata_scsiop_read_capacity10(ccb *pccb)
864 if (!ataid[pccb->target]) {
865 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
867 "\tPlease run SCSI command INQUIRY first!\n");
871 cap64 = ata_id_n_sectors(ataid[pccb->target]);
872 if (cap64 > 0x100000000ULL)
875 cap = cpu_to_be32(cap64);
876 memcpy(pccb->pdata, &cap, sizeof(cap));
878 block_size = cpu_to_be32((u32)512);
879 memcpy(&pccb->pdata[4], &block_size, 4);
886 * SCSI READ CAPACITY16 command operation.
888 static int ata_scsiop_read_capacity16(ccb *pccb)
893 if (!ataid[pccb->target]) {
894 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
896 "\tPlease run SCSI command INQUIRY first!\n");
900 cap = ata_id_n_sectors(ataid[pccb->target]);
901 cap = cpu_to_be64(cap);
902 memcpy(pccb->pdata, &cap, sizeof(cap));
904 block_size = cpu_to_be64((u64)512);
905 memcpy(&pccb->pdata[8], &block_size, 8);
912 * SCSI TEST UNIT READY command operation.
914 static int ata_scsiop_test_unit_ready(ccb *pccb)
916 return (ataid[pccb->target]) ? 0 : -EPERM;
920 int scsi_exec(ccb *pccb)
924 switch (pccb->cmd[0]) {
927 ret = ata_scsiop_read_write(pccb, 0);
930 ret = ata_scsiop_read_write(pccb, 1);
932 case SCSI_RD_CAPAC10:
933 ret = ata_scsiop_read_capacity10(pccb);
935 case SCSI_RD_CAPAC16:
936 ret = ata_scsiop_read_capacity16(pccb);
939 ret = ata_scsiop_test_unit_ready(pccb);
942 ret = ata_scsiop_inquiry(pccb);
945 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
950 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
958 void scsi_low_level_init(int busdevfunc)
963 #ifndef CONFIG_SCSI_AHCI_PLAT
964 # ifdef CONFIG_DM_PCI
968 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
973 ahci_init_one(busdevfunc);
977 linkmap = probe_ent->link_port_map;
979 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
980 if (((linkmap >> i) & 0x01)) {
981 if (ahci_port_start((u8) i)) {
982 printf("Can not start port %d\n", i);
989 #ifdef CONFIG_SCSI_AHCI_PLAT
990 int ahci_init(void __iomem *base)
995 probe_ent = malloc(sizeof(struct ahci_probe_ent));
997 printf("%s: No memory for probe_ent\n", __func__);
1001 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
1003 probe_ent->host_flags = ATA_FLAG_SATA
1004 | ATA_FLAG_NO_LEGACY
1007 | ATA_FLAG_NO_ATAPI;
1008 probe_ent->pio_mask = 0x1f;
1009 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
1011 probe_ent->mmio_base = base;
1013 /* initialize adapter */
1014 rc = ahci_host_init(probe_ent);
1018 ahci_print_info(probe_ent);
1020 linkmap = probe_ent->link_port_map;
1022 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
1023 if (((linkmap >> i) & 0x01)) {
1024 if (ahci_port_start((u8) i)) {
1025 printf("Can not start port %d\n", i);
1034 void __weak scsi_init(void)
1041 * In the general case of generic rotating media it makes sense to have a
1042 * flush capability. It probably even makes sense in the case of SSDs because
1043 * one cannot always know for sure what kind of internal cache/flush mechanism
1044 * is embodied therein. At first it was planned to invoke this after the last
1045 * write to disk and before rebooting. In practice, knowing, a priori, which
1046 * is the last write is difficult. Because writing to the disk in u-boot is
1047 * very rare, this flush command will be invoked after every block write.
1049 static int ata_io_flush(u8 port)
1052 struct ahci_ioports *pp = &(probe_ent->port[port]);
1053 void __iomem *port_mmio = pp->port_mmio;
1054 u32 cmd_fis_len = 5; /* five dwords */
1056 /* Preset the FIS */
1058 fis[0] = 0x27; /* Host to device FIS. */
1059 fis[1] = 1 << 7; /* Command FIS. */
1060 fis[2] = ATA_CMD_FLUSH_EXT;
1062 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1063 ahci_fill_cmd_slot(pp, cmd_fis_len);
1064 ahci_dcache_flush_sata_cmd(pp);
1065 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1067 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1068 WAIT_MS_FLUSH, 0x1)) {
1069 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1077 __weak void scsi_bus_reset(void)
1082 void scsi_print_error(ccb * pccb)
1084 /*The ahci error info can be read in the ahci driver*/