git.sur5r.net Git - u-boot/blob - drivers/clk/clk_rk3288.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/cru_rk3288.h>
  15 #include <asm/arch/grf_rk3288.h>
  16 #include <asm/arch/hardware.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include <dm/device-internal.h>
  19 #include <dm/lists.h>
  20 #include <dm/uclass-internal.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct rk3288_clk_plat {
  25         enum rk_clk_id clk_id;
  26 };
  27
  28 struct rk3288_clk_priv {
  29         struct rk3288_grf *grf;
  30         struct rk3288_cru *cru;
  31         ulong rate;
  32 };
  33
  34 struct pll_div {
  35         u32 nr;
  36         u32 nf;
  37         u32 no;
  38 };
  39
  40 enum {
  41         VCO_MAX_HZ      = 2200U * 1000000,
  42         VCO_MIN_HZ      = 440 * 1000000,
  43         OUTPUT_MAX_HZ   = 2200U * 1000000,
  44         OUTPUT_MIN_HZ   = 27500000,
  45         FREF_MAX_HZ     = 2200U * 1000000,
  46         FREF_MIN_HZ     = 269 * 1000000,
  47 };
  48
  49 enum {
  50         /* PLL CON0 */
  51         PLL_OD_MASK             = 0x0f,
  52
  53         /* PLL CON1 */
  54         PLL_NF_MASK             = 0x1fff,
  55
  56         /* PLL CON2 */
  57         PLL_BWADJ_MASK          = 0x0fff,
  58
  59         /* PLL CON3 */
  60         PLL_RESET_SHIFT         = 5,
  61
  62         /* CLKSEL1: pd bus clk pll sel: codec or general */
  63         PD_BUS_SEL_PLL_MASK     = 15,
  64         PD_BUS_SEL_CPLL         = 0,
  65         PD_BUS_SEL_GPLL,
  66
  67         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  68         PD_BUS_PCLK_DIV_SHIFT   = 12,
  69         PD_BUS_PCLK_DIV_MASK    = 7,
  70
  71         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  72         PD_BUS_HCLK_DIV_SHIFT   = 8,
  73         PD_BUS_HCLK_DIV_MASK    = 3,
  74
  75         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  76         PD_BUS_ACLK_DIV0_SHIFT  = 3,
  77         PD_BUS_ACLK_DIV0_MASK   = 0x1f,
  78         PD_BUS_ACLK_DIV1_SHIFT  = 0,
  79         PD_BUS_ACLK_DIV1_MASK   = 0x7,
  80
  81         /*
  82          * CLKSEL10
  83          * peripheral bus pclk div:
  84          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
  85          */
  86         PERI_SEL_PLL_MASK        = 1,
  87         PERI_SEL_PLL_SHIFT       = 15,
  88         PERI_SEL_CPLL           = 0,
  89         PERI_SEL_GPLL,
  90
  91         PERI_PCLK_DIV_SHIFT     = 12,
  92         PERI_PCLK_DIV_MASK      = 3,
  93
  94         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  95         PERI_HCLK_DIV_SHIFT     = 8,
  96         PERI_HCLK_DIV_MASK      = 3,
  97
  98         /*
  99          * peripheral bus aclk div:
 100          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
 101          */
 102         PERI_ACLK_DIV_SHIFT     = 0,
 103         PERI_ACLK_DIV_MASK      = 0x1f,
 104
 105         SOCSTS_DPLL_LOCK        = 1 << 5,
 106         SOCSTS_APLL_LOCK        = 1 << 6,
 107         SOCSTS_CPLL_LOCK        = 1 << 7,
 108         SOCSTS_GPLL_LOCK        = 1 << 8,
 109         SOCSTS_NPLL_LOCK        = 1 << 9,
 110 };
 111
 112 #define RATE_TO_DIV(input_rate, output_rate) \
 113         ((input_rate) / (output_rate) - 1);
 114
 115 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 116
 117 #define PLL_DIVISORS(hz, _nr, _no) {\
 118         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
 119         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
 120                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
 121                        "divisors on line " __stringify(__LINE__));
 122
 123 /* Keep divisors as low as possible to reduce jitter and power usage */
 124 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 125 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 126 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 127
 128 int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
 129 {
 130         struct udevice *dev;
 131
 132         for (uclass_find_first_device(UCLASS_CLK, &dev);
 133              dev;
 134              uclass_find_next_device(&dev)) {
 135                 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 136
 137                 if (plat->clk_id == clk_id) {
 138                         *devp = dev;
 139                         return device_probe(dev);
 140                 }
 141         }
 142
 143         return -ENODEV;
 144 }
 145
 146 void *rockchip_get_cru(void)
 147 {
 148         struct rk3288_clk_priv *priv;
 149         struct udevice *dev;
 150         int ret;
 151
 152         ret = rkclk_get_clk(CLK_GENERAL, &dev);
 153         if (ret)
 154                 return ERR_PTR(ret);
 155         priv = dev_get_priv(dev);
 156         return priv->cru;
 157 }
 158
 159 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 160                          const struct pll_div *div)
 161 {
 162         int pll_id = rk_pll_id(clk_id);
 163         struct rk3288_pll *pll = &cru->pll[pll_id];
 164         /* All PLLs have same VCO and output frequency range restrictions. */
 165         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
 166         uint output_hz = vco_hz / div->no;
 167
 168         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 169               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 170         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 171                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 172                (div->no == 1 || !(div->no % 2)));
 173
 174         /* enter reset */
 175         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 176
 177         rk_clrsetreg(&pll->con0,
 178                      CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
 179                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 180         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 181         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 182
 183         udelay(10);
 184
 185         /* return from reset */
 186         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 187
 188         return 0;
 189 }
 190
 191 static inline unsigned int log2(unsigned int value)
 192 {
 193         return fls(value) - 1;
 194 }
 195
 196 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
 197                                unsigned int hz)
 198 {
 199         static const struct pll_div dpll_cfg[] = {
 200                 {.nf = 25, .nr = 2, .no = 1},
 201                 {.nf = 400, .nr = 9, .no = 2},
 202                 {.nf = 500, .nr = 9, .no = 2},
 203                 {.nf = 100, .nr = 3, .no = 1},
 204         };
 205         int cfg;
 206
 207         switch (hz) {
 208         case 300000000:
 209                 cfg = 0;
 210                 break;
 211         case 533000000: /* actually 533.3P MHz */
 212                 cfg = 1;
 213                 break;
 214         case 666000000: /* actually 666.6P MHz */
 215                 cfg = 2;
 216                 break;
 217         case 800000000:
 218                 cfg = 3;
 219                 break;
 220         default:
 221                 debug("Unsupported SDRAM frequency");
 222                 return -EINVAL;
 223         }
 224
 225         /* pll enter slow-mode */
 226         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 227                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 228
 229         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
 230
 231         /* wait for pll lock */
 232         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
 233                 udelay(1);
 234
 235         /* PLL enter normal-mode */
 236         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 237                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 238
 239         return 0;
 240 }
 241
 242 #ifndef CONFIG_SPL_BUILD
 243 #define VCO_MAX_KHZ     2200000
 244 #define VCO_MIN_KHZ     440000
 245 #define FREF_MAX_KHZ    2200000
 246 #define FREF_MIN_KHZ    269
 247
 248 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 249 {
 250         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
 251         uint fref_khz;
 252         uint diff_khz, best_diff_khz;
 253         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 254         uint vco_khz;
 255         uint no = 1;
 256         uint freq_khz = freq_hz / 1000;
 257
 258         if (!freq_hz) {
 259                 printf("%s: the frequency can not be 0 Hz\n", __func__);
 260                 return -EINVAL;
 261         }
 262
 263         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 264         if (ext_div) {
 265                 *ext_div = DIV_ROUND_UP(no, max_no);
 266                 no = DIV_ROUND_UP(no, *ext_div);
 267         }
 268
 269         /* only even divisors (and 1) are supported */
 270         if (no > 1)
 271                 no = DIV_ROUND_UP(no, 2) * 2;
 272
 273         vco_khz = freq_khz * no;
 274         if (ext_div)
 275                 vco_khz *= *ext_div;
 276
 277         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 278                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
 279                        __func__, freq_hz);
 280                 return -1;
 281         }
 282
 283         div->no = no;
 284
 285         best_diff_khz = vco_khz;
 286         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 287                 fref_khz = ref_khz / nr;
 288                 if (fref_khz < FREF_MIN_KHZ)
 289                         break;
 290                 if (fref_khz > FREF_MAX_KHZ)
 291                         continue;
 292
 293                 nf = vco_khz / fref_khz;
 294                 if (nf >= max_nf)
 295                         continue;
 296                 diff_khz = vco_khz - nf * fref_khz;
 297                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 298                         nf++;
 299                         diff_khz = fref_khz - diff_khz;
 300                 }
 301
 302                 if (diff_khz >= best_diff_khz)
 303                         continue;
 304
 305                 best_diff_khz = diff_khz;
 306                 div->nr = nr;
 307                 div->nf = nf;
 308         }
 309
 310         if (best_diff_khz > 4 * 1000) {
 311                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
 312                        __func__, freq_hz, best_diff_khz * 1000);
 313                 return -EINVAL;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 320                                 int periph, unsigned int rate_hz)
 321 {
 322         struct pll_div npll_config = {0};
 323         u32 lcdc_div;
 324         int ret;
 325
 326         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
 327         if (ret)
 328                 return ret;
 329
 330         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 331                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 332         rkclk_set_pll(cru, CLK_NEW, &npll_config);
 333
 334         /* waiting for pll lock */
 335         while (1) {
 336                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 337                         break;
 338                 udelay(1);
 339         }
 340
 341         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 342                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 343
 344         /* vop dclk source clk: npll,dclk_div: 1 */
 345         switch (periph) {
 346         case DCLK_VOP0:
 347                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
 348                              (lcdc_div - 1) << 8 | 2 << 0);
 349                 break;
 350         case DCLK_VOP1:
 351                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
 352                              (lcdc_div - 1) << 8 | 2 << 6);
 353                 break;
 354         }
 355
 356         return 0;
 357 }
 358 #endif
 359
 360 #ifdef CONFIG_SPL_BUILD
 361 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 362 {
 363         u32 aclk_div;
 364         u32 hclk_div;
 365         u32 pclk_div;
 366
 367         /* pll enter slow-mode */
 368         rk_clrsetreg(&cru->cru_mode_con,
 369                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 370                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 371                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 372                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 373
 374         /* init pll */
 375         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 376         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 377
 378         /* waiting for pll lock */
 379         while ((readl(&grf->soc_status[1]) &
 380                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 381                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 382                 udelay(1);
 383
 384         /*
 385          * pd_bus clock pll source selection and
 386          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 387          */
 388         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 389         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 390         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 391         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 392                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
 393
 394         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 395         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 396                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
 397
 398         rk_clrsetreg(&cru->cru_clksel_con[1],
 399                      PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
 400                      PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
 401                      PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
 402                      PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
 403                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 404                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 405                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
 406                      0 << 0);
 407
 408         /*
 409          * peri clock pll source selection and
 410          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 411          */
 412         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 413         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 414
 415         hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 416         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 417                 PERI_ACLK_HZ && (hclk_div < 0x4));
 418
 419         pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 420         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 421                 PERI_ACLK_HZ && (pclk_div < 0x4));
 422
 423         rk_clrsetreg(&cru->cru_clksel_con[10],
 424                      PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
 425                      PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
 426                      PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
 427                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 428                      pclk_div << PERI_PCLK_DIV_SHIFT |
 429                      hclk_div << PERI_HCLK_DIV_SHIFT |
 430                      aclk_div << PERI_ACLK_DIV_SHIFT);
 431
 432         /* PLL enter normal-mode */
 433         rk_clrsetreg(&cru->cru_mode_con,
 434                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 435                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 436                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 437                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 438 }
 439 #endif
 440
 441 /* Get pll rate by id */
 442 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
 443                                    enum rk_clk_id clk_id)
 444 {
 445         uint32_t nr, no, nf;
 446         uint32_t con;
 447         int pll_id = rk_pll_id(clk_id);
 448         struct rk3288_pll *pll = &cru->pll[pll_id];
 449         static u8 clk_shift[CLK_COUNT] = {
 450                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 451                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
 452         };
 453         uint shift;
 454
 455         con = readl(&cru->cru_mode_con);
 456         shift = clk_shift[clk_id];
 457         switch ((con >> shift) & APLL_MODE_MASK) {
 458         case APLL_MODE_SLOW:
 459                 return OSC_HZ;
 460         case APLL_MODE_NORMAL:
 461                 /* normal mode */
 462                 con = readl(&pll->con0);
 463                 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
 464                 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
 465                 con = readl(&pll->con1);
 466                 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
 467
 468                 return (24 * nf / (nr * no)) * 1000000;
 469         case APLL_MODE_DEEP:
 470         default:
 471                 return 32768;
 472         }
 473 }
 474
 475 static ulong rk3288_clk_get_rate(struct udevice *dev)
 476 {
 477         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 478         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 479
 480         debug("%s\n", dev->name);
 481         return rkclk_pll_get_rate(priv->cru, plat->clk_id);
 482 }
 483
 484 static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
 485 {
 486         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 487         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 488
 489         debug("%s\n", dev->name);
 490         switch (plat->clk_id) {
 491         case CLK_DDR:
 492                 rkclk_configure_ddr(priv->cru, priv->grf, rate);
 493                 break;
 494         default:
 495                 return -ENOENT;
 496         }
 497
 498         return 0;
 499 }
 500
 501 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 502                                   int periph)
 503 {
 504         uint src_rate;
 505         uint div, mux;
 506         u32 con;
 507
 508         switch (periph) {
 509         case HCLK_EMMC:
 510                 con = readl(&cru->cru_clksel_con[12]);
 511                 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
 512                 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 513                 break;
 514         case HCLK_SDMMC:
 515                 con = readl(&cru->cru_clksel_con[11]);
 516                 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
 517                 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
 518                 break;
 519         case HCLK_SDIO0:
 520                 con = readl(&cru->cru_clksel_con[12]);
 521                 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
 522                 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
 523                 break;
 524         default:
 525                 return -EINVAL;
 526         }
 527
 528         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 529         return DIV_TO_RATE(src_rate, div);
 530 }
 531
 532 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 533                                   int  periph, uint freq)
 534 {
 535         int src_clk_div;
 536         int mux;
 537
 538         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 539         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 540
 541         if (src_clk_div > 0x3f) {
 542                 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
 543                 mux = EMMC_PLL_SELECT_24MHZ;
 544                 assert((int)EMMC_PLL_SELECT_24MHZ ==
 545                        (int)MMC0_PLL_SELECT_24MHZ);
 546         } else {
 547                 mux = EMMC_PLL_SELECT_GENERAL;
 548                 assert((int)EMMC_PLL_SELECT_GENERAL ==
 549                        (int)MMC0_PLL_SELECT_GENERAL);
 550         }
 551         switch (periph) {
 552         case HCLK_EMMC:
 553                 rk_clrsetreg(&cru->cru_clksel_con[12],
 554                              EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 555                              EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 556                              mux << EMMC_PLL_SHIFT |
 557                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 558                 break;
 559         case HCLK_SDMMC:
 560                 rk_clrsetreg(&cru->cru_clksel_con[11],
 561                              MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 562                              MMC0_DIV_MASK << MMC0_DIV_SHIFT,
 563                              mux << MMC0_PLL_SHIFT |
 564                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 565                 break;
 566         case HCLK_SDIO0:
 567                 rk_clrsetreg(&cru->cru_clksel_con[12],
 568                              SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
 569                              SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
 570                              mux << SDIO0_PLL_SHIFT |
 571                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 572                 break;
 573         default:
 574                 return -EINVAL;
 575         }
 576
 577         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 578 }
 579
 580 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 581                                   int periph)
 582 {
 583         uint div, mux;
 584         u32 con;
 585
 586         switch (periph) {
 587         case SCLK_SPI0:
 588                 con = readl(&cru->cru_clksel_con[25]);
 589                 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
 590                 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
 591                 break;
 592         case SCLK_SPI1:
 593                 con = readl(&cru->cru_clksel_con[25]);
 594                 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
 595                 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
 596                 break;
 597         case SCLK_SPI2:
 598                 con = readl(&cru->cru_clksel_con[39]);
 599                 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
 600                 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
 601                 break;
 602         default:
 603                 return -EINVAL;
 604         }
 605         assert(mux == SPI0_PLL_SELECT_GENERAL);
 606
 607         return DIV_TO_RATE(gclk_rate, div);
 608 }
 609
 610 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 611                                   int periph, uint freq)
 612 {
 613         int src_clk_div;
 614
 615         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
 616         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 617         switch (periph) {
 618         case SCLK_SPI0:
 619                 rk_clrsetreg(&cru->cru_clksel_con[25],
 620                              SPI0_PLL_MASK << SPI0_PLL_SHIFT |
 621                              SPI0_DIV_MASK << SPI0_DIV_SHIFT,
 622                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 623                              src_clk_div << SPI0_DIV_SHIFT);
 624                 break;
 625         case SCLK_SPI1:
 626                 rk_clrsetreg(&cru->cru_clksel_con[25],
 627                              SPI1_PLL_MASK << SPI1_PLL_SHIFT |
 628                              SPI1_DIV_MASK << SPI1_DIV_SHIFT,
 629                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 630                              src_clk_div << SPI1_DIV_SHIFT);
 631                 break;
 632         case SCLK_SPI2:
 633                 rk_clrsetreg(&cru->cru_clksel_con[39],
 634                              SPI2_PLL_MASK << SPI2_PLL_SHIFT |
 635                              SPI2_DIV_MASK << SPI2_DIV_SHIFT,
 636                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 637                              src_clk_div << SPI2_DIV_SHIFT);
 638                 break;
 639         default:
 640                 return -EINVAL;
 641         }
 642
 643         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 644 }
 645
 646 static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
 647 {
 648         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 649         struct udevice *gclk;
 650         ulong new_rate, gclk_rate;
 651         int ret;
 652
 653         ret = rkclk_get_clk(CLK_GENERAL, &gclk);
 654         if (ret)
 655                 return ret;
 656         gclk_rate = clk_get_rate(gclk);
 657         switch (periph) {
 658         case HCLK_EMMC:
 659         case HCLK_SDMMC:
 660         case HCLK_SDIO0:
 661                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
 662                 break;
 663         case SCLK_SPI0:
 664         case SCLK_SPI1:
 665         case SCLK_SPI2:
 666                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph);
 667                 break;
 668         case PCLK_I2C0:
 669         case PCLK_I2C1:
 670         case PCLK_I2C2:
 671         case PCLK_I2C3:
 672         case PCLK_I2C4:
 673         case PCLK_I2C5:
 674                 return gclk_rate;
 675         default:
 676                 return -ENOENT;
 677         }
 678
 679         return new_rate;
 680 }
 681
 682 static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 683 {
 684         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 685         struct rk3288_cru *cru = priv->cru;
 686         struct udevice *gclk;
 687         ulong new_rate, gclk_rate;
 688         int ret;
 689
 690         ret = rkclk_get_clk(CLK_GENERAL, &gclk);
 691         if (ret)
 692                 return ret;
 693         gclk_rate = clk_get_rate(gclk);
 694         switch (periph) {
 695         case HCLK_EMMC:
 696         case HCLK_SDMMC:
 697         case HCLK_SDIO0:
 698                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, periph, rate);
 699                 break;
 700         case SCLK_SPI0:
 701         case SCLK_SPI1:
 702         case SCLK_SPI2:
 703                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
 704                 break;
 705 #ifndef CONFIG_SPL_BUILD
 706         case DCLK_VOP0:
 707         case DCLK_VOP1:
 708                 new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
 709                 break;
 710         case SCLK_EDP_24M:
 711                 /* clk_edp_24M source: 24M */
 712                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
 713
 714                 /* rst edp */
 715                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
 716                 udelay(1);
 717                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
 718                 new_rate = rate;
 719                 break;
 720         case ACLK_VOP0:
 721         case ACLK_VOP1: {
 722                 u32 div;
 723
 724                 /* vop aclk source clk: cpll */
 725                 div = CPLL_HZ / rate;
 726                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 727
 728                 switch (periph) {
 729                 case ACLK_VOP0:
 730                         rk_clrsetreg(&cru->cru_clksel_con[31],
 731                                      3 << 6 | 0x1f << 0,
 732                                      0 << 6 | (div - 1) << 0);
 733                         break;
 734                 case ACLK_VOP1:
 735                         rk_clrsetreg(&cru->cru_clksel_con[31],
 736                                      3 << 14 | 0x1f << 8,
 737                                      0 << 14 | (div - 1) << 8);
 738                         break;
 739                 }
 740                 new_rate = rate;
 741                 break;
 742         }
 743         case PCLK_HDMI_CTRL:
 744                 /* enable pclk hdmi ctrl */
 745                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
 746
 747                 /* software reset hdmi */
 748                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
 749                 udelay(1);
 750                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
 751                 new_rate = rate;
 752                 break;
 753 #endif
 754         default:
 755                 return -ENOENT;
 756         }
 757
 758         return new_rate;
 759 }
 760
 761 static struct clk_ops rk3288_clk_ops = {
 762         .get_rate       = rk3288_clk_get_rate,
 763         .set_rate       = rk3288_clk_set_rate,
 764         .set_periph_rate = rk3288_set_periph_rate,
 765         .get_periph_rate = rk3288_get_periph_rate,
 766 };
 767
 768 static int rk3288_clk_probe(struct udevice *dev)
 769 {
 770         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 771         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 772
 773         if (plat->clk_id != CLK_OSC) {
 774                 struct rk3288_clk_priv *parent_priv = dev_get_priv(dev->parent);
 775
 776                 priv->cru = parent_priv->cru;
 777                 priv->grf = parent_priv->grf;
 778                 return 0;
 779         }
 780         priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
 781         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 782 #ifdef CONFIG_SPL_BUILD
 783         rkclk_init(priv->cru, priv->grf);
 784 #endif
 785
 786         return 0;
 787 }
 788
 789 static const char *const clk_name[CLK_COUNT] = {
 790         "osc",
 791         "apll",
 792         "dpll",
 793         "cpll",
 794         "gpll",
 795         "npll",
 796 };
 797
 798 static int rk3288_clk_bind(struct udevice *dev)
 799 {
 800         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 801         int pll, ret;
 802
 803         /* We only need to set up the root clock */
 804         if (dev->of_offset == -1) {
 805                 plat->clk_id = CLK_OSC;
 806                 return 0;
 807         }
 808
 809         /* Create devices for P main clocks */
 810         for (pll = 1; pll < CLK_COUNT; pll++) {
 811                 struct udevice *child;
 812                 struct rk3288_clk_plat *cplat;
 813
 814                 debug("%s %s\n", __func__, clk_name[pll]);
 815                 ret = device_bind_driver(dev, "clk_rk3288", clk_name[pll],
 816                                          &child);
 817                 if (ret)
 818                         return ret;
 819                 cplat = dev_get_platdata(child);
 820                 cplat->clk_id = pll;
 821         }
 822
 823         /* The reset driver does not have a device node, so bind it here */
 824         ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev);
 825         if (ret)
 826                 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
 827
 828         return 0;
 829 }
 830
 831 static const struct udevice_id rk3288_clk_ids[] = {
 832         { .compatible = "rockchip,rk3288-cru" },
 833         { }
 834 };
 835
 836 U_BOOT_DRIVER(clk_rk3288) = {
 837         .name           = "clk_rk3288",
 838         .id             = UCLASS_CLK,
 839         .of_match       = rk3288_clk_ids,
 840         .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
 841         .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
 842         .ops            = &rk3288_clk_ops,
 843         .bind           = rk3288_clk_bind,
 844         .probe          = rk3288_clk_probe,
 845 };