git.sur5r.net Git - u-boot/blob - drivers/clk/clk_rk3288.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/cru_rk3288.h>
  15 #include <asm/arch/grf_rk3288.h>
  16 #include <asm/arch/hardware.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include <dm/device-internal.h>
  19 #include <dm/lists.h>
  20 #include <dm/uclass-internal.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct rk3288_clk_plat {
  25         enum rk_clk_id clk_id;
  26 };
  27
  28 struct rk3288_clk_priv {
  29         struct rk3288_grf *grf;
  30         struct rk3288_cru *cru;
  31         ulong rate;
  32 };
  33
  34 struct pll_div {
  35         u32 nr;
  36         u32 nf;
  37         u32 no;
  38 };
  39
  40 enum {
  41         VCO_MAX_HZ      = 2200U * 1000000,
  42         VCO_MIN_HZ      = 440 * 1000000,
  43         OUTPUT_MAX_HZ   = 2200U * 1000000,
  44         OUTPUT_MIN_HZ   = 27500000,
  45         FREF_MAX_HZ     = 2200U * 1000000,
  46         FREF_MIN_HZ     = 269 * 1000000,
  47 };
  48
  49 enum {
  50         /* PLL CON0 */
  51         PLL_OD_MASK             = 0x0f,
  52
  53         /* PLL CON1 */
  54         PLL_NF_MASK             = 0x1fff,
  55
  56         /* PLL CON2 */
  57         PLL_BWADJ_MASK          = 0x0fff,
  58
  59         /* PLL CON3 */
  60         PLL_RESET_SHIFT         = 5,
  61
  62         /* CLKSEL1: pd bus clk pll sel: codec or general */
  63         PD_BUS_SEL_PLL_MASK     = 15,
  64         PD_BUS_SEL_CPLL         = 0,
  65         PD_BUS_SEL_GPLL,
  66
  67         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  68         PD_BUS_PCLK_DIV_SHIFT   = 12,
  69         PD_BUS_PCLK_DIV_MASK    = 7,
  70
  71         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  72         PD_BUS_HCLK_DIV_SHIFT   = 8,
  73         PD_BUS_HCLK_DIV_MASK    = 3,
  74
  75         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  76         PD_BUS_ACLK_DIV0_SHIFT  = 3,
  77         PD_BUS_ACLK_DIV0_MASK   = 0x1f,
  78         PD_BUS_ACLK_DIV1_SHIFT  = 0,
  79         PD_BUS_ACLK_DIV1_MASK   = 0x7,
  80
  81         /*
  82          * CLKSEL10
  83          * peripheral bus pclk div:
  84          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
  85          */
  86         PERI_PCLK_DIV_SHIFT     = 12,
  87         PERI_PCLK_DIV_MASK      = 7,
  88
  89         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  90         PERI_HCLK_DIV_SHIFT     = 8,
  91         PERI_HCLK_DIV_MASK      = 3,
  92
  93         /*
  94          * peripheral bus aclk div:
  95          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
  96          */
  97         PERI_ACLK_DIV_SHIFT     = 0,
  98         PERI_ACLK_DIV_MASK      = 0x1f,
  99
 100         SOCSTS_DPLL_LOCK        = 1 << 5,
 101         SOCSTS_APLL_LOCK        = 1 << 6,
 102         SOCSTS_CPLL_LOCK        = 1 << 7,
 103         SOCSTS_GPLL_LOCK        = 1 << 8,
 104         SOCSTS_NPLL_LOCK        = 1 << 9,
 105 };
 106
 107 #define RATE_TO_DIV(input_rate, output_rate) \
 108         ((input_rate) / (output_rate) - 1);
 109
 110 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 111
 112 #define PLL_DIVISORS(hz, _nr, _no) {\
 113         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
 114         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
 115                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
 116                        "divisors on line " __stringify(__LINE__));
 117
 118 /* Keep divisors as low as possible to reduce jitter and power usage */
 119 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 120 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 121 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 122
 123 int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
 124 {
 125         struct udevice *dev;
 126
 127         for (uclass_find_first_device(UCLASS_CLK, &dev);
 128              dev;
 129              uclass_find_next_device(&dev)) {
 130                 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 131
 132                 if (plat->clk_id == clk_id) {
 133                         *devp = dev;
 134                         return device_probe(dev);
 135                 }
 136         }
 137
 138         return -ENODEV;
 139 }
 140
 141 void *rockchip_get_cru(void)
 142 {
 143         struct rk3288_clk_priv *priv;
 144         struct udevice *dev;
 145         int ret;
 146
 147         ret = rkclk_get_clk(CLK_GENERAL, &dev);
 148         if (ret)
 149                 return ERR_PTR(ret);
 150         priv = dev_get_priv(dev);
 151         return priv->cru;
 152 }
 153
 154 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 155                          const struct pll_div *div)
 156 {
 157         int pll_id = rk_pll_id(clk_id);
 158         struct rk3288_pll *pll = &cru->pll[pll_id];
 159         /* All PLLs have same VCO and output frequency range restrictions. */
 160         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
 161         uint output_hz = vco_hz / div->no;
 162
 163         debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 164               pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 165         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 166                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 167                (div->no == 1 || !(div->no % 2)));
 168
 169         /* enter rest */
 170         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 171
 172         rk_clrsetreg(&pll->con0,
 173                      CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
 174                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 175         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 176         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 177
 178         udelay(10);
 179
 180         /* return form rest */
 181         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 182
 183         return 0;
 184 }
 185
 186 static inline unsigned int log2(unsigned int value)
 187 {
 188         return fls(value) - 1;
 189 }
 190
 191 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
 192                                unsigned int hz)
 193 {
 194         static const struct pll_div dpll_cfg[] = {
 195                 {.nf = 25, .nr = 2, .no = 1},
 196                 {.nf = 400, .nr = 9, .no = 2},
 197                 {.nf = 500, .nr = 9, .no = 2},
 198                 {.nf = 100, .nr = 3, .no = 1},
 199         };
 200         int cfg;
 201
 202         debug("%s: cru=%p, grf=%p, hz=%u\n", __func__, cru, grf, hz);
 203         switch (hz) {
 204         case 300000000:
 205                 cfg = 0;
 206                 break;
 207         case 533000000: /* actually 533.3P MHz */
 208                 cfg = 1;
 209                 break;
 210         case 666000000: /* actually 666.6P MHz */
 211                 cfg = 2;
 212                 break;
 213         case 800000000:
 214                 cfg = 3;
 215                 break;
 216         default:
 217                 debug("Unsupported SDRAM frequency, add to clock.c!");
 218                 return -EINVAL;
 219         }
 220
 221         /* pll enter slow-mode */
 222         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 223                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 224
 225         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
 226
 227         /* wait for pll lock */
 228         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
 229                 udelay(1);
 230
 231         /* PLL enter normal-mode */
 232         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 233                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 234
 235         return 0;
 236 }
 237
 238 #ifndef CONFIG_SPL_BUILD
 239 #define VCO_MAX_KHZ     2200000
 240 #define VCO_MIN_KHZ     440000
 241 #define FREF_MAX_KHZ    2200000
 242 #define FREF_MIN_KHZ    269
 243
 244 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 245 {
 246         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
 247         uint fref_khz;
 248         uint diff_khz, best_diff_khz;
 249         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 250         uint vco_khz;
 251         uint no = 1;
 252         uint freq_khz = freq_hz / 1000;
 253
 254         if (!freq_hz) {
 255                 printf("%s: the frequency can not be 0 Hz\n", __func__);
 256                 return -EINVAL;
 257         }
 258
 259         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 260         if (ext_div) {
 261                 *ext_div = DIV_ROUND_UP(no, max_no);
 262                 no = DIV_ROUND_UP(no, *ext_div);
 263         }
 264
 265         /* only even divisors (and 1) are supported */
 266         if (no > 1)
 267                 no = DIV_ROUND_UP(no, 2) * 2;
 268
 269         vco_khz = freq_khz * no;
 270         if (ext_div)
 271                 vco_khz *= *ext_div;
 272
 273         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 274                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
 275                        __func__, freq_hz);
 276                 return -1;
 277         }
 278
 279         div->no = no;
 280
 281         best_diff_khz = vco_khz;
 282         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 283                 fref_khz = ref_khz / nr;
 284                 if (fref_khz < FREF_MIN_KHZ)
 285                         break;
 286                 if (fref_khz > FREF_MAX_KHZ)
 287                         continue;
 288
 289                 nf = vco_khz / fref_khz;
 290                 if (nf >= max_nf)
 291                         continue;
 292                 diff_khz = vco_khz - nf * fref_khz;
 293                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 294                         nf++;
 295                         diff_khz = fref_khz - diff_khz;
 296                 }
 297
 298                 if (diff_khz >= best_diff_khz)
 299                         continue;
 300
 301                 best_diff_khz = diff_khz;
 302                 div->nr = nr;
 303                 div->nf = nf;
 304         }
 305
 306         if (best_diff_khz > 4 * 1000) {
 307                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
 308                        __func__, freq_hz, best_diff_khz * 1000);
 309                 return -EINVAL;
 310         }
 311
 312         return 0;
 313 }
 314
 315 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 316                                 int periph, unsigned int rate_hz)
 317 {
 318         struct pll_div npll_config = {0};
 319         u32 lcdc_div;
 320         int ret;
 321
 322         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
 323         if (ret)
 324                 return ret;
 325
 326         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 327                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 328         rkclk_set_pll(cru, CLK_NEW, &npll_config);
 329
 330         /* waiting for pll lock */
 331         while (1) {
 332                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 333                         break;
 334                 udelay(1);
 335         }
 336
 337         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 338                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 339
 340         /* vop dclk source clk: npll,dclk_div: 1 */
 341         switch (periph) {
 342         case DCLK_VOP0:
 343                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
 344                              (lcdc_div - 1) << 8 | 2 << 0);
 345                 break;
 346         case DCLK_VOP1:
 347                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
 348                              (lcdc_div - 1) << 8 | 2 << 6);
 349                 break;
 350         }
 351
 352         return 0;
 353 }
 354 #endif
 355
 356 #ifdef CONFIG_SPL_BUILD
 357 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 358 {
 359         u32 aclk_div;
 360         u32 hclk_div;
 361         u32 pclk_div;
 362
 363         /* pll enter slow-mode */
 364         rk_clrsetreg(&cru->cru_mode_con,
 365                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 366                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 367                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 368                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 369
 370         /* init pll */
 371         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 372         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 373
 374         /* waiting for pll lock */
 375         while ((readl(&grf->soc_status[1]) &
 376                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 377                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 378                 udelay(1);
 379
 380         /*
 381          * pd_bus clock pll source selection and
 382          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 383          */
 384         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 385         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 386         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 387         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 388                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
 389
 390         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 391         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 392                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
 393
 394         rk_clrsetreg(&cru->cru_clksel_con[1],
 395                      PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
 396                      PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
 397                      PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
 398                      PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
 399                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 400                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 401                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
 402                      0 << 0);
 403
 404         /*
 405          * peri clock pll source selection and
 406          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 407          */
 408         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 409         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 410
 411         hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 412         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 413                 PERI_ACLK_HZ && (hclk_div < 0x4));
 414
 415         pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 416         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 417                 PERI_ACLK_HZ && (pclk_div < 0x4));
 418
 419         rk_clrsetreg(&cru->cru_clksel_con[10],
 420                      PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
 421                      PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
 422                      PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
 423                      pclk_div << PERI_PCLK_DIV_SHIFT |
 424                      hclk_div << PERI_HCLK_DIV_SHIFT |
 425                      aclk_div << PERI_ACLK_DIV_SHIFT);
 426
 427         /* PLL enter normal-mode */
 428         rk_clrsetreg(&cru->cru_mode_con,
 429                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 430                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 431                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 432                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 433 }
 434 #endif
 435
 436 /* Get pll rate by id */
 437 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
 438                                    enum rk_clk_id clk_id)
 439 {
 440         uint32_t nr, no, nf;
 441         uint32_t con;
 442         int pll_id = rk_pll_id(clk_id);
 443         struct rk3288_pll *pll = &cru->pll[pll_id];
 444         static u8 clk_shift[CLK_COUNT] = {
 445                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 446                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
 447         };
 448         uint shift;
 449
 450         con = readl(&cru->cru_mode_con);
 451         shift = clk_shift[clk_id];
 452         switch ((con >> shift) & APLL_MODE_MASK) {
 453         case APLL_MODE_SLOW:
 454                 return OSC_HZ;
 455         case APLL_MODE_NORMAL:
 456                 /* normal mode */
 457                 con = readl(&pll->con0);
 458                 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
 459                 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
 460                 con = readl(&pll->con1);
 461                 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
 462
 463                 return (24 * nf / (nr * no)) * 1000000;
 464         case APLL_MODE_DEEP:
 465         default:
 466                 return 32768;
 467         }
 468 }
 469
 470 static ulong rk3288_clk_get_rate(struct udevice *dev)
 471 {
 472         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 473         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 474
 475         debug("%s\n", dev->name);
 476         return rkclk_pll_get_rate(priv->cru, plat->clk_id);
 477 }
 478
 479 static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
 480 {
 481         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 482         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 483
 484         debug("%s\n", dev->name);
 485         switch (plat->clk_id) {
 486         case CLK_DDR:
 487                 rkclk_configure_ddr(priv->cru, priv->grf, rate);
 488                 break;
 489         default:
 490                 return -ENOENT;
 491         }
 492
 493         return 0;
 494 }
 495
 496 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 497                                   int periph)
 498 {
 499         uint src_rate;
 500         uint div, mux;
 501         u32 con;
 502
 503         switch (periph) {
 504         case HCLK_EMMC:
 505                 con = readl(&cru->cru_clksel_con[12]);
 506                 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
 507                 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 508                 break;
 509         case HCLK_SDMMC:
 510                 con = readl(&cru->cru_clksel_con[11]);
 511                 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
 512                 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
 513                 break;
 514         case HCLK_SDIO0:
 515                 con = readl(&cru->cru_clksel_con[12]);
 516                 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
 517                 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
 518                 break;
 519         default:
 520                 return -EINVAL;
 521         }
 522
 523         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 524         return DIV_TO_RATE(src_rate, div);
 525 }
 526
 527 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 528                                   int  periph, uint freq)
 529 {
 530         int src_clk_div;
 531         int mux;
 532
 533         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 534         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 535
 536         if (src_clk_div > 0x3f) {
 537                 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
 538                 mux = EMMC_PLL_SELECT_24MHZ;
 539                 assert((int)EMMC_PLL_SELECT_24MHZ ==
 540                        (int)MMC0_PLL_SELECT_24MHZ);
 541         } else {
 542                 mux = EMMC_PLL_SELECT_GENERAL;
 543                 assert((int)EMMC_PLL_SELECT_GENERAL ==
 544                        (int)MMC0_PLL_SELECT_GENERAL);
 545         }
 546         switch (periph) {
 547         case HCLK_EMMC:
 548                 rk_clrsetreg(&cru->cru_clksel_con[12],
 549                              EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 550                              EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 551                              mux << EMMC_PLL_SHIFT |
 552                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 553                 break;
 554         case HCLK_SDMMC:
 555                 rk_clrsetreg(&cru->cru_clksel_con[11],
 556                              MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 557                              MMC0_DIV_MASK << MMC0_DIV_SHIFT,
 558                              mux << MMC0_PLL_SHIFT |
 559                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 560                 break;
 561         case HCLK_SDIO0:
 562                 rk_clrsetreg(&cru->cru_clksel_con[12],
 563                              SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
 564                              SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
 565                              mux << SDIO0_PLL_SHIFT |
 566                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 567                 break;
 568         default:
 569                 return -EINVAL;
 570         }
 571
 572         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 573 }
 574
 575 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 576                                   int periph)
 577 {
 578         uint div, mux;
 579         u32 con;
 580
 581         switch (periph) {
 582         case SCLK_SPI0:
 583                 con = readl(&cru->cru_clksel_con[25]);
 584                 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
 585                 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
 586                 break;
 587         case SCLK_SPI1:
 588                 con = readl(&cru->cru_clksel_con[25]);
 589                 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
 590                 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
 591                 break;
 592         case SCLK_SPI2:
 593                 con = readl(&cru->cru_clksel_con[39]);
 594                 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
 595                 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
 596                 break;
 597         default:
 598                 return -EINVAL;
 599         }
 600         assert(mux == SPI0_PLL_SELECT_GENERAL);
 601
 602         return DIV_TO_RATE(gclk_rate, div);
 603 }
 604
 605 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 606                                   int periph, uint freq)
 607 {
 608         int src_clk_div;
 609
 610         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
 611         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 612         switch (periph) {
 613         case SCLK_SPI0:
 614                 rk_clrsetreg(&cru->cru_clksel_con[25],
 615                              SPI0_PLL_MASK << SPI0_PLL_SHIFT |
 616                              SPI0_DIV_MASK << SPI0_DIV_SHIFT,
 617                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 618                              src_clk_div << SPI0_DIV_SHIFT);
 619                 break;
 620         case SCLK_SPI1:
 621                 rk_clrsetreg(&cru->cru_clksel_con[25],
 622                              SPI1_PLL_MASK << SPI1_PLL_SHIFT |
 623                              SPI1_DIV_MASK << SPI1_DIV_SHIFT,
 624                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 625                              src_clk_div << SPI1_DIV_SHIFT);
 626                 break;
 627         case SCLK_SPI2:
 628                 rk_clrsetreg(&cru->cru_clksel_con[39],
 629                              SPI2_PLL_MASK << SPI2_PLL_SHIFT |
 630                              SPI2_DIV_MASK << SPI2_DIV_SHIFT,
 631                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 632                              src_clk_div << SPI2_DIV_SHIFT);
 633                 break;
 634         default:
 635                 return -EINVAL;
 636         }
 637
 638         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 639 }
 640
 641 static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
 642 {
 643         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 644         struct udevice *gclk;
 645         ulong new_rate, gclk_rate;
 646         int ret;
 647
 648         ret = rkclk_get_clk(CLK_GENERAL, &gclk);
 649         if (ret)
 650                 return ret;
 651         gclk_rate = clk_get_rate(gclk);
 652         switch (periph) {
 653         case HCLK_EMMC:
 654         case HCLK_SDMMC:
 655         case HCLK_SDIO0:
 656                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
 657                 break;
 658         case SCLK_SPI0:
 659         case SCLK_SPI1:
 660         case SCLK_SPI2:
 661                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph);
 662                 break;
 663         case PCLK_I2C0:
 664         case PCLK_I2C1:
 665         case PCLK_I2C2:
 666         case PCLK_I2C3:
 667         case PCLK_I2C4:
 668         case PCLK_I2C5:
 669                 return gclk_rate;
 670         default:
 671                 return -ENOENT;
 672         }
 673
 674         return new_rate;
 675 }
 676
 677 static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 678 {
 679         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 680         struct rk3288_cru *cru = priv->cru;
 681         struct udevice *gclk;
 682         ulong new_rate, gclk_rate;
 683         int ret;
 684
 685         ret = rkclk_get_clk(CLK_GENERAL, &gclk);
 686         if (ret)
 687                 return ret;
 688         gclk_rate = clk_get_rate(gclk);
 689         switch (periph) {
 690         case HCLK_EMMC:
 691         case HCLK_SDMMC:
 692         case HCLK_SDIO0:
 693                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, periph, rate);
 694                 break;
 695         case SCLK_SPI0:
 696         case SCLK_SPI1:
 697         case SCLK_SPI2:
 698                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
 699                 break;
 700 #ifndef CONFIG_SPL_BUILD
 701         case DCLK_VOP0:
 702         case DCLK_VOP1:
 703                 new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
 704                 break;
 705         case SCLK_EDP_24M:
 706                 /* clk_edp_24M source: 24M */
 707                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
 708
 709                 /* rst edp */
 710                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
 711                 udelay(1);
 712                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
 713                 new_rate = rate;
 714                 break;
 715         case ACLK_VOP0:
 716         case ACLK_VOP1: {
 717                 u32 div;
 718
 719                 /* vop aclk source clk: cpll */
 720                 div = CPLL_HZ / rate;
 721                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 722
 723                 switch (periph) {
 724                 case ACLK_VOP0:
 725                         rk_clrsetreg(&cru->cru_clksel_con[31],
 726                                      3 << 6 | 0x1f << 0,
 727                                      0 << 6 | (div - 1) << 0);
 728                         break;
 729                 case ACLK_VOP1:
 730                         rk_clrsetreg(&cru->cru_clksel_con[31],
 731                                      3 << 14 | 0x1f << 8,
 732                                      0 << 14 | (div - 1) << 8);
 733                         break;
 734                 }
 735                 new_rate = rate;
 736                 break;
 737         }
 738         case PCLK_HDMI_CTRL:
 739                 /* enable pclk hdmi ctrl */
 740                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
 741
 742                 /* software reset hdmi */
 743                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
 744                 udelay(1);
 745                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
 746                 new_rate = rate;
 747                 break;
 748 #endif
 749         default:
 750                 return -ENOENT;
 751         }
 752
 753         return new_rate;
 754 }
 755
 756 static struct clk_ops rk3288_clk_ops = {
 757         .get_rate       = rk3288_clk_get_rate,
 758         .set_rate       = rk3288_clk_set_rate,
 759         .set_periph_rate = rk3288_set_periph_rate,
 760         .get_periph_rate = rk3288_get_periph_rate,
 761 };
 762
 763 static int rk3288_clk_probe(struct udevice *dev)
 764 {
 765         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 766         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 767
 768         if (plat->clk_id != CLK_OSC) {
 769                 struct rk3288_clk_priv *parent_priv = dev_get_priv(dev->parent);
 770
 771                 priv->cru = parent_priv->cru;
 772                 priv->grf = parent_priv->grf;
 773                 return 0;
 774         }
 775         priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
 776         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 777 #ifdef CONFIG_SPL_BUILD
 778         rkclk_init(priv->cru, priv->grf);
 779 #endif
 780
 781         return 0;
 782 }
 783
 784 static const char *const clk_name[CLK_COUNT] = {
 785         "osc",
 786         "apll",
 787         "dpll",
 788         "cpll",
 789         "gpll",
 790         "mpll",
 791 };
 792
 793 static int rk3288_clk_bind(struct udevice *dev)
 794 {
 795         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 796         int pll, ret;
 797
 798         /* We only need to set up the root clock */
 799         if (dev->of_offset == -1) {
 800                 plat->clk_id = CLK_OSC;
 801                 return 0;
 802         }
 803
 804         /* Create devices for P main clocks */
 805         for (pll = 1; pll < CLK_COUNT; pll++) {
 806                 struct udevice *child;
 807                 struct rk3288_clk_plat *cplat;
 808
 809                 debug("%s %s\n", __func__, clk_name[pll]);
 810                 ret = device_bind_driver(dev, "clk_rk3288", clk_name[pll],
 811                                          &child);
 812                 if (ret)
 813                         return ret;
 814                 cplat = dev_get_platdata(child);
 815                 cplat->clk_id = pll;
 816         }
 817
 818         /* The reset driver does not have a device node, so bind it here */
 819         ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev);
 820         if (ret)
 821                 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
 822
 823         return 0;
 824 }
 825
 826 static const struct udevice_id rk3288_clk_ids[] = {
 827         { .compatible = "rockchip,rk3288-cru" },
 828         { }
 829 };
 830
 831 U_BOOT_DRIVER(clk_rk3288) = {
 832         .name           = "clk_rk3288",
 833         .id             = UCLASS_CLK,
 834         .of_match       = rk3288_clk_ids,
 835         .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
 836         .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
 837         .ops            = &rk3288_clk_ops,
 838         .bind           = rk3288_clk_bind,
 839         .probe          = rk3288_clk_probe,
 840 };