2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
13 #include <asm/arch/rcc.h>
14 #include <asm/arch/stm32.h>
15 #include <asm/arch/stm32_periph.h>
16 #include <asm/arch/stm32_pwr.h>
18 #include <dt-bindings/mfd/stm32f7-rcc.h>
20 #define RCC_CR_HSION BIT(0)
21 #define RCC_CR_HSEON BIT(16)
22 #define RCC_CR_HSERDY BIT(17)
23 #define RCC_CR_HSEBYP BIT(18)
24 #define RCC_CR_CSSON BIT(19)
25 #define RCC_CR_PLLON BIT(24)
26 #define RCC_CR_PLLRDY BIT(25)
28 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
29 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
30 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
31 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
32 #define RCC_PLLCFGR_PLLSRC BIT(22)
33 #define RCC_PLLCFGR_PLLM_SHIFT 0
34 #define RCC_PLLCFGR_PLLN_SHIFT 6
35 #define RCC_PLLCFGR_PLLP_SHIFT 16
36 #define RCC_PLLCFGR_PLLQ_SHIFT 24
38 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
39 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
40 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
41 #define RCC_CFGR_SW0 BIT(0)
42 #define RCC_CFGR_SW1 BIT(1)
43 #define RCC_CFGR_SW_MASK GENMASK(1, 0)
44 #define RCC_CFGR_SW_HSI 0
45 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
46 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
47 #define RCC_CFGR_SWS0 BIT(2)
48 #define RCC_CFGR_SWS1 BIT(3)
49 #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
50 #define RCC_CFGR_SWS_HSI 0
51 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
52 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
53 #define RCC_CFGR_HPRE_SHIFT 4
54 #define RCC_CFGR_PPRE1_SHIFT 10
55 #define RCC_CFGR_PPRE2_SHIFT 13
72 #define AHB_PSC_16 0xB
73 #define AHB_PSC_64 0xC
74 #define AHB_PSC_128 0xD
75 #define AHB_PSC_256 0xE
76 #define AHB_PSC_512 0xF
82 #define APB_PSC_16 0x7
85 struct stm32_rcc_regs *base;
86 struct stm32_pwr_regs *pwr_regs;
89 #if !defined(CONFIG_STM32_HSE_HZ)
90 #error "CONFIG_STM32_HSE_HZ not defined!"
92 #if (CONFIG_STM32_HSE_HZ == 25000000)
93 #if (CONFIG_SYS_CLK_FREQ == 200000000)
95 struct pll_psc sys_pll_psc = {
100 .ahb_psc = AHB_PSC_1,
101 .apb1_psc = APB_PSC_4,
102 .apb2_psc = APB_PSC_2
106 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
110 static int configure_clocks(struct udevice *dev)
112 struct stm32_clk *priv = dev_get_priv(dev);
113 struct stm32_rcc_regs *regs = priv->base;
114 struct stm32_pwr_regs *pwr = priv->pwr_regs;
116 /* Reset RCC configuration */
117 setbits_le32(®s->cr, RCC_CR_HSION);
118 writel(0, ®s->cfgr); /* Reset CFGR */
119 clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
121 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
122 clrbits_le32(®s->cr, RCC_CR_HSEBYP);
123 writel(0, ®s->cir); /* Disable all interrupts */
125 /* Configure for HSE+PLL operation */
126 setbits_le32(®s->cr, RCC_CR_HSEON);
127 while (!(readl(®s->cr) & RCC_CR_HSERDY))
130 setbits_le32(®s->cfgr, ((
131 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
132 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
133 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
135 /* Configure the main PLL */
136 setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
137 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
138 sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT);
139 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
140 sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT);
141 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
142 ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
143 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
144 sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
146 /* Enable the main PLL */
147 setbits_le32(®s->cr, RCC_CR_PLLON);
148 while (!(readl(®s->cr) & RCC_CR_PLLRDY))
151 /* Enable high performance mode, System frequency up to 200 MHz */
152 setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
153 setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
155 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
157 /* Enable the Over-drive switch */
158 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
160 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
163 stm32_flash_latency_cfg(5);
164 clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
165 setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
167 while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
174 static unsigned long stm32_clk_get_rate(struct clk *clk)
176 struct stm32_clk *priv = dev_get_priv(clk->dev);
177 struct stm32_rcc_regs *regs = priv->base;
180 /* Prescaler table lookups for clock computation */
181 u8 ahb_psc_table[16] = {
182 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
184 u8 apb_psc_table[8] = {
185 0, 0, 0, 0, 1, 2, 3, 4
188 if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
190 u16 pllm, plln, pllp;
191 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
192 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
193 >> RCC_PLLCFGR_PLLN_SHIFT);
194 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
195 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
196 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
203 * AHB CLOCK: 3 x 32 bits consecutive registers are used :
204 * AHB1, AHB2 and AHB3
206 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
207 shift = ahb_psc_table[(
208 (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
209 >> RCC_CFGR_HPRE_SHIFT)];
210 return sysclk >>= shift;
213 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
214 shift = apb_psc_table[(
215 (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
216 >> RCC_CFGR_PPRE1_SHIFT)];
217 return sysclk >>= shift;
220 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
221 shift = apb_psc_table[(
222 (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
223 >> RCC_CFGR_PPRE2_SHIFT)];
224 return sysclk >>= shift;
227 pr_err("clock index %ld out of range\n", clk->id);
233 static int stm32_clk_enable(struct clk *clk)
235 struct stm32_clk *priv = dev_get_priv(clk->dev);
236 struct stm32_rcc_regs *regs = priv->base;
237 u32 offset = clk->id / 32;
238 u32 bit_index = clk->id % 32;
240 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
241 __func__, clk->id, offset, bit_index);
242 setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
247 void clock_setup(int peripheral)
249 switch (peripheral) {
250 case SYSCFG_CLOCK_CFG:
251 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
253 case TIMER2_CLOCK_CFG:
254 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
256 case STMMAC_CLOCK_CFG:
257 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
258 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
259 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
266 static int stm32_clk_probe(struct udevice *dev)
268 struct ofnode_phandle_args args;
271 debug("%s: stm32_clk_probe\n", __func__);
273 struct stm32_clk *priv = dev_get_priv(dev);
276 addr = devfdt_get_addr(dev);
277 if (addr == FDT_ADDR_T_NONE)
280 priv->base = (struct stm32_rcc_regs *)addr;
282 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
285 debug("%s: can't find syscon device (%d)\n", __func__,
290 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
292 configure_clocks(dev);
297 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
299 debug("%s(clk=%p)\n", __func__, clk);
301 if (args->args_count != 2) {
302 debug("Invaild args_count: %d\n", args->args_count);
306 if (args->args_count)
307 clk->id = args->args[1];
314 static struct clk_ops stm32_clk_ops = {
315 .of_xlate = stm32_clk_of_xlate,
316 .enable = stm32_clk_enable,
317 .get_rate = stm32_clk_get_rate,
320 static const struct udevice_id stm32_clk_ids[] = {
321 { .compatible = "st,stm32f42xx-rcc"},
322 { .compatible = "st,stm32f746-rcc"},
326 U_BOOT_DRIVER(stm32f7_clk) = {
327 .name = "stm32f7_clk",
329 .of_match = stm32_clk_ids,
330 .ops = &stm32_clk_ops,
331 .probe = stm32_clk_probe,
332 .priv_auto_alloc_size = sizeof(struct stm32_clk),
333 .flags = DM_FLAG_PRE_RELOC,