2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
8 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
17 #define MAX_HSI_HZ 64000000
20 #define RCC_OCENSETR 0x0C
21 #define RCC_OCENCLRR 0x10
22 #define RCC_HSICFGR 0x18
23 #define RCC_MPCKSELR 0x20
24 #define RCC_ASSCKSELR 0x24
25 #define RCC_RCK12SELR 0x28
26 #define RCC_MPCKDIVR 0x2C
27 #define RCC_AXIDIVR 0x30
28 #define RCC_APB4DIVR 0x3C
29 #define RCC_APB5DIVR 0x40
30 #define RCC_RTCDIVR 0x44
31 #define RCC_MSSCKSELR 0x48
32 #define RCC_PLL1CR 0x80
33 #define RCC_PLL1CFGR1 0x84
34 #define RCC_PLL1CFGR2 0x88
35 #define RCC_PLL1FRACR 0x8C
36 #define RCC_PLL1CSGR 0x90
37 #define RCC_PLL2CR 0x94
38 #define RCC_PLL2CFGR1 0x98
39 #define RCC_PLL2CFGR2 0x9C
40 #define RCC_PLL2FRACR 0xA0
41 #define RCC_PLL2CSGR 0xA4
42 #define RCC_I2C46CKSELR 0xC0
43 #define RCC_CPERCKSELR 0xD0
44 #define RCC_STGENCKSELR 0xD4
45 #define RCC_DDRITFCR 0xD8
46 #define RCC_BDCR 0x140
47 #define RCC_RDLSICR 0x144
48 #define RCC_MP_APB4ENSETR 0x200
49 #define RCC_MP_APB5ENSETR 0x208
50 #define RCC_MP_AHB5ENSETR 0x210
51 #define RCC_MP_AHB6ENSETR 0x218
52 #define RCC_OCRDYR 0x808
53 #define RCC_DBGCFGR 0x80C
54 #define RCC_RCK3SELR 0x820
55 #define RCC_RCK4SELR 0x824
56 #define RCC_MCUDIVR 0x830
57 #define RCC_APB1DIVR 0x834
58 #define RCC_APB2DIVR 0x838
59 #define RCC_APB3DIVR 0x83C
60 #define RCC_PLL3CR 0x880
61 #define RCC_PLL3CFGR1 0x884
62 #define RCC_PLL3CFGR2 0x888
63 #define RCC_PLL3FRACR 0x88C
64 #define RCC_PLL3CSGR 0x890
65 #define RCC_PLL4CR 0x894
66 #define RCC_PLL4CFGR1 0x898
67 #define RCC_PLL4CFGR2 0x89C
68 #define RCC_PLL4FRACR 0x8A0
69 #define RCC_PLL4CSGR 0x8A4
70 #define RCC_I2C12CKSELR 0x8C0
71 #define RCC_I2C35CKSELR 0x8C4
72 #define RCC_UART6CKSELR 0x8E4
73 #define RCC_UART24CKSELR 0x8E8
74 #define RCC_UART35CKSELR 0x8EC
75 #define RCC_UART78CKSELR 0x8F0
76 #define RCC_SDMMC12CKSELR 0x8F4
77 #define RCC_SDMMC3CKSELR 0x8F8
78 #define RCC_ETHCKSELR 0x8FC
79 #define RCC_QSPICKSELR 0x900
80 #define RCC_FMCCKSELR 0x904
81 #define RCC_USBCKSELR 0x91C
82 #define RCC_MP_APB1ENSETR 0xA00
83 #define RCC_MP_APB2ENSETR 0XA08
84 #define RCC_MP_AHB2ENSETR 0xA18
85 #define RCC_MP_AHB4ENSETR 0xA28
87 /* used for most of SELR register */
88 #define RCC_SELR_SRC_MASK GENMASK(2, 0)
89 #define RCC_SELR_SRCRDY BIT(31)
91 /* Values of RCC_MPCKSELR register */
92 #define RCC_MPCKSELR_HSI 0
93 #define RCC_MPCKSELR_HSE 1
94 #define RCC_MPCKSELR_PLL 2
95 #define RCC_MPCKSELR_PLL_MPUDIV 3
97 /* Values of RCC_ASSCKSELR register */
98 #define RCC_ASSCKSELR_HSI 0
99 #define RCC_ASSCKSELR_HSE 1
100 #define RCC_ASSCKSELR_PLL 2
102 /* Values of RCC_MSSCKSELR register */
103 #define RCC_MSSCKSELR_HSI 0
104 #define RCC_MSSCKSELR_HSE 1
105 #define RCC_MSSCKSELR_CSI 2
106 #define RCC_MSSCKSELR_PLL 3
108 /* Values of RCC_CPERCKSELR register */
109 #define RCC_CPERCKSELR_HSI 0
110 #define RCC_CPERCKSELR_CSI 1
111 #define RCC_CPERCKSELR_HSE 2
113 /* used for most of DIVR register : max div for RTC */
114 #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
115 #define RCC_DIVR_DIVRDY BIT(31)
117 /* Masks for specific DIVR registers */
118 #define RCC_APBXDIV_MASK GENMASK(2, 0)
119 #define RCC_MPUDIV_MASK GENMASK(2, 0)
120 #define RCC_AXIDIV_MASK GENMASK(2, 0)
121 #define RCC_MCUDIV_MASK GENMASK(3, 0)
123 /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
124 #define RCC_MP_ENCLRR_OFFSET 4
126 /* Fields of RCC_BDCR register */
127 #define RCC_BDCR_LSEON BIT(0)
128 #define RCC_BDCR_LSEBYP BIT(1)
129 #define RCC_BDCR_LSERDY BIT(2)
130 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
131 #define RCC_BDCR_LSEDRV_SHIFT 4
132 #define RCC_BDCR_LSECSSON BIT(8)
133 #define RCC_BDCR_RTCCKEN BIT(20)
134 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
135 #define RCC_BDCR_RTCSRC_SHIFT 16
137 /* Fields of RCC_RDLSICR register */
138 #define RCC_RDLSICR_LSION BIT(0)
139 #define RCC_RDLSICR_LSIRDY BIT(1)
141 /* used for ALL PLLNCR registers */
142 #define RCC_PLLNCR_PLLON BIT(0)
143 #define RCC_PLLNCR_PLLRDY BIT(1)
144 #define RCC_PLLNCR_DIVPEN BIT(4)
145 #define RCC_PLLNCR_DIVQEN BIT(5)
146 #define RCC_PLLNCR_DIVREN BIT(6)
147 #define RCC_PLLNCR_DIVEN_SHIFT 4
149 /* used for ALL PLLNCFGR1 registers */
150 #define RCC_PLLNCFGR1_DIVM_SHIFT 16
151 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
152 #define RCC_PLLNCFGR1_DIVN_SHIFT 0
153 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
154 /* only for PLL3 and PLL4 */
155 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
156 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
158 /* used for ALL PLLNCFGR2 registers */
159 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
160 #define RCC_PLLNCFGR2_DIVP_SHIFT 0
161 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
162 #define RCC_PLLNCFGR2_DIVQ_SHIFT 8
163 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
164 #define RCC_PLLNCFGR2_DIVR_SHIFT 16
165 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
167 /* used for ALL PLLNFRACR registers */
168 #define RCC_PLLNFRACR_FRACV_SHIFT 3
169 #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
170 #define RCC_PLLNFRACR_FRACLE BIT(16)
172 /* used for ALL PLLNCSGR registers */
173 #define RCC_PLLNCSGR_INC_STEP_SHIFT 16
174 #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
175 #define RCC_PLLNCSGR_MOD_PER_SHIFT 0
176 #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
177 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
178 #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
180 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
181 #define RCC_OCENR_HSION BIT(0)
182 #define RCC_OCENR_CSION BIT(4)
183 #define RCC_OCENR_HSEON BIT(8)
184 #define RCC_OCENR_HSEBYP BIT(10)
185 #define RCC_OCENR_HSECSSON BIT(11)
187 /* Fields of RCC_OCRDYR register */
188 #define RCC_OCRDYR_HSIRDY BIT(0)
189 #define RCC_OCRDYR_HSIDIVRDY BIT(2)
190 #define RCC_OCRDYR_CSIRDY BIT(4)
191 #define RCC_OCRDYR_HSERDY BIT(8)
193 /* Fields of DDRITFCR register */
194 #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
195 #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
196 #define RCC_DDRITFCR_DDRCKMOD_SSR 0
198 /* Fields of RCC_HSICFGR register */
199 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
201 /* used for MCO related operations */
202 #define RCC_MCOCFG_MCOON BIT(12)
203 #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
204 #define RCC_MCOCFG_MCODIV_SHIFT 4
205 #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
207 enum stm32mp1_parent_id {
209 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
210 * they are used as index in osc[] as entry point
221 /* other parent source */
253 enum stm32mp1_parent_sel {
273 enum stm32mp1_pll_id {
281 enum stm32mp1_div_id {
288 enum stm32mp1_clksrc_id {
301 enum stm32mp1_clkdiv_id {
316 enum stm32mp1_pllcfg {
326 enum stm32mp1_pllcsg {
333 enum stm32mp1_plltype {
339 struct stm32mp1_pll {
345 struct stm32mp1_clk_gate {
354 struct stm32mp1_clk_sel {
362 #define REFCLK_SIZE 4
363 struct stm32mp1_clk_pll {
364 enum stm32mp1_plltype plltype;
371 u8 refclk[REFCLK_SIZE];
374 struct stm32mp1_clk_data {
375 const struct stm32mp1_clk_gate *gate;
376 const struct stm32mp1_clk_sel *sel;
377 const struct stm32mp1_clk_pll *pll;
381 struct stm32mp1_clk_priv {
383 const struct stm32mp1_clk_data *data;
385 struct udevice *osc_dev[NB_OSC];
388 #define STM32MP1_CLK(off, b, idx, s) \
395 .fixed = _UNKNOWN_ID, \
398 #define STM32MP1_CLK_F(off, b, idx, f) \
404 .sel = _UNKNOWN_SEL, \
408 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
415 .fixed = _UNKNOWN_ID, \
418 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
424 .sel = _UNKNOWN_SEL, \
428 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
434 .nb_parent = ARRAY_SIZE((p)) \
437 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
441 .rckxselr = (off1), \
442 .pllxcfgr1 = (off2), \
443 .pllxcfgr2 = (off3), \
444 .pllxfracr = (off4), \
446 .pllxcsgr = (off6), \
453 static const u8 stm32mp1_clks[][2] = {
463 {CK_HSE_DIV2, _HSE_KER_DIV2},
466 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
467 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
468 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
469 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
470 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
471 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
472 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
473 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
474 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
475 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
476 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
477 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
479 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
480 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
481 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
482 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
483 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
484 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
485 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
486 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
487 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
488 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
490 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
492 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
493 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
494 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
496 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
497 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
499 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
500 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
502 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
503 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
504 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
505 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
506 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
507 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
508 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
509 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
510 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
511 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
512 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
514 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
516 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
517 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
518 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
519 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
520 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
521 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
522 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
523 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
524 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
525 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
527 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
530 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
531 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
532 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
533 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
535 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
537 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
539 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
541 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
542 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
543 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
544 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
545 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
546 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
547 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
548 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
550 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
551 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
552 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
553 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
554 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
555 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
557 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
559 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
561 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
563 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
565 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
566 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
567 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
568 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
569 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
570 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
573 #ifdef STM32MP1_CLOCK_TREE_INIT
574 /* define characteristic of PLL according type */
576 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
588 #endif /* STM32MP1_CLOCK_TREE_INIT */
590 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
591 STM32MP1_CLK_PLL(_PLL1, PLL_1600,
592 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
593 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
594 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
595 STM32MP1_CLK_PLL(_PLL2, PLL_1600,
596 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
597 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
598 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
599 STM32MP1_CLK_PLL(_PLL3, PLL_800,
600 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
601 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
602 _HSI, _HSE, _CSI, _UNKNOWN_ID),
603 STM32MP1_CLK_PLL(_PLL4, PLL_800,
604 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
605 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
606 _HSI, _HSE, _CSI, _I2S_CKIN),
609 /* Prescaler table lookups for clock computation */
610 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
611 static const u8 stm32mp1_mcu_div[16] = {
612 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
615 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
616 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
617 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
618 static const u8 stm32mp1_mpu_apbx_div[8] = {
619 0, 1, 2, 3, 4, 4, 4, 4
622 /* div = /1 /2 /3 /4 */
623 static const u8 stm32mp1_axi_div[8] = {
624 1, 2, 3, 4, 4, 4, 4, 4
628 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
634 [_I2S_CKIN] = "I2S_CKIN",
635 [_HSI_KER] = "HSI_KER",
636 [_HSE_KER] = "HSE_KER",
637 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
638 [_CSI_KER] = "CSI_KER",
639 [_PLL1_P] = "PLL1_P",
640 [_PLL1_Q] = "PLL1_Q",
641 [_PLL1_R] = "PLL1_R",
642 [_PLL2_P] = "PLL2_P",
643 [_PLL2_Q] = "PLL2_Q",
644 [_PLL2_R] = "PLL2_R",
645 [_PLL3_P] = "PLL3_P",
646 [_PLL3_Q] = "PLL3_Q",
647 [_PLL3_R] = "PLL3_R",
648 [_PLL4_P] = "PLL4_P",
649 [_PLL4_Q] = "PLL4_Q",
650 [_PLL4_R] = "PLL4_R",
659 [_CK_PER] = "CK_PER",
660 [_CK_MPU] = "CK_MPU",
661 [_CK_MCU] = "CK_MCU",
662 [_USB_PHY_48] = "USB_PHY_48"
665 static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
666 [_I2C12_SEL] = "I2C12",
667 [_I2C35_SEL] = "I2C35",
668 [_I2C46_SEL] = "I2C46",
669 [_UART6_SEL] = "UART6",
670 [_UART24_SEL] = "UART24",
671 [_UART35_SEL] = "UART35",
672 [_UART78_SEL] = "UART78",
673 [_SDMMC12_SEL] = "SDMMC12",
674 [_SDMMC3_SEL] = "SDMMC3",
676 [_QSPI_SEL] = "QSPI",
678 [_USBPHY_SEL] = "USBPHY",
679 [_USBO_SEL] = "USBO",
680 [_STGEN_SEL] = "STGEN"
684 static const struct stm32mp1_clk_data stm32mp1_data = {
685 .gate = stm32mp1_clk_gate,
686 .sel = stm32mp1_clk_sel,
687 .pll = stm32mp1_clk_pll,
688 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
691 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
694 debug("%s: clk id %d not found\n", __func__, idx);
698 debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
699 (u32)priv->osc[idx], priv->osc[idx] / 1000);
701 return priv->osc[idx];
704 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
706 const struct stm32mp1_clk_gate *gate = priv->data->gate;
707 int i, nb_clks = priv->data->nb_gate;
709 for (i = 0; i < nb_clks; i++) {
710 if (gate[i].index == id)
715 printf("%s: clk id %d not found\n", __func__, (u32)id);
722 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
725 const struct stm32mp1_clk_gate *gate = priv->data->gate;
727 if (gate[i].sel > _PARENT_SEL_NB) {
728 printf("%s: parents for clk id %d not found\n",
736 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
739 const struct stm32mp1_clk_gate *gate = priv->data->gate;
741 if (gate[i].fixed == _UNKNOWN_ID)
744 return gate[i].fixed;
747 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
750 const struct stm32mp1_clk_sel *sel = priv->data->sel;
754 for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
755 if (stm32mp1_clks[i][0] == id)
756 return stm32mp1_clks[i][1];
758 i = stm32mp1_clk_get_id(priv, id);
762 p = stm32mp1_clk_get_fixed_parent(priv, i);
763 if (p >= 0 && p < _PARENT_NB)
766 s = stm32mp1_clk_get_sel(priv, i);
770 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
772 if (p < sel[s].nb_parent) {
774 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
775 stm32mp1_clk_parent_name[sel[s].parent[p]],
776 stm32mp1_clk_parent_sel_name[s],
779 return sel[s].parent[p];
782 pr_err("%s: no parents defined for clk id %d\n",
788 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
789 int pll_id, int div_id)
791 const struct stm32mp1_clk_pll *pll = priv->data->pll;
792 int divm, divn, divy, src;
794 u32 selr, cfgr1, cfgr2, fracr;
795 const u8 shift[_DIV_NB] = {
796 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
797 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
798 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
800 debug("%s(%d, %d)\n", __func__, pll_id, div_id);
801 if (div_id > _DIV_NB)
804 selr = readl(priv->base + pll[pll_id].rckxselr);
805 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
806 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
807 fracr = readl(priv->base + pll[pll_id].pllxfracr);
809 debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n",
810 pll_id, selr, cfgr1, cfgr2, fracr);
812 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
813 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
814 divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
816 debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
818 src = selr & RCC_SELR_SRC_MASK;
819 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
821 debug(" refclk = %d kHz\n", (u32)(refclk / 1000));
824 * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
825 * So same final result than PLL2 et 4
827 * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
828 * / (DIVM + 1) * (DIVy + 1)
830 * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
832 if (fracr & RCC_PLLNFRACR_FRACLE) {
833 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
834 >> RCC_PLLNFRACR_FRACV_SHIFT;
835 dfout = (ulong)lldiv((unsigned long long)refclk *
836 (((divn + 1) << 13) + fracv),
837 ((unsigned long long)(divm + 1) *
840 dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
842 debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
847 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
855 reg = readl(priv->base + RCC_MPCKSELR);
856 switch (reg & RCC_SELR_SRC_MASK) {
857 case RCC_MPCKSELR_HSI:
858 clock = stm32mp1_clk_get_fixed(priv, _HSI);
860 case RCC_MPCKSELR_HSE:
861 clock = stm32mp1_clk_get_fixed(priv, _HSE);
863 case RCC_MPCKSELR_PLL:
864 case RCC_MPCKSELR_PLL_MPUDIV:
865 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
866 if (p == RCC_MPCKSELR_PLL_MPUDIV) {
867 reg = readl(priv->base + RCC_MPCKDIVR);
868 clock /= stm32mp1_mpu_div[reg &
880 reg = readl(priv->base + RCC_ASSCKSELR);
881 switch (reg & RCC_SELR_SRC_MASK) {
882 case RCC_ASSCKSELR_HSI:
883 clock = stm32mp1_clk_get_fixed(priv, _HSI);
885 case RCC_ASSCKSELR_HSE:
886 clock = stm32mp1_clk_get_fixed(priv, _HSE);
888 case RCC_ASSCKSELR_PLL:
889 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
893 /* System clock divider */
894 reg = readl(priv->base + RCC_AXIDIVR);
895 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
899 reg = readl(priv->base + RCC_APB4DIVR);
900 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
903 reg = readl(priv->base + RCC_APB5DIVR);
904 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
915 reg = readl(priv->base + RCC_MSSCKSELR);
916 switch (reg & RCC_SELR_SRC_MASK) {
917 case RCC_MSSCKSELR_HSI:
918 clock = stm32mp1_clk_get_fixed(priv, _HSI);
920 case RCC_MSSCKSELR_HSE:
921 clock = stm32mp1_clk_get_fixed(priv, _HSE);
923 case RCC_MSSCKSELR_CSI:
924 clock = stm32mp1_clk_get_fixed(priv, _CSI);
926 case RCC_MSSCKSELR_PLL:
927 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
931 /* MCU clock divider */
932 reg = readl(priv->base + RCC_MCUDIVR);
933 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
937 reg = readl(priv->base + RCC_APB1DIVR);
938 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
941 reg = readl(priv->base + RCC_APB2DIVR);
942 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
945 reg = readl(priv->base + RCC_APB3DIVR);
946 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
954 reg = readl(priv->base + RCC_CPERCKSELR);
955 switch (reg & RCC_SELR_SRC_MASK) {
956 case RCC_CPERCKSELR_HSI:
957 clock = stm32mp1_clk_get_fixed(priv, _HSI);
959 case RCC_CPERCKSELR_HSE:
960 clock = stm32mp1_clk_get_fixed(priv, _HSE);
962 case RCC_CPERCKSELR_CSI:
963 clock = stm32mp1_clk_get_fixed(priv, _CSI);
969 clock = stm32mp1_clk_get_fixed(priv, _HSI);
973 clock = stm32mp1_clk_get_fixed(priv, _CSI);
978 clock = stm32mp1_clk_get_fixed(priv, _HSE);
979 if (p == _HSE_KER_DIV2)
983 clock = stm32mp1_clk_get_fixed(priv, _LSI);
986 clock = stm32mp1_clk_get_fixed(priv, _LSE);
992 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
997 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1002 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1007 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1011 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
1018 debug("%s(%d) clock = %lx : %ld kHz\n",
1019 __func__, p, clock, clock / 1000);
1024 static int stm32mp1_clk_enable(struct clk *clk)
1026 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1027 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1028 int i = stm32mp1_clk_get_id(priv, clk->id);
1033 if (gate[i].set_clr)
1034 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1036 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1038 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1043 static int stm32mp1_clk_disable(struct clk *clk)
1045 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1046 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1047 int i = stm32mp1_clk_get_id(priv, clk->id);
1052 if (gate[i].set_clr)
1053 writel(BIT(gate[i].bit),
1054 priv->base + gate[i].offset
1055 + RCC_MP_ENCLRR_OFFSET);
1057 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1059 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1064 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1066 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1067 int p = stm32mp1_clk_get_parent(priv, clk->id);
1073 rate = stm32mp1_clk_get(priv, p);
1076 debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1077 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1082 static void stm32mp1_osc_clk_init(const char *name,
1083 struct stm32mp1_clk_priv *priv,
1087 struct udevice *dev = NULL;
1089 priv->osc[index] = 0;
1091 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1092 if (clk_request(dev, &clk))
1093 pr_err("%s request", name);
1095 priv->osc[index] = clk_get_rate(&clk);
1097 priv->osc_dev[index] = dev;
1100 static void stm32mp1_osc_init(struct udevice *dev)
1102 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1104 const char *name[NB_OSC] = {
1110 [_I2S_CKIN] = "i2s_ckin",
1111 [_USB_PHY_48] = "ck_usbo_48m"};
1113 for (i = 0; i < NB_OSC; i++) {
1114 stm32mp1_osc_clk_init(name[i], priv, i);
1115 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1119 static int stm32mp1_clk_probe(struct udevice *dev)
1122 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1124 priv->base = dev_read_addr(dev->parent);
1125 if (priv->base == FDT_ADDR_T_NONE)
1128 priv->data = (void *)&stm32mp1_data;
1130 if (!priv->data->gate || !priv->data->sel ||
1134 stm32mp1_osc_init(dev);
1139 static const struct clk_ops stm32mp1_clk_ops = {
1140 .enable = stm32mp1_clk_enable,
1141 .disable = stm32mp1_clk_disable,
1142 .get_rate = stm32mp1_clk_get_rate,
1145 static const struct udevice_id stm32mp1_clk_ids[] = {
1146 { .compatible = "st,stm32mp1-rcc-clk" },
1150 U_BOOT_DRIVER(stm32mp1_clock) = {
1151 .name = "stm32mp1_clk",
1153 .of_match = stm32mp1_clk_ids,
1154 .ops = &stm32mp1_clk_ops,
1155 .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
1156 .probe = stm32mp1_clk_probe,