1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2016 Xilinx, Inc.
9 #include <linux/bitops.h>
10 #include <clk-uclass.h>
12 #include <asm/arch/sys_proto.h>
15 static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
16 static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
18 /* Full power domain clocks */
19 #define CRF_APB_APLL_CTRL (zynqmp_crf_apb_clkc_base + 0x00)
20 #define CRF_APB_DPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x0c)
21 #define CRF_APB_VPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x18)
22 #define CRF_APB_PLL_STATUS (zynqmp_crf_apb_clkc_base + 0x24)
23 #define CRF_APB_APLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x28)
24 #define CRF_APB_DPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x2c)
25 #define CRF_APB_VPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x30)
26 /* Peripheral clocks */
27 #define CRF_APB_ACPU_CTRL (zynqmp_crf_apb_clkc_base + 0x40)
28 #define CRF_APB_DBG_TRACE_CTRL (zynqmp_crf_apb_clkc_base + 0x44)
29 #define CRF_APB_DBG_FPD_CTRL (zynqmp_crf_apb_clkc_base + 0x48)
30 #define CRF_APB_DP_VIDEO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x50)
31 #define CRF_APB_DP_AUDIO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x54)
32 #define CRF_APB_DP_STC_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x5c)
33 #define CRF_APB_DDR_CTRL (zynqmp_crf_apb_clkc_base + 0x60)
34 #define CRF_APB_GPU_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x64)
35 #define CRF_APB_SATA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x80)
36 #define CRF_APB_PCIE_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x94)
37 #define CRF_APB_GDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x98)
38 #define CRF_APB_DPDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x9c)
39 #define CRF_APB_TOPSW_MAIN_CTRL (zynqmp_crf_apb_clkc_base + 0xa0)
40 #define CRF_APB_TOPSW_LSBUS_CTRL (zynqmp_crf_apb_clkc_base + 0xa4)
41 #define CRF_APB_GTGREF0_REF_CTRL (zynqmp_crf_apb_clkc_base + 0xa8)
42 #define CRF_APB_DBG_TSTMP_CTRL (zynqmp_crf_apb_clkc_base + 0xd8)
44 /* Low power domain clocks */
45 #define CRL_APB_IOPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x00)
46 #define CRL_APB_RPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x10)
47 #define CRL_APB_PLL_STATUS (zynqmp_crl_apb_clkc_base + 0x20)
48 #define CRL_APB_IOPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x24)
49 #define CRL_APB_RPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x28)
50 /* Peripheral clocks */
51 #define CRL_APB_USB3_DUAL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x2c)
52 #define CRL_APB_GEM0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x30)
53 #define CRL_APB_GEM1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x34)
54 #define CRL_APB_GEM2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x38)
55 #define CRL_APB_GEM3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x3c)
56 #define CRL_APB_USB0_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x40)
57 #define CRL_APB_USB1_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x44)
58 #define CRL_APB_QSPI_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x48)
59 #define CRL_APB_SDIO0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x4c)
60 #define CRL_APB_SDIO1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x50)
61 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54)
62 #define CRL_APB_UART1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x58)
63 #define CRL_APB_SPI0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x5c)
64 #define CRL_APB_SPI1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x60)
65 #define CRL_APB_CAN0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x64)
66 #define CRL_APB_CAN1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x68)
67 #define CRL_APB_CPU_R5_CTRL (zynqmp_crl_apb_clkc_base + 0x70)
68 #define CRL_APB_IOU_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x7c)
69 #define CRL_APB_CSU_PLL_CTRL (zynqmp_crl_apb_clkc_base + 0x80)
70 #define CRL_APB_PCAP_CTRL (zynqmp_crl_apb_clkc_base + 0x84)
71 #define CRL_APB_LPD_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x88)
72 #define CRL_APB_LPD_LSBUS_CTRL (zynqmp_crl_apb_clkc_base + 0x8c)
73 #define CRL_APB_DBG_LPD_CTRL (zynqmp_crl_apb_clkc_base + 0x90)
74 #define CRL_APB_NAND_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x94)
75 #define CRL_APB_ADMA_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x98)
76 #define CRL_APB_PL0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa0)
77 #define CRL_APB_PL1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa4)
78 #define CRL_APB_PL2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa8)
79 #define CRL_APB_PL3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xac)
80 #define CRL_APB_PL0_THR_CNT (zynqmp_crl_apb_clkc_base + 0xb4)
81 #define CRL_APB_PL1_THR_CNT (zynqmp_crl_apb_clkc_base + 0xbc)
82 #define CRL_APB_PL2_THR_CNT (zynqmp_crl_apb_clkc_base + 0xc4)
83 #define CRL_APB_PL3_THR_CNT (zynqmp_crl_apb_clkc_base + 0xdc)
84 #define CRL_APB_GEM_TSU_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe0)
85 #define CRL_APB_DLL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe4)
86 #define CRL_APB_AMS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe8)
87 #define CRL_APB_I2C0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x100)
88 #define CRL_APB_I2C1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x104)
89 #define CRL_APB_TIMESTAMP_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x108)
91 #define ZYNQ_CLK_MAXDIV 0x3f
92 #define CLK_CTRL_DIV1_SHIFT 16
93 #define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
94 #define CLK_CTRL_DIV0_SHIFT 8
95 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
96 #define CLK_CTRL_SRCSEL_SHIFT 0
97 #define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
98 #define PLLCTRL_FBDIV_MASK 0x7f00
99 #define PLLCTRL_FBDIV_SHIFT 8
100 #define PLLCTRL_RESET_MASK 1
101 #define PLLCTRL_RESET_SHIFT 0
102 #define PLLCTRL_BYPASS_MASK 0x8
103 #define PLLCTRL_BYPASS_SHFT 3
104 #define PLLCTRL_POST_SRC_SHFT 24
105 #define PLLCTRL_POST_SRC_MASK (0x7 << PLLCTRL_POST_SRC_SHFT)
108 #define NUM_MIO_PINS 77
113 iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd,
115 dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp,
116 dp_video_ref, dp_audio_ref,
117 dp_stc_ref, gdma_ref, dpdma_ref,
118 ddr_ref, sata_ref, pcie_ref,
119 gpu_ref, gpu_pp0_ref, gpu_pp1_ref,
120 topsw_main, topsw_lsbus,
122 lpd_switch, lpd_lsbus,
123 usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1,
125 csu_spb, csu_pll, pcap,
127 gem_tsu_ref, gem_tsu,
128 gem0_ref, gem1_ref, gem2_ref, gem3_ref,
129 gem0_rx, gem1_rx, gem2_rx, gem3_rx,
131 sdio0_ref, sdio1_ref,
132 uart0_ref, uart1_ref,
135 i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1,
145 static const char * const clk_names[clk_max] = {
146 "iopll", "rpll", "apll", "dpll",
147 "vpll", "iopll_to_fpd", "rpll_to_fpd",
148 "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
149 "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
150 "dbg_trace", "dbg_tstmp", "dp_video_ref",
151 "dp_audio_ref", "dp_stc_ref", "gdma_ref",
152 "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
153 "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
154 "topsw_main", "topsw_lsbus", "gtgref0_ref",
155 "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
156 "usb1_bus_ref", "usb3_dual_ref", "usb0",
157 "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
158 "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
159 "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
160 "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
161 "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
162 "uart0_ref", "uart1_ref", "spi0_ref",
163 "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
164 "can0_ref", "can1_ref", "can0", "can1",
165 "dll_ref", "adma_ref", "timestamp_ref",
166 "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
169 struct zynqmp_clk_priv {
170 unsigned long ps_clk_freq;
171 unsigned long video_clk;
172 unsigned long pss_alt_ref_clk;
173 unsigned long gt_crx_ref_clk;
174 unsigned long aux_ref_clk;
177 static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
181 return CRL_APB_IOPLL_CTRL;
183 return CRL_APB_RPLL_CTRL;
185 return CRF_APB_APLL_CTRL;
187 return CRF_APB_DPLL_CTRL;
189 return CRF_APB_VPLL_CTRL;
191 return CRF_APB_ACPU_CTRL;
193 return CRF_APB_DDR_CTRL;
195 return CRL_APB_QSPI_REF_CTRL;
197 return CRL_APB_GEM0_REF_CTRL;
199 return CRL_APB_GEM1_REF_CTRL;
201 return CRL_APB_GEM2_REF_CTRL;
203 return CRL_APB_GEM3_REF_CTRL;
205 return CRL_APB_UART0_REF_CTRL;
207 return CRL_APB_UART1_REF_CTRL;
209 return CRL_APB_SDIO0_REF_CTRL;
211 return CRL_APB_SDIO1_REF_CTRL;
213 return CRL_APB_SPI0_REF_CTRL;
215 return CRL_APB_SPI1_REF_CTRL;
217 return CRL_APB_NAND_REF_CTRL;
219 return CRL_APB_I2C0_REF_CTRL;
221 return CRL_APB_I2C1_REF_CTRL;
223 return CRL_APB_CAN0_REF_CTRL;
225 return CRL_APB_CAN1_REF_CTRL;
227 return CRL_APB_PL0_REF_CTRL;
229 return CRL_APB_PL1_REF_CTRL;
231 return CRL_APB_PL2_REF_CTRL;
233 return CRL_APB_PL3_REF_CTRL;
235 return CRF_APB_TOPSW_LSBUS_CTRL;
237 return CRL_APB_IOPLL_TO_FPD_CTRL;
239 debug("Invalid clk id%d\n", id);
244 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
246 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
247 CLK_CTRL_SRCSEL_SHIFT;
260 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
262 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
263 CLK_CTRL_SRCSEL_SHIFT;
274 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
276 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
277 CLK_CTRL_SRCSEL_SHIFT;
290 static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
292 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
293 CLK_CTRL_SRCSEL_SHIFT;
306 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
307 struct zynqmp_clk_priv *priv,
313 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
314 PLLCTRL_POST_SRC_SHFT;
316 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
317 PLLCTRL_POST_SRC_SHFT;
321 return priv->video_clk;
323 return priv->pss_alt_ref_clk;
325 return priv->aux_ref_clk;
327 return priv->gt_crx_ref_clk;
330 return priv->ps_clk_freq;
334 static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
337 u32 clk_ctrl, reset, mul;
341 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
343 printf("%s mio read fail\n", __func__);
347 if (clk_ctrl & PLLCTRL_BYPASS_MASK)
348 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
350 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);
352 reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
353 if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))
356 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
360 if (clk_ctrl & (1 << 16))
366 static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
372 unsigned long pllrate;
374 ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
376 printf("%s mio read fail\n", __func__);
380 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
382 pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
383 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
384 if (IS_ERR_VALUE(pllrate))
387 return DIV_ROUND_CLOSEST(pllrate, div);
390 static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
397 ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
399 printf("%s mio read fail\n", __func__);
403 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
405 pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
406 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
407 if (IS_ERR_VALUE(pllrate))
410 return DIV_ROUND_CLOSEST(pllrate, div);
413 static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
414 enum zynqmp_clk id, bool two_divs)
422 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
424 printf("%s mio read fail\n", __func__);
428 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
433 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
438 pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
439 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
440 if (IS_ERR_VALUE(pllrate))
445 DIV_ROUND_CLOSEST(pllrate, div0), div1);
448 static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
449 enum zynqmp_clk id, bool two_divs)
457 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
459 printf("%d %s mio read fail\n", __LINE__, __func__);
463 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
467 pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
469 ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
471 printf("%d %s mio read fail\n", __LINE__, __func__);
474 div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
479 if (pll == iopll_to_fpd)
482 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
483 if (IS_ERR_VALUE(pllrate))
488 DIV_ROUND_CLOSEST(pllrate, div0), div1);
491 static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
493 u32 *div0, u32 *div1)
495 long new_err, best_err = (long)(~0UL >> 1);
496 ulong new_rate, best_rate = 0;
499 for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
500 for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
501 new_rate = DIV_ROUND_CLOSEST(
502 DIV_ROUND_CLOSEST(pll_rate, d0), d1);
503 new_err = abs(new_rate - rate);
505 if (new_err < best_err) {
509 best_rate = new_rate;
517 static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
518 enum zynqmp_clk id, ulong rate,
522 u32 clk_ctrl, div0 = 0, div1 = 0;
523 ulong pll_rate, new_rate;
528 reg = zynqmp_clk_get_register(id);
529 ret = zynqmp_mmio_read(reg, &clk_ctrl);
531 printf("%s mio read fail\n", __func__);
535 pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
536 pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
537 if (IS_ERR_VALUE(pll_rate))
540 clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
542 clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
543 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate,
545 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
547 div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
548 if (div0 > ZYNQ_CLK_MAXDIV)
549 div0 = ZYNQ_CLK_MAXDIV;
550 new_rate = DIV_ROUND_CLOSEST(rate, div0);
552 clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
554 mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
555 (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
557 ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
559 printf("%s mio write fail\n", __func__);
566 static ulong zynqmp_clk_get_rate(struct clk *clk)
568 struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
569 enum zynqmp_clk id = clk->id;
570 bool two_divs = false;
574 return zynqmp_clk_get_pll_rate(priv, id);
576 return zynqmp_clk_get_cpu_rate(priv, id);
578 return zynqmp_clk_get_ddr_rate(priv);
579 case gem0_ref ... gem3_ref:
580 case qspi_ref ... can1_ref:
583 return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
586 return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
592 static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
594 struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
595 enum zynqmp_clk id = clk->id;
596 bool two_divs = true;
599 case gem0_ref ... gem3_ref:
600 case qspi_ref ... can1_ref:
601 return zynqmp_clk_set_peripheral_rate(priv, id,
608 int soc_clk_dump(void)
613 ret = uclass_get_device_by_driver(UCLASS_CLK,
614 DM_GET_DRIVER(zynqmp_clk), &dev);
618 printf("clk\t\tfrequency\n");
619 for (i = 0; i < clk_max; i++) {
620 const char *name = clk_names[i];
626 ret = clk_request(dev, &clk);
630 rate = clk_get_rate(&clk);
634 if ((rate == (unsigned long)-ENOSYS) ||
635 (rate == (unsigned long)-ENXIO) ||
636 (rate == (unsigned long)-EIO))
637 printf("%10s%20s\n", name, "unknown");
639 printf("%10s%20lu\n", name, rate);
646 static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
651 ret = clk_get_by_name(dev, name, &clk);
653 dev_err(dev, "failed to get %s\n", name);
657 *freq = clk_get_rate(&clk);
658 if (IS_ERR_VALUE(*freq)) {
659 dev_err(dev, "failed to get rate %s\n", name);
665 static int zynqmp_clk_probe(struct udevice *dev)
668 struct zynqmp_clk_priv *priv = dev_get_priv(dev);
670 debug("%s\n", __func__);
671 ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq);
675 ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk);
679 ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev,
680 &priv->pss_alt_ref_clk);
684 ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk);
688 ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev,
689 &priv->gt_crx_ref_clk);
696 static struct clk_ops zynqmp_clk_ops = {
697 .set_rate = zynqmp_clk_set_rate,
698 .get_rate = zynqmp_clk_get_rate,
701 static const struct udevice_id zynqmp_clk_ids[] = {
702 { .compatible = "xlnx,zynqmp-clk" },
703 { .compatible = "xlnx,zynqmp-clkc" },
707 U_BOOT_DRIVER(zynqmp_clk) = {
708 .name = "zynqmp-clk",
710 .of_match = zynqmp_clk_ids,
711 .probe = zynqmp_clk_probe,
712 .ops = &zynqmp_clk_ops,
713 .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),