2 * Renesas RCar Gen3 CPG MSSR driver
4 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
6 * Based on the following driver from Linux kernel:
7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 * Copyright (C) 2016 Glider bvba
11 * SPDX-License-Identifier: GPL-2.0+
14 #ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
15 #define __DRIVERS_CLK_RENESAS_CPG_MSSR__
17 struct cpg_mssr_info {
18 const struct cpg_core_clk *core_clk;
19 unsigned int core_clk_size;
20 const struct mssr_mod_clk *mod_clk;
21 unsigned int mod_clk_size;
22 const struct mstp_stop_table *mstp_table;
23 unsigned int mstp_table_size;
24 const char *reset_node;
25 const char *extalr_node;
28 struct gen3_clk_priv {
30 struct cpg_mssr_info *info;
32 struct clk clk_extalr;
33 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
37 * Definitions of CPG Core Clocks
40 * - Clock outputs exported to DT
41 * - External input clocks
42 * - Internal CPG clocks
49 /* Depending on type */
50 unsigned int parent; /* Core Clocks only */
58 CLK_TYPE_IN, /* External Clock Input */
59 CLK_TYPE_FF, /* Fixed Factor Clock */
61 /* Custom definitions start here */
65 #define DEF_TYPE(_name, _id, _type...) \
66 { .name = _name, .id = _id, .type = _type }
67 #define DEF_BASE(_name, _id, _type, _parent...) \
68 DEF_TYPE(_name, _id, _type, .parent = _parent)
70 #define DEF_INPUT(_name, _id) \
71 DEF_TYPE(_name, _id, CLK_TYPE_IN)
72 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
73 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
74 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
75 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
76 #define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
77 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
78 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
80 DEF_BASE(_name, _id, CLK_TYPE_FF, \
81 (_parent_clean), .div = (_div_clean), 1)
84 * Definitions of Module Clocks
89 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
92 /* Convert from sparse base-100 to packed index space */
93 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
95 #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
97 #define DEF_MOD(_name, _mod, _parent...) \
98 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
100 enum rcar_gen3_clk_types {
101 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
114 struct rcar_gen3_cpg_pll_config {
115 unsigned int extal_div;
116 unsigned int pll1_mult;
117 unsigned int pll3_mult;
120 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
123 /* Core Clock Outputs exported to DT */
124 LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
126 /* External Input Clocks */
130 /* Internal Core Clocks */
157 struct mstp_stop_table {
163 #define TSTR0_STR0 BIT(0)
165 int gen3_clk_probe(struct udevice *dev);
166 int gen3_clk_remove(struct udevice *dev);
168 extern const struct clk_ops gen3_clk_ops;
170 #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */