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[u-boot] / drivers / clk / rockchip / clk_rk3288.c
1 /*
2  * (C) Copyright 2015 Google, Inc
3  *
4  * SPDX-License-Identifier:     GPL-2.0
5  */
6
7 #include <common.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <dt-structs.h>
11 #include <errno.h>
12 #include <mapmem.h>
13 #include <syscon.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/cru_rk3288.h>
17 #include <asm/arch/grf_rk3288.h>
18 #include <asm/arch/hardware.h>
19 #include <dt-bindings/clock/rk3288-cru.h>
20 #include <dm/device-internal.h>
21 #include <dm/lists.h>
22 #include <dm/uclass-internal.h>
23 #include <linux/log2.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 struct rk3288_clk_plat {
28 #if CONFIG_IS_ENABLED(OF_PLATDATA)
29         struct dtd_rockchip_rk3288_cru dtd;
30 #endif
31 };
32
33 struct pll_div {
34         u32 nr;
35         u32 nf;
36         u32 no;
37 };
38
39 enum {
40         VCO_MAX_HZ      = 2200U * 1000000,
41         VCO_MIN_HZ      = 440 * 1000000,
42         OUTPUT_MAX_HZ   = 2200U * 1000000,
43         OUTPUT_MIN_HZ   = 27500000,
44         FREF_MAX_HZ     = 2200U * 1000000,
45         FREF_MIN_HZ     = 269 * 1000,
46 };
47
48 enum {
49         /* PLL CON0 */
50         PLL_OD_MASK             = 0x0f,
51
52         /* PLL CON1 */
53         PLL_NF_MASK             = 0x1fff,
54
55         /* PLL CON2 */
56         PLL_BWADJ_MASK          = 0x0fff,
57
58         /* PLL CON3 */
59         PLL_RESET_SHIFT         = 5,
60
61         /* CLKSEL0 */
62         CORE_SEL_PLL_MASK       = 1,
63         CORE_SEL_PLL_SHIFT      = 15,
64         A17_DIV_MASK            = 0x1f,
65         A17_DIV_SHIFT           = 8,
66         MP_DIV_MASK             = 0xf,
67         MP_DIV_SHIFT            = 4,
68         M0_DIV_MASK             = 0xf,
69         M0_DIV_SHIFT            = 0,
70
71         /* CLKSEL1: pd bus clk pll sel: codec or general */
72         PD_BUS_SEL_PLL_MASK     = 15,
73         PD_BUS_SEL_CPLL         = 0,
74         PD_BUS_SEL_GPLL,
75
76         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
77         PD_BUS_PCLK_DIV_SHIFT   = 12,
78         PD_BUS_PCLK_DIV_MASK    = 7,
79
80         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
81         PD_BUS_HCLK_DIV_SHIFT   = 8,
82         PD_BUS_HCLK_DIV_MASK    = 3,
83
84         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
85         PD_BUS_ACLK_DIV0_SHIFT  = 3,
86         PD_BUS_ACLK_DIV0_MASK   = 0x1f,
87         PD_BUS_ACLK_DIV1_SHIFT  = 0,
88         PD_BUS_ACLK_DIV1_MASK   = 0x7,
89
90         /*
91          * CLKSEL10
92          * peripheral bus pclk div:
93          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
94          */
95         PERI_SEL_PLL_MASK        = 1,
96         PERI_SEL_PLL_SHIFT       = 15,
97         PERI_SEL_CPLL           = 0,
98         PERI_SEL_GPLL,
99
100         PERI_PCLK_DIV_SHIFT     = 12,
101         PERI_PCLK_DIV_MASK      = 3,
102
103         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
104         PERI_HCLK_DIV_SHIFT     = 8,
105         PERI_HCLK_DIV_MASK      = 3,
106
107         /*
108          * peripheral bus aclk div:
109          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
110          */
111         PERI_ACLK_DIV_SHIFT     = 0,
112         PERI_ACLK_DIV_MASK      = 0x1f,
113
114         SOCSTS_DPLL_LOCK        = 1 << 5,
115         SOCSTS_APLL_LOCK        = 1 << 6,
116         SOCSTS_CPLL_LOCK        = 1 << 7,
117         SOCSTS_GPLL_LOCK        = 1 << 8,
118         SOCSTS_NPLL_LOCK        = 1 << 9,
119 };
120
121 #define RATE_TO_DIV(input_rate, output_rate) \
122         ((input_rate) / (output_rate) - 1);
123
124 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
125
126 #define PLL_DIVISORS(hz, _nr, _no) {\
127         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
128         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
129                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
130                        "divisors on line " __stringify(__LINE__));
131
132 /* Keep divisors as low as possible to reduce jitter and power usage */
133 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
134 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
135 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
136
137 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
138                          const struct pll_div *div)
139 {
140         int pll_id = rk_pll_id(clk_id);
141         struct rk3288_pll *pll = &cru->pll[pll_id];
142         /* All PLLs have same VCO and output frequency range restrictions. */
143         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
144         uint output_hz = vco_hz / div->no;
145
146         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
147               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
148         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
149                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
150                (div->no == 1 || !(div->no % 2)));
151
152         /* enter reset */
153         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
154
155         rk_clrsetreg(&pll->con0,
156                      CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
157                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
158         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
159         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
160
161         udelay(10);
162
163         /* return from reset */
164         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
165
166         return 0;
167 }
168
169 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
170                                unsigned int hz)
171 {
172         static const struct pll_div dpll_cfg[] = {
173                 {.nf = 25, .nr = 2, .no = 1},
174                 {.nf = 400, .nr = 9, .no = 2},
175                 {.nf = 500, .nr = 9, .no = 2},
176                 {.nf = 100, .nr = 3, .no = 1},
177         };
178         int cfg;
179
180         switch (hz) {
181         case 300000000:
182                 cfg = 0;
183                 break;
184         case 533000000: /* actually 533.3P MHz */
185                 cfg = 1;
186                 break;
187         case 666000000: /* actually 666.6P MHz */
188                 cfg = 2;
189                 break;
190         case 800000000:
191                 cfg = 3;
192                 break;
193         default:
194                 debug("Unsupported SDRAM frequency");
195                 return -EINVAL;
196         }
197
198         /* pll enter slow-mode */
199         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
200                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
201
202         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
203
204         /* wait for pll lock */
205         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
206                 udelay(1);
207
208         /* PLL enter normal-mode */
209         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
210                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
211
212         return 0;
213 }
214
215 #ifndef CONFIG_SPL_BUILD
216 #define VCO_MAX_KHZ     2200000
217 #define VCO_MIN_KHZ     440000
218 #define FREF_MAX_KHZ    2200000
219 #define FREF_MIN_KHZ    269
220
221 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
222 {
223         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
224         uint fref_khz;
225         uint diff_khz, best_diff_khz;
226         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
227         uint vco_khz;
228         uint no = 1;
229         uint freq_khz = freq_hz / 1000;
230
231         if (!freq_hz) {
232                 printf("%s: the frequency can not be 0 Hz\n", __func__);
233                 return -EINVAL;
234         }
235
236         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
237         if (ext_div) {
238                 *ext_div = DIV_ROUND_UP(no, max_no);
239                 no = DIV_ROUND_UP(no, *ext_div);
240         }
241
242         /* only even divisors (and 1) are supported */
243         if (no > 1)
244                 no = DIV_ROUND_UP(no, 2) * 2;
245
246         vco_khz = freq_khz * no;
247         if (ext_div)
248                 vco_khz *= *ext_div;
249
250         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
251                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
252                        __func__, freq_hz);
253                 return -1;
254         }
255
256         div->no = no;
257
258         best_diff_khz = vco_khz;
259         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
260                 fref_khz = ref_khz / nr;
261                 if (fref_khz < FREF_MIN_KHZ)
262                         break;
263                 if (fref_khz > FREF_MAX_KHZ)
264                         continue;
265
266                 nf = vco_khz / fref_khz;
267                 if (nf >= max_nf)
268                         continue;
269                 diff_khz = vco_khz - nf * fref_khz;
270                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
271                         nf++;
272                         diff_khz = fref_khz - diff_khz;
273                 }
274
275                 if (diff_khz >= best_diff_khz)
276                         continue;
277
278                 best_diff_khz = diff_khz;
279                 div->nr = nr;
280                 div->nf = nf;
281         }
282
283         if (best_diff_khz > 4 * 1000) {
284                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
285                        __func__, freq_hz, best_diff_khz * 1000);
286                 return -EINVAL;
287         }
288
289         return 0;
290 }
291
292 static int rockchip_mac_set_clk(struct rk3288_cru *cru,
293                                   int periph, uint freq)
294 {
295         /* Assuming mac_clk is fed by an external clock */
296         rk_clrsetreg(&cru->cru_clksel_con[21],
297                      RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
298                      RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
299
300          return 0;
301 }
302
303 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
304                                 int periph, unsigned int rate_hz)
305 {
306         struct pll_div npll_config = {0};
307         u32 lcdc_div;
308         int ret;
309
310         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
311         if (ret)
312                 return ret;
313
314         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
315                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
316         rkclk_set_pll(cru, CLK_NEW, &npll_config);
317
318         /* waiting for pll lock */
319         while (1) {
320                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
321                         break;
322                 udelay(1);
323         }
324
325         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
326                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
327
328         /* vop dclk source clk: npll,dclk_div: 1 */
329         switch (periph) {
330         case DCLK_VOP0:
331                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
332                              (lcdc_div - 1) << 8 | 2 << 0);
333                 break;
334         case DCLK_VOP1:
335                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
336                              (lcdc_div - 1) << 8 | 2 << 6);
337                 break;
338         }
339
340         return 0;
341 }
342 #endif
343
344 #ifdef CONFIG_SPL_BUILD
345 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
346 {
347         u32 aclk_div;
348         u32 hclk_div;
349         u32 pclk_div;
350
351         /* pll enter slow-mode */
352         rk_clrsetreg(&cru->cru_mode_con,
353                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
354                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
355                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
356                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
357
358         /* init pll */
359         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
360         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
361
362         /* waiting for pll lock */
363         while ((readl(&grf->soc_status[1]) &
364                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
365                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
366                 udelay(1);
367
368         /*
369          * pd_bus clock pll source selection and
370          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
371          */
372         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
373         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
374         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
375         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
376                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
377
378         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
379         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
380                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
381
382         rk_clrsetreg(&cru->cru_clksel_con[1],
383                      PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
384                      PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
385                      PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
386                      PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
387                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
388                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
389                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
390                      0 << 0);
391
392         /*
393          * peri clock pll source selection and
394          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
395          */
396         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
397         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
398
399         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
400         assert((1 << hclk_div) * PERI_HCLK_HZ ==
401                 PERI_ACLK_HZ && (hclk_div < 0x4));
402
403         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
404         assert((1 << pclk_div) * PERI_PCLK_HZ ==
405                 PERI_ACLK_HZ && (pclk_div < 0x4));
406
407         rk_clrsetreg(&cru->cru_clksel_con[10],
408                      PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
409                      PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
410                      PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
411                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
412                      pclk_div << PERI_PCLK_DIV_SHIFT |
413                      hclk_div << PERI_HCLK_DIV_SHIFT |
414                      aclk_div << PERI_ACLK_DIV_SHIFT);
415
416         /* PLL enter normal-mode */
417         rk_clrsetreg(&cru->cru_mode_con,
418                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
419                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
420                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
421                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
422 }
423 #endif
424
425 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
426 {
427         /* pll enter slow-mode */
428         rk_clrsetreg(&cru->cru_mode_con,
429                      APLL_MODE_MASK << APLL_MODE_SHIFT,
430                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
431
432         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
433
434         /* waiting for pll lock */
435         while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
436                 udelay(1);
437
438         /*
439          * core clock pll source selection and
440          * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
441          * core clock select apll, apll clk = 1800MHz
442          * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
443          */
444         rk_clrsetreg(&cru->cru_clksel_con[0],
445                      CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT |
446                      A17_DIV_MASK << A17_DIV_SHIFT |
447                      MP_DIV_MASK << MP_DIV_SHIFT |
448                      M0_DIV_MASK << M0_DIV_SHIFT,
449                      0 << A17_DIV_SHIFT |
450                      3 << MP_DIV_SHIFT |
451                      1 << M0_DIV_SHIFT);
452
453         /*
454          * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
455          * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
456          */
457         rk_clrsetreg(&cru->cru_clksel_con[37],
458                      CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT |
459                      ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT |
460                      PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT,
461                      1 << CLK_L2RAM_DIV_SHIFT |
462                      3 << ATCLK_CORE_DIV_CON_SHIFT |
463                      3 << PCLK_CORE_DBG_DIV_SHIFT);
464
465         /* PLL enter normal-mode */
466         rk_clrsetreg(&cru->cru_mode_con,
467                      APLL_MODE_MASK << APLL_MODE_SHIFT,
468                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
469 }
470
471 /* Get pll rate by id */
472 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
473                                    enum rk_clk_id clk_id)
474 {
475         uint32_t nr, no, nf;
476         uint32_t con;
477         int pll_id = rk_pll_id(clk_id);
478         struct rk3288_pll *pll = &cru->pll[pll_id];
479         static u8 clk_shift[CLK_COUNT] = {
480                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
481                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
482         };
483         uint shift;
484
485         con = readl(&cru->cru_mode_con);
486         shift = clk_shift[clk_id];
487         switch ((con >> shift) & APLL_MODE_MASK) {
488         case APLL_MODE_SLOW:
489                 return OSC_HZ;
490         case APLL_MODE_NORMAL:
491                 /* normal mode */
492                 con = readl(&pll->con0);
493                 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
494                 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
495                 con = readl(&pll->con1);
496                 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
497
498                 return (24 * nf / (nr * no)) * 1000000;
499         case APLL_MODE_DEEP:
500         default:
501                 return 32768;
502         }
503 }
504
505 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
506                                   int periph)
507 {
508         uint src_rate;
509         uint div, mux;
510         u32 con;
511
512         switch (periph) {
513         case HCLK_EMMC:
514                 con = readl(&cru->cru_clksel_con[12]);
515                 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
516                 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
517                 break;
518         case HCLK_SDMMC:
519                 con = readl(&cru->cru_clksel_con[11]);
520                 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
521                 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
522                 break;
523         case HCLK_SDIO0:
524                 con = readl(&cru->cru_clksel_con[12]);
525                 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
526                 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
527                 break;
528         default:
529                 return -EINVAL;
530         }
531
532         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
533         return DIV_TO_RATE(src_rate, div);
534 }
535
536 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
537                                   int  periph, uint freq)
538 {
539         int src_clk_div;
540         int mux;
541
542         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
543         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
544
545         if (src_clk_div > 0x3f) {
546                 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
547                 mux = EMMC_PLL_SELECT_24MHZ;
548                 assert((int)EMMC_PLL_SELECT_24MHZ ==
549                        (int)MMC0_PLL_SELECT_24MHZ);
550         } else {
551                 mux = EMMC_PLL_SELECT_GENERAL;
552                 assert((int)EMMC_PLL_SELECT_GENERAL ==
553                        (int)MMC0_PLL_SELECT_GENERAL);
554         }
555         switch (periph) {
556         case HCLK_EMMC:
557                 rk_clrsetreg(&cru->cru_clksel_con[12],
558                              EMMC_PLL_MASK << EMMC_PLL_SHIFT |
559                              EMMC_DIV_MASK << EMMC_DIV_SHIFT,
560                              mux << EMMC_PLL_SHIFT |
561                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
562                 break;
563         case HCLK_SDMMC:
564                 rk_clrsetreg(&cru->cru_clksel_con[11],
565                              MMC0_PLL_MASK << MMC0_PLL_SHIFT |
566                              MMC0_DIV_MASK << MMC0_DIV_SHIFT,
567                              mux << MMC0_PLL_SHIFT |
568                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
569                 break;
570         case HCLK_SDIO0:
571                 rk_clrsetreg(&cru->cru_clksel_con[12],
572                              SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
573                              SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
574                              mux << SDIO0_PLL_SHIFT |
575                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
576                 break;
577         default:
578                 return -EINVAL;
579         }
580
581         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
582 }
583
584 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
585                                   int periph)
586 {
587         uint div, mux;
588         u32 con;
589
590         switch (periph) {
591         case SCLK_SPI0:
592                 con = readl(&cru->cru_clksel_con[25]);
593                 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
594                 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
595                 break;
596         case SCLK_SPI1:
597                 con = readl(&cru->cru_clksel_con[25]);
598                 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
599                 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
600                 break;
601         case SCLK_SPI2:
602                 con = readl(&cru->cru_clksel_con[39]);
603                 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
604                 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
605                 break;
606         default:
607                 return -EINVAL;
608         }
609         assert(mux == SPI0_PLL_SELECT_GENERAL);
610
611         return DIV_TO_RATE(gclk_rate, div);
612 }
613
614 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
615                                   int periph, uint freq)
616 {
617         int src_clk_div;
618
619         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
620         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
621         switch (periph) {
622         case SCLK_SPI0:
623                 rk_clrsetreg(&cru->cru_clksel_con[25],
624                              SPI0_PLL_MASK << SPI0_PLL_SHIFT |
625                              SPI0_DIV_MASK << SPI0_DIV_SHIFT,
626                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
627                              src_clk_div << SPI0_DIV_SHIFT);
628                 break;
629         case SCLK_SPI1:
630                 rk_clrsetreg(&cru->cru_clksel_con[25],
631                              SPI1_PLL_MASK << SPI1_PLL_SHIFT |
632                              SPI1_DIV_MASK << SPI1_DIV_SHIFT,
633                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
634                              src_clk_div << SPI1_DIV_SHIFT);
635                 break;
636         case SCLK_SPI2:
637                 rk_clrsetreg(&cru->cru_clksel_con[39],
638                              SPI2_PLL_MASK << SPI2_PLL_SHIFT |
639                              SPI2_DIV_MASK << SPI2_DIV_SHIFT,
640                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
641                              src_clk_div << SPI2_DIV_SHIFT);
642                 break;
643         default:
644                 return -EINVAL;
645         }
646
647         return rockchip_spi_get_clk(cru, gclk_rate, periph);
648 }
649
650 static ulong rk3288_clk_get_rate(struct clk *clk)
651 {
652         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
653         ulong new_rate, gclk_rate;
654
655         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
656         switch (clk->id) {
657         case 0 ... 63:
658                 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
659                 break;
660         case HCLK_EMMC:
661         case HCLK_SDMMC:
662         case HCLK_SDIO0:
663                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
664                 break;
665         case SCLK_SPI0:
666         case SCLK_SPI1:
667         case SCLK_SPI2:
668                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
669                 break;
670         case PCLK_I2C0:
671         case PCLK_I2C1:
672         case PCLK_I2C2:
673         case PCLK_I2C3:
674         case PCLK_I2C4:
675         case PCLK_I2C5:
676                 return gclk_rate;
677         case PCLK_PWM:
678                 return PD_BUS_PCLK_HZ;
679         default:
680                 return -ENOENT;
681         }
682
683         return new_rate;
684 }
685
686 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
687 {
688         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
689         struct rk3288_cru *cru = priv->cru;
690         ulong new_rate, gclk_rate;
691
692         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
693         switch (clk->id) {
694         case CLK_DDR:
695                 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
696                 break;
697         case HCLK_EMMC:
698         case HCLK_SDMMC:
699         case HCLK_SDIO0:
700                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
701                 break;
702         case SCLK_SPI0:
703         case SCLK_SPI1:
704         case SCLK_SPI2:
705                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
706                 break;
707 #ifndef CONFIG_SPL_BUILD
708         case SCLK_MAC:
709                 new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
710                 break;
711         case DCLK_VOP0:
712         case DCLK_VOP1:
713                 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
714                 break;
715         case SCLK_EDP_24M:
716                 /* clk_edp_24M source: 24M */
717                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
718
719                 /* rst edp */
720                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
721                 udelay(1);
722                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
723                 new_rate = rate;
724                 break;
725         case ACLK_VOP0:
726         case ACLK_VOP1: {
727                 u32 div;
728
729                 /* vop aclk source clk: cpll */
730                 div = CPLL_HZ / rate;
731                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
732
733                 switch (clk->id) {
734                 case ACLK_VOP0:
735                         rk_clrsetreg(&cru->cru_clksel_con[31],
736                                      3 << 6 | 0x1f << 0,
737                                      0 << 6 | (div - 1) << 0);
738                         break;
739                 case ACLK_VOP1:
740                         rk_clrsetreg(&cru->cru_clksel_con[31],
741                                      3 << 14 | 0x1f << 8,
742                                      0 << 14 | (div - 1) << 8);
743                         break;
744                 }
745                 new_rate = rate;
746                 break;
747         }
748         case PCLK_HDMI_CTRL:
749                 /* enable pclk hdmi ctrl */
750                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
751
752                 /* software reset hdmi */
753                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
754                 udelay(1);
755                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
756                 new_rate = rate;
757                 break;
758 #endif
759         default:
760                 return -ENOENT;
761         }
762
763         return new_rate;
764 }
765
766 static struct clk_ops rk3288_clk_ops = {
767         .get_rate       = rk3288_clk_get_rate,
768         .set_rate       = rk3288_clk_set_rate,
769 };
770
771 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
772 {
773 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
774         struct rk3288_clk_priv *priv = dev_get_priv(dev);
775
776         priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
777 #endif
778
779         return 0;
780 }
781
782 static int rk3288_clk_probe(struct udevice *dev)
783 {
784         struct rk3288_clk_priv *priv = dev_get_priv(dev);
785
786         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
787         if (IS_ERR(priv->grf))
788                 return PTR_ERR(priv->grf);
789 #ifdef CONFIG_SPL_BUILD
790 #if CONFIG_IS_ENABLED(OF_PLATDATA)
791         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
792
793         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
794 #endif
795         rkclk_init(priv->cru, priv->grf);
796 #endif
797
798         return 0;
799 }
800
801 static int rk3288_clk_bind(struct udevice *dev)
802 {
803         int ret;
804
805         /* The reset driver does not have a device node, so bind it here */
806         ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
807         if (ret)
808                 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
809
810         return 0;
811 }
812
813 static const struct udevice_id rk3288_clk_ids[] = {
814         { .compatible = "rockchip,rk3288-cru" },
815         { }
816 };
817
818 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
819         .name           = "rockchip_rk3288_cru",
820         .id             = UCLASS_CLK,
821         .of_match       = rk3288_clk_ids,
822         .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
823         .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
824         .ops            = &rk3288_clk_ops,
825         .bind           = rk3288_clk_bind,
826         .ofdata_to_platdata     = rk3288_clk_ofdata_to_platdata,
827         .probe          = rk3288_clk_probe,
828 };