2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/cru_rk3288.h>
17 #include <asm/arch/grf_rk3288.h>
18 #include <asm/arch/hardware.h>
19 #include <dt-bindings/clock/rk3288-cru.h>
20 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
23 #include <linux/log2.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 struct rk3288_clk_plat {
28 #if CONFIG_IS_ENABLED(OF_PLATDATA)
29 struct dtd_rockchip_rk3288_cru dtd;
40 VCO_MAX_HZ = 2200U * 1000000,
41 VCO_MIN_HZ = 440 * 1000000,
42 OUTPUT_MAX_HZ = 2200U * 1000000,
43 OUTPUT_MIN_HZ = 27500000,
44 FREF_MAX_HZ = 2200U * 1000000,
45 FREF_MIN_HZ = 269 * 1000,
56 PLL_BWADJ_MASK = 0x0fff,
62 CORE_SEL_PLL_SHIFT = 15,
63 CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT,
65 A17_DIV_MASK = 0x1f << A17_DIV_SHIFT,
67 MP_DIV_MASK = 0xf << MP_DIV_SHIFT,
69 M0_DIV_MASK = 0xf << M0_DIV_SHIFT,
71 /* CLKSEL1: pd bus clk pll sel: codec or general */
72 PD_BUS_SEL_PLL_MASK = 15,
76 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
77 PD_BUS_PCLK_DIV_SHIFT = 12,
78 PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT,
80 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
81 PD_BUS_HCLK_DIV_SHIFT = 8,
82 PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT,
84 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
85 PD_BUS_ACLK_DIV0_SHIFT = 3,
86 PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
87 PD_BUS_ACLK_DIV1_SHIFT = 0,
88 PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
92 * peripheral bus pclk div:
93 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
95 PERI_SEL_PLL_SHIFT = 15,
96 PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT,
100 PERI_PCLK_DIV_SHIFT = 12,
101 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
103 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
104 PERI_HCLK_DIV_SHIFT = 8,
105 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
108 * peripheral bus aclk div:
109 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
111 PERI_ACLK_DIV_SHIFT = 0,
112 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
114 SOCSTS_DPLL_LOCK = 1 << 5,
115 SOCSTS_APLL_LOCK = 1 << 6,
116 SOCSTS_CPLL_LOCK = 1 << 7,
117 SOCSTS_GPLL_LOCK = 1 << 8,
118 SOCSTS_NPLL_LOCK = 1 << 9,
121 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
123 #define PLL_DIVISORS(hz, _nr, _no) {\
124 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
125 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
126 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
127 "divisors on line " __stringify(__LINE__));
129 /* Keep divisors as low as possible to reduce jitter and power usage */
130 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
131 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
132 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
134 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
135 const struct pll_div *div)
137 int pll_id = rk_pll_id(clk_id);
138 struct rk3288_pll *pll = &cru->pll[pll_id];
139 /* All PLLs have same VCO and output frequency range restrictions. */
140 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
141 uint output_hz = vco_hz / div->no;
143 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
144 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
145 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
146 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
147 (div->no == 1 || !(div->no % 2)));
150 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
152 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
153 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
154 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
155 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
159 /* return from reset */
160 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
165 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
168 static const struct pll_div dpll_cfg[] = {
169 {.nf = 25, .nr = 2, .no = 1},
170 {.nf = 400, .nr = 9, .no = 2},
171 {.nf = 500, .nr = 9, .no = 2},
172 {.nf = 100, .nr = 3, .no = 1},
180 case 533000000: /* actually 533.3P MHz */
183 case 666000000: /* actually 666.6P MHz */
190 debug("Unsupported SDRAM frequency");
194 /* pll enter slow-mode */
195 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
196 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
198 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
200 /* wait for pll lock */
201 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
204 /* PLL enter normal-mode */
205 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
206 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
211 #ifndef CONFIG_SPL_BUILD
212 #define VCO_MAX_KHZ 2200000
213 #define VCO_MIN_KHZ 440000
214 #define FREF_MAX_KHZ 2200000
215 #define FREF_MIN_KHZ 269
217 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
219 uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
221 uint diff_khz, best_diff_khz;
222 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
225 uint freq_khz = freq_hz / 1000;
228 printf("%s: the frequency can not be 0 Hz\n", __func__);
232 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
234 *ext_div = DIV_ROUND_UP(no, max_no);
235 no = DIV_ROUND_UP(no, *ext_div);
238 /* only even divisors (and 1) are supported */
240 no = DIV_ROUND_UP(no, 2) * 2;
242 vco_khz = freq_khz * no;
246 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
247 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
254 best_diff_khz = vco_khz;
255 for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
256 fref_khz = ref_khz / nr;
257 if (fref_khz < FREF_MIN_KHZ)
259 if (fref_khz > FREF_MAX_KHZ)
262 nf = vco_khz / fref_khz;
265 diff_khz = vco_khz - nf * fref_khz;
266 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
268 diff_khz = fref_khz - diff_khz;
271 if (diff_khz >= best_diff_khz)
274 best_diff_khz = diff_khz;
279 if (best_diff_khz > 4 * 1000) {
280 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
281 __func__, freq_hz, best_diff_khz * 1000);
288 static int rockchip_mac_set_clk(struct rk3288_cru *cru,
289 int periph, uint freq)
291 /* Assuming mac_clk is fed by an external clock */
292 rk_clrsetreg(&cru->cru_clksel_con[21],
294 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
299 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
300 int periph, unsigned int rate_hz)
302 struct pll_div npll_config = {0};
306 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
310 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
311 NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
312 rkclk_set_pll(cru, CLK_NEW, &npll_config);
314 /* waiting for pll lock */
316 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
321 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
322 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
324 /* vop dclk source clk: npll,dclk_div: 1 */
327 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
328 (lcdc_div - 1) << 8 | 2 << 0);
331 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
332 (lcdc_div - 1) << 8 | 2 << 6);
338 #endif /* CONFIG_SPL_BUILD */
340 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
346 /* pll enter slow-mode */
347 rk_clrsetreg(&cru->cru_mode_con,
348 GPLL_MODE_MASK | CPLL_MODE_MASK,
349 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
350 CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
353 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
354 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
356 /* waiting for pll lock */
357 while ((readl(&grf->soc_status[1]) &
358 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
359 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
363 * pd_bus clock pll source selection and
364 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
366 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
367 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
368 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
369 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
370 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
372 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
373 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
374 PD_BUS_ACLK_HZ && pclk_div < 0x7);
376 rk_clrsetreg(&cru->cru_clksel_con[1],
377 PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
378 PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
379 pclk_div << PD_BUS_PCLK_DIV_SHIFT |
380 hclk_div << PD_BUS_HCLK_DIV_SHIFT |
381 aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
385 * peri clock pll source selection and
386 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
388 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
389 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
391 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
392 assert((1 << hclk_div) * PERI_HCLK_HZ ==
393 PERI_ACLK_HZ && (hclk_div < 0x4));
395 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
396 assert((1 << pclk_div) * PERI_PCLK_HZ ==
397 PERI_ACLK_HZ && (pclk_div < 0x4));
399 rk_clrsetreg(&cru->cru_clksel_con[10],
400 PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
402 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
403 pclk_div << PERI_PCLK_DIV_SHIFT |
404 hclk_div << PERI_HCLK_DIV_SHIFT |
405 aclk_div << PERI_ACLK_DIV_SHIFT);
407 /* PLL enter normal-mode */
408 rk_clrsetreg(&cru->cru_mode_con,
409 GPLL_MODE_MASK | CPLL_MODE_MASK,
410 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
411 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
414 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
416 /* pll enter slow-mode */
417 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
418 APLL_MODE_SLOW << APLL_MODE_SHIFT);
420 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
422 /* waiting for pll lock */
423 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
427 * core clock pll source selection and
428 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
429 * core clock select apll, apll clk = 1800MHz
430 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
432 rk_clrsetreg(&cru->cru_clksel_con[0],
433 CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
440 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
441 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
443 rk_clrsetreg(&cru->cru_clksel_con[37],
444 CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
445 PCLK_CORE_DBG_DIV_MASK,
446 1 << CLK_L2RAM_DIV_SHIFT |
447 3 << ATCLK_CORE_DIV_CON_SHIFT |
448 3 << PCLK_CORE_DBG_DIV_SHIFT);
450 /* PLL enter normal-mode */
451 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
452 APLL_MODE_NORMAL << APLL_MODE_SHIFT);
455 /* Get pll rate by id */
456 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
457 enum rk_clk_id clk_id)
461 int pll_id = rk_pll_id(clk_id);
462 struct rk3288_pll *pll = &cru->pll[pll_id];
463 static u8 clk_shift[CLK_COUNT] = {
464 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
465 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
469 con = readl(&cru->cru_mode_con);
470 shift = clk_shift[clk_id];
471 switch ((con >> shift) & CRU_MODE_MASK) {
474 case APLL_MODE_NORMAL:
476 con = readl(&pll->con0);
477 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
478 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
479 con = readl(&pll->con1);
480 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
482 return (24 * nf / (nr * no)) * 1000000;
489 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
499 con = readl(&cru->cru_clksel_con[12]);
500 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
501 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
505 con = readl(&cru->cru_clksel_con[11]);
506 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
507 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
511 con = readl(&cru->cru_clksel_con[12]);
512 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
513 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
519 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
520 return DIV_TO_RATE(src_rate, div);
523 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
524 int periph, uint freq)
529 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
530 /* mmc clock default div 2 internal, need provide double in cru */
531 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
533 if (src_clk_div > 0x3f) {
534 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
535 assert(src_clk_div < 0x40);
536 mux = EMMC_PLL_SELECT_24MHZ;
537 assert((int)EMMC_PLL_SELECT_24MHZ ==
538 (int)MMC0_PLL_SELECT_24MHZ);
540 mux = EMMC_PLL_SELECT_GENERAL;
541 assert((int)EMMC_PLL_SELECT_GENERAL ==
542 (int)MMC0_PLL_SELECT_GENERAL);
547 rk_clrsetreg(&cru->cru_clksel_con[12],
548 EMMC_PLL_MASK | EMMC_DIV_MASK,
549 mux << EMMC_PLL_SHIFT |
550 (src_clk_div - 1) << EMMC_DIV_SHIFT);
554 rk_clrsetreg(&cru->cru_clksel_con[11],
555 MMC0_PLL_MASK | MMC0_DIV_MASK,
556 mux << MMC0_PLL_SHIFT |
557 (src_clk_div - 1) << MMC0_DIV_SHIFT);
561 rk_clrsetreg(&cru->cru_clksel_con[12],
562 SDIO0_PLL_MASK | SDIO0_DIV_MASK,
563 mux << SDIO0_PLL_SHIFT |
564 (src_clk_div - 1) << SDIO0_DIV_SHIFT);
570 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
573 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
581 con = readl(&cru->cru_clksel_con[25]);
582 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
583 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
586 con = readl(&cru->cru_clksel_con[25]);
587 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
588 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
591 con = readl(&cru->cru_clksel_con[39]);
592 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
593 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
598 assert(mux == SPI0_PLL_SELECT_GENERAL);
600 return DIV_TO_RATE(gclk_rate, div);
603 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
604 int periph, uint freq)
608 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
609 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
610 assert(src_clk_div < 128);
613 rk_clrsetreg(&cru->cru_clksel_con[25],
614 SPI0_PLL_MASK | SPI0_DIV_MASK,
615 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
616 src_clk_div << SPI0_DIV_SHIFT);
619 rk_clrsetreg(&cru->cru_clksel_con[25],
620 SPI1_PLL_MASK | SPI1_DIV_MASK,
621 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
622 src_clk_div << SPI1_DIV_SHIFT);
625 rk_clrsetreg(&cru->cru_clksel_con[39],
626 SPI2_PLL_MASK | SPI2_DIV_MASK,
627 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
628 src_clk_div << SPI2_DIV_SHIFT);
634 return rockchip_spi_get_clk(cru, gclk_rate, periph);
637 static ulong rk3288_clk_get_rate(struct clk *clk)
639 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
640 ulong new_rate, gclk_rate;
642 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
645 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
653 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
658 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
668 return PD_BUS_PCLK_HZ;
676 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
678 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
679 struct rk3288_cru *cru = priv->cru;
680 ulong new_rate, gclk_rate;
682 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
685 /* We only support a fixed rate here */
686 if (rate != 1800000000)
688 rk3288_clk_configure_cpu(priv->cru, priv->grf);
692 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
700 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
705 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
707 #ifndef CONFIG_SPL_BUILD
709 new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
713 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
716 /* clk_edp_24M source: 24M */
717 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
720 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
722 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
729 /* vop aclk source clk: cpll */
730 div = CPLL_HZ / rate;
731 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
735 rk_clrsetreg(&cru->cru_clksel_con[31],
737 0 << 6 | (div - 1) << 0);
740 rk_clrsetreg(&cru->cru_clksel_con[31],
742 0 << 14 | (div - 1) << 8);
749 /* enable pclk hdmi ctrl */
750 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
752 /* software reset hdmi */
753 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
755 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
766 static struct clk_ops rk3288_clk_ops = {
767 .get_rate = rk3288_clk_get_rate,
768 .set_rate = rk3288_clk_set_rate,
771 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
773 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
774 struct rk3288_clk_priv *priv = dev_get_priv(dev);
776 priv->cru = (struct rk3288_cru *)devfdt_get_addr(dev);
782 static int rk3288_clk_probe(struct udevice *dev)
784 struct rk3288_clk_priv *priv = dev_get_priv(dev);
785 bool init_clocks = false;
787 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
788 if (IS_ERR(priv->grf))
789 return PTR_ERR(priv->grf);
790 #ifdef CONFIG_SPL_BUILD
791 #if CONFIG_IS_ENABLED(OF_PLATDATA)
792 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
794 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
798 if (!(gd->flags & GD_FLG_RELOC)) {
802 * Init clocks in U-Boot proper if the NPLL is runnning. This
803 * indicates that a previous boot loader set up the clocks, so
804 * we need to redo it. U-Boot's SPL does not set this clock.
806 reg = readl(&priv->cru->cru_mode_con);
807 if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
813 rkclk_init(priv->cru, priv->grf);
818 static int rk3288_clk_bind(struct udevice *dev)
822 /* The reset driver does not have a device node, so bind it here */
823 ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
825 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
830 static const struct udevice_id rk3288_clk_ids[] = {
831 { .compatible = "rockchip,rk3288-cru" },
835 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
836 .name = "rockchip_rk3288_cru",
838 .of_match = rk3288_clk_ids,
839 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
840 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
841 .ops = &rk3288_clk_ops,
842 .bind = rk3288_clk_bind,
843 .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata,
844 .probe = rk3288_clk_probe,