git.sur5r.net Git - u-boot/blob - drivers/clk/rockchip/clk_rk3288.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <dt-structs.h>
  11 #include <errno.h>
  12 #include <mapmem.h>
  13 #include <syscon.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/cru_rk3288.h>
  17 #include <asm/arch/grf_rk3288.h>
  18 #include <asm/arch/hardware.h>
  19 #include <dt-bindings/clock/rk3288-cru.h>
  20 #include <dm/device-internal.h>
  21 #include <dm/lists.h>
  22 #include <dm/uclass-internal.h>
  23 #include <linux/log2.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 struct rk3288_clk_plat {
  28 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  29         struct dtd_rockchip_rk3288_cru dtd;
  30 #endif
  31 };
  32
  33 struct pll_div {
  34         u32 nr;
  35         u32 nf;
  36         u32 no;
  37 };
  38
  39 enum {
  40         VCO_MAX_HZ      = 2200U * 1000000,
  41         VCO_MIN_HZ      = 440 * 1000000,
  42         OUTPUT_MAX_HZ   = 2200U * 1000000,
  43         OUTPUT_MIN_HZ   = 27500000,
  44         FREF_MAX_HZ     = 2200U * 1000000,
  45         FREF_MIN_HZ     = 269 * 1000,
  46 };
  47
  48 enum {
  49         /* PLL CON0 */
  50         PLL_OD_MASK             = 0x0f,
  51
  52         /* PLL CON1 */
  53         PLL_NF_MASK             = 0x1fff,
  54
  55         /* PLL CON2 */
  56         PLL_BWADJ_MASK          = 0x0fff,
  57
  58         /* PLL CON3 */
  59         PLL_RESET_SHIFT         = 5,
  60
  61         /* CLKSEL0 */
  62         CORE_SEL_PLL_SHIFT      = 15,
  63         CORE_SEL_PLL_MASK       = 1 << CORE_SEL_PLL_SHIFT,
  64         A17_DIV_SHIFT           = 8,
  65         A17_DIV_MASK            = 0x1f << A17_DIV_SHIFT,
  66         MP_DIV_SHIFT            = 4,
  67         MP_DIV_MASK             = 0xf << MP_DIV_SHIFT,
  68         M0_DIV_SHIFT            = 0,
  69         M0_DIV_MASK             = 0xf << M0_DIV_SHIFT,
  70
  71         /* CLKSEL1: pd bus clk pll sel: codec or general */
  72         PD_BUS_SEL_PLL_MASK     = 15,
  73         PD_BUS_SEL_CPLL         = 0,
  74         PD_BUS_SEL_GPLL,
  75
  76         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  77         PD_BUS_PCLK_DIV_SHIFT   = 12,
  78         PD_BUS_PCLK_DIV_MASK    = 7 << PD_BUS_PCLK_DIV_SHIFT,
  79
  80         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  81         PD_BUS_HCLK_DIV_SHIFT   = 8,
  82         PD_BUS_HCLK_DIV_MASK    = 3 << PD_BUS_HCLK_DIV_SHIFT,
  83
  84         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  85         PD_BUS_ACLK_DIV0_SHIFT  = 3,
  86         PD_BUS_ACLK_DIV0_MASK   = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
  87         PD_BUS_ACLK_DIV1_SHIFT  = 0,
  88         PD_BUS_ACLK_DIV1_MASK   = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
  89
  90         /*
  91          * CLKSEL10
  92          * peripheral bus pclk div:
  93          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
  94          */
  95         PERI_SEL_PLL_SHIFT       = 15,
  96         PERI_SEL_PLL_MASK        = 1 << PERI_SEL_PLL_SHIFT,
  97         PERI_SEL_CPLL           = 0,
  98         PERI_SEL_GPLL,
  99
 100         PERI_PCLK_DIV_SHIFT     = 12,
 101         PERI_PCLK_DIV_MASK      = 3 << PERI_PCLK_DIV_SHIFT,
 102
 103         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
 104         PERI_HCLK_DIV_SHIFT     = 8,
 105         PERI_HCLK_DIV_MASK      = 3 << PERI_HCLK_DIV_SHIFT,
 106
 107         /*
 108          * peripheral bus aclk div:
 109          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
 110          */
 111         PERI_ACLK_DIV_SHIFT     = 0,
 112         PERI_ACLK_DIV_MASK      = 0x1f << PERI_ACLK_DIV_SHIFT,
 113
 114         SOCSTS_DPLL_LOCK        = 1 << 5,
 115         SOCSTS_APLL_LOCK        = 1 << 6,
 116         SOCSTS_CPLL_LOCK        = 1 << 7,
 117         SOCSTS_GPLL_LOCK        = 1 << 8,
 118         SOCSTS_NPLL_LOCK        = 1 << 9,
 119 };
 120
 121 #define RATE_TO_DIV(input_rate, output_rate) \
 122         ((input_rate) / (output_rate) - 1);
 123
 124 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 125
 126 #define PLL_DIVISORS(hz, _nr, _no) {\
 127         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
 128         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
 129                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
 130                        "divisors on line " __stringify(__LINE__));
 131
 132 /* Keep divisors as low as possible to reduce jitter and power usage */
 133 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 134 #ifdef CONFIG_SPL_BUILD
 135 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 136 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 137 #endif
 138
 139 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 140                          const struct pll_div *div)
 141 {
 142         int pll_id = rk_pll_id(clk_id);
 143         struct rk3288_pll *pll = &cru->pll[pll_id];
 144         /* All PLLs have same VCO and output frequency range restrictions. */
 145         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
 146         uint output_hz = vco_hz / div->no;
 147
 148         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 149               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 150         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 151                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 152                (div->no == 1 || !(div->no % 2)));
 153
 154         /* enter reset */
 155         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 156
 157         rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
 158                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 159         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 160         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 161
 162         udelay(10);
 163
 164         /* return from reset */
 165         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 166
 167         return 0;
 168 }
 169
 170 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
 171                                unsigned int hz)
 172 {
 173         static const struct pll_div dpll_cfg[] = {
 174                 {.nf = 25, .nr = 2, .no = 1},
 175                 {.nf = 400, .nr = 9, .no = 2},
 176                 {.nf = 500, .nr = 9, .no = 2},
 177                 {.nf = 100, .nr = 3, .no = 1},
 178         };
 179         int cfg;
 180
 181         switch (hz) {
 182         case 300000000:
 183                 cfg = 0;
 184                 break;
 185         case 533000000: /* actually 533.3P MHz */
 186                 cfg = 1;
 187                 break;
 188         case 666000000: /* actually 666.6P MHz */
 189                 cfg = 2;
 190                 break;
 191         case 800000000:
 192                 cfg = 3;
 193                 break;
 194         default:
 195                 debug("Unsupported SDRAM frequency");
 196                 return -EINVAL;
 197         }
 198
 199         /* pll enter slow-mode */
 200         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 201                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 202
 203         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
 204
 205         /* wait for pll lock */
 206         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
 207                 udelay(1);
 208
 209         /* PLL enter normal-mode */
 210         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 211                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 212
 213         return 0;
 214 }
 215
 216 #ifndef CONFIG_SPL_BUILD
 217 #define VCO_MAX_KHZ     2200000
 218 #define VCO_MIN_KHZ     440000
 219 #define FREF_MAX_KHZ    2200000
 220 #define FREF_MIN_KHZ    269
 221
 222 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 223 {
 224         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
 225         uint fref_khz;
 226         uint diff_khz, best_diff_khz;
 227         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 228         uint vco_khz;
 229         uint no = 1;
 230         uint freq_khz = freq_hz / 1000;
 231
 232         if (!freq_hz) {
 233                 printf("%s: the frequency can not be 0 Hz\n", __func__);
 234                 return -EINVAL;
 235         }
 236
 237         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 238         if (ext_div) {
 239                 *ext_div = DIV_ROUND_UP(no, max_no);
 240                 no = DIV_ROUND_UP(no, *ext_div);
 241         }
 242
 243         /* only even divisors (and 1) are supported */
 244         if (no > 1)
 245                 no = DIV_ROUND_UP(no, 2) * 2;
 246
 247         vco_khz = freq_khz * no;
 248         if (ext_div)
 249                 vco_khz *= *ext_div;
 250
 251         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 252                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
 253                        __func__, freq_hz);
 254                 return -1;
 255         }
 256
 257         div->no = no;
 258
 259         best_diff_khz = vco_khz;
 260         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 261                 fref_khz = ref_khz / nr;
 262                 if (fref_khz < FREF_MIN_KHZ)
 263                         break;
 264                 if (fref_khz > FREF_MAX_KHZ)
 265                         continue;
 266
 267                 nf = vco_khz / fref_khz;
 268                 if (nf >= max_nf)
 269                         continue;
 270                 diff_khz = vco_khz - nf * fref_khz;
 271                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 272                         nf++;
 273                         diff_khz = fref_khz - diff_khz;
 274                 }
 275
 276                 if (diff_khz >= best_diff_khz)
 277                         continue;
 278
 279                 best_diff_khz = diff_khz;
 280                 div->nr = nr;
 281                 div->nf = nf;
 282         }
 283
 284         if (best_diff_khz > 4 * 1000) {
 285                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
 286                        __func__, freq_hz, best_diff_khz * 1000);
 287                 return -EINVAL;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int rockchip_mac_set_clk(struct rk3288_cru *cru,
 294                                   int periph, uint freq)
 295 {
 296         /* Assuming mac_clk is fed by an external clock */
 297         rk_clrsetreg(&cru->cru_clksel_con[21],
 298                      RMII_EXTCLK_MASK,
 299                      RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
 300
 301          return 0;
 302 }
 303
 304 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 305                                 int periph, unsigned int rate_hz)
 306 {
 307         struct pll_div npll_config = {0};
 308         u32 lcdc_div;
 309         int ret;
 310
 311         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
 312         if (ret)
 313                 return ret;
 314
 315         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 316                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 317         rkclk_set_pll(cru, CLK_NEW, &npll_config);
 318
 319         /* waiting for pll lock */
 320         while (1) {
 321                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 322                         break;
 323                 udelay(1);
 324         }
 325
 326         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 327                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 328
 329         /* vop dclk source clk: npll,dclk_div: 1 */
 330         switch (periph) {
 331         case DCLK_VOP0:
 332                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
 333                              (lcdc_div - 1) << 8 | 2 << 0);
 334                 break;
 335         case DCLK_VOP1:
 336                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
 337                              (lcdc_div - 1) << 8 | 2 << 6);
 338                 break;
 339         }
 340
 341         return 0;
 342 }
 343 #endif
 344
 345 #ifdef CONFIG_SPL_BUILD
 346 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 347 {
 348         u32 aclk_div;
 349         u32 hclk_div;
 350         u32 pclk_div;
 351
 352         /* pll enter slow-mode */
 353         rk_clrsetreg(&cru->cru_mode_con,
 354                      GPLL_MODE_MASK | CPLL_MODE_MASK,
 355                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 356                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 357
 358         /* init pll */
 359         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 360         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 361
 362         /* waiting for pll lock */
 363         while ((readl(&grf->soc_status[1]) &
 364                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 365                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 366                 udelay(1);
 367
 368         /*
 369          * pd_bus clock pll source selection and
 370          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 371          */
 372         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 373         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 374         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 375         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 376                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
 377
 378         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 379         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 380                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
 381
 382         rk_clrsetreg(&cru->cru_clksel_con[1],
 383                      PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
 384                      PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
 385                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 386                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 387                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
 388                      0 << 0);
 389
 390         /*
 391          * peri clock pll source selection and
 392          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 393          */
 394         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 395         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 396
 397         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 398         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 399                 PERI_ACLK_HZ && (hclk_div < 0x4));
 400
 401         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 402         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 403                 PERI_ACLK_HZ && (pclk_div < 0x4));
 404
 405         rk_clrsetreg(&cru->cru_clksel_con[10],
 406                      PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
 407                      PERI_ACLK_DIV_MASK,
 408                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 409                      pclk_div << PERI_PCLK_DIV_SHIFT |
 410                      hclk_div << PERI_HCLK_DIV_SHIFT |
 411                      aclk_div << PERI_ACLK_DIV_SHIFT);
 412
 413         /* PLL enter normal-mode */
 414         rk_clrsetreg(&cru->cru_mode_con,
 415                      GPLL_MODE_MASK | CPLL_MODE_MASK,
 416                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 417                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 418 }
 419 #endif
 420
 421 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
 422 {
 423         /* pll enter slow-mode */
 424         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 425                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 426
 427         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
 428
 429         /* waiting for pll lock */
 430         while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
 431                 udelay(1);
 432
 433         /*
 434          * core clock pll source selection and
 435          * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
 436          * core clock select apll, apll clk = 1800MHz
 437          * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
 438          */
 439         rk_clrsetreg(&cru->cru_clksel_con[0],
 440                      CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
 441                      M0_DIV_MASK,
 442                      0 << A17_DIV_SHIFT |
 443                      3 << MP_DIV_SHIFT |
 444                      1 << M0_DIV_SHIFT);
 445
 446         /*
 447          * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
 448          * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
 449          */
 450         rk_clrsetreg(&cru->cru_clksel_con[37],
 451                      CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
 452                      PCLK_CORE_DBG_DIV_MASK,
 453                      1 << CLK_L2RAM_DIV_SHIFT |
 454                      3 << ATCLK_CORE_DIV_CON_SHIFT |
 455                      3 << PCLK_CORE_DBG_DIV_SHIFT);
 456
 457         /* PLL enter normal-mode */
 458         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 459                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 460 }
 461
 462 /* Get pll rate by id */
 463 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
 464                                    enum rk_clk_id clk_id)
 465 {
 466         uint32_t nr, no, nf;
 467         uint32_t con;
 468         int pll_id = rk_pll_id(clk_id);
 469         struct rk3288_pll *pll = &cru->pll[pll_id];
 470         static u8 clk_shift[CLK_COUNT] = {
 471                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 472                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
 473         };
 474         uint shift;
 475
 476         con = readl(&cru->cru_mode_con);
 477         shift = clk_shift[clk_id];
 478         switch ((con >> shift) & CRU_MODE_MASK) {
 479         case APLL_MODE_SLOW:
 480                 return OSC_HZ;
 481         case APLL_MODE_NORMAL:
 482                 /* normal mode */
 483                 con = readl(&pll->con0);
 484                 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
 485                 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
 486                 con = readl(&pll->con1);
 487                 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
 488
 489                 return (24 * nf / (nr * no)) * 1000000;
 490         case APLL_MODE_DEEP:
 491         default:
 492                 return 32768;
 493         }
 494 }
 495
 496 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 497                                   int periph)
 498 {
 499         uint src_rate;
 500         uint div, mux;
 501         u32 con;
 502
 503         switch (periph) {
 504         case HCLK_EMMC:
 505         case SCLK_EMMC:
 506                 con = readl(&cru->cru_clksel_con[12]);
 507                 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
 508                 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 509                 break;
 510         case HCLK_SDMMC:
 511         case SCLK_SDMMC:
 512                 con = readl(&cru->cru_clksel_con[11]);
 513                 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
 514                 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
 515                 break;
 516         case HCLK_SDIO0:
 517         case SCLK_SDIO0:
 518                 con = readl(&cru->cru_clksel_con[12]);
 519                 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
 520                 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
 521                 break;
 522         default:
 523                 return -EINVAL;
 524         }
 525
 526         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 527         return DIV_TO_RATE(src_rate, div);
 528 }
 529
 530 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 531                                   int  periph, uint freq)
 532 {
 533         int src_clk_div;
 534         int mux;
 535
 536         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 537         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 538
 539         if (src_clk_div > 0x3f) {
 540                 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
 541                 mux = EMMC_PLL_SELECT_24MHZ;
 542                 assert((int)EMMC_PLL_SELECT_24MHZ ==
 543                        (int)MMC0_PLL_SELECT_24MHZ);
 544         } else {
 545                 mux = EMMC_PLL_SELECT_GENERAL;
 546                 assert((int)EMMC_PLL_SELECT_GENERAL ==
 547                        (int)MMC0_PLL_SELECT_GENERAL);
 548         }
 549         switch (periph) {
 550         case HCLK_EMMC:
 551         case SCLK_EMMC:
 552                 rk_clrsetreg(&cru->cru_clksel_con[12],
 553                              EMMC_PLL_MASK | EMMC_DIV_MASK,
 554                              mux << EMMC_PLL_SHIFT |
 555                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 556                 break;
 557         case HCLK_SDMMC:
 558         case SCLK_SDMMC:
 559                 rk_clrsetreg(&cru->cru_clksel_con[11],
 560                              MMC0_PLL_MASK | MMC0_DIV_MASK,
 561                              mux << MMC0_PLL_SHIFT |
 562                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 563                 break;
 564         case HCLK_SDIO0:
 565         case SCLK_SDIO0:
 566                 rk_clrsetreg(&cru->cru_clksel_con[12],
 567                              SDIO0_PLL_MASK | SDIO0_DIV_MASK,
 568                              mux << SDIO0_PLL_SHIFT |
 569                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 570                 break;
 571         default:
 572                 return -EINVAL;
 573         }
 574
 575         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 576 }
 577
 578 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 579                                   int periph)
 580 {
 581         uint div, mux;
 582         u32 con;
 583
 584         switch (periph) {
 585         case SCLK_SPI0:
 586                 con = readl(&cru->cru_clksel_con[25]);
 587                 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
 588                 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
 589                 break;
 590         case SCLK_SPI1:
 591                 con = readl(&cru->cru_clksel_con[25]);
 592                 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
 593                 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
 594                 break;
 595         case SCLK_SPI2:
 596                 con = readl(&cru->cru_clksel_con[39]);
 597                 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
 598                 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
 599                 break;
 600         default:
 601                 return -EINVAL;
 602         }
 603         assert(mux == SPI0_PLL_SELECT_GENERAL);
 604
 605         return DIV_TO_RATE(gclk_rate, div);
 606 }
 607
 608 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 609                                   int periph, uint freq)
 610 {
 611         int src_clk_div;
 612
 613         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
 614         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 615         switch (periph) {
 616         case SCLK_SPI0:
 617                 rk_clrsetreg(&cru->cru_clksel_con[25],
 618                              SPI0_PLL_MASK | SPI0_DIV_MASK,
 619                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 620                              src_clk_div << SPI0_DIV_SHIFT);
 621                 break;
 622         case SCLK_SPI1:
 623                 rk_clrsetreg(&cru->cru_clksel_con[25],
 624                              SPI1_PLL_MASK | SPI1_DIV_MASK,
 625                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 626                              src_clk_div << SPI1_DIV_SHIFT);
 627                 break;
 628         case SCLK_SPI2:
 629                 rk_clrsetreg(&cru->cru_clksel_con[39],
 630                              SPI2_PLL_MASK | SPI2_DIV_MASK,
 631                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 632                              src_clk_div << SPI2_DIV_SHIFT);
 633                 break;
 634         default:
 635                 return -EINVAL;
 636         }
 637
 638         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 639 }
 640
 641 static ulong rk3288_clk_get_rate(struct clk *clk)
 642 {
 643         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 644         ulong new_rate, gclk_rate;
 645
 646         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 647         switch (clk->id) {
 648         case 0 ... 63:
 649                 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
 650                 break;
 651         case HCLK_EMMC:
 652         case HCLK_SDMMC:
 653         case HCLK_SDIO0:
 654         case SCLK_EMMC:
 655         case SCLK_SDMMC:
 656         case SCLK_SDIO0:
 657                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 658                 break;
 659         case SCLK_SPI0:
 660         case SCLK_SPI1:
 661         case SCLK_SPI2:
 662                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
 663                 break;
 664         case PCLK_I2C0:
 665         case PCLK_I2C1:
 666         case PCLK_I2C2:
 667         case PCLK_I2C3:
 668         case PCLK_I2C4:
 669         case PCLK_I2C5:
 670                 return gclk_rate;
 671         case PCLK_PWM:
 672                 return PD_BUS_PCLK_HZ;
 673         default:
 674                 return -ENOENT;
 675         }
 676
 677         return new_rate;
 678 }
 679
 680 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 681 {
 682         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 683         struct rk3288_cru *cru = priv->cru;
 684         ulong new_rate, gclk_rate;
 685
 686         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 687         switch (clk->id) {
 688         case PLL_APLL:
 689                 /* We only support a fixed rate here */
 690                 if (rate != 1800000000)
 691                         return -EINVAL;
 692                 rk3288_clk_configure_cpu(priv->cru, priv->grf);
 693                 new_rate = rate;
 694                 break;
 695         case CLK_DDR:
 696                 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
 697                 break;
 698         case HCLK_EMMC:
 699         case HCLK_SDMMC:
 700         case HCLK_SDIO0:
 701         case SCLK_EMMC:
 702         case SCLK_SDMMC:
 703         case SCLK_SDIO0:
 704                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
 705                 break;
 706         case SCLK_SPI0:
 707         case SCLK_SPI1:
 708         case SCLK_SPI2:
 709                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
 710                 break;
 711 #ifndef CONFIG_SPL_BUILD
 712         case SCLK_MAC:
 713                 new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
 714                 break;
 715         case DCLK_VOP0:
 716         case DCLK_VOP1:
 717                 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
 718                 break;
 719         case SCLK_EDP_24M:
 720                 /* clk_edp_24M source: 24M */
 721                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
 722
 723                 /* rst edp */
 724                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
 725                 udelay(1);
 726                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
 727                 new_rate = rate;
 728                 break;
 729         case ACLK_VOP0:
 730         case ACLK_VOP1: {
 731                 u32 div;
 732
 733                 /* vop aclk source clk: cpll */
 734                 div = CPLL_HZ / rate;
 735                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 736
 737                 switch (clk->id) {
 738                 case ACLK_VOP0:
 739                         rk_clrsetreg(&cru->cru_clksel_con[31],
 740                                      3 << 6 | 0x1f << 0,
 741                                      0 << 6 | (div - 1) << 0);
 742                         break;
 743                 case ACLK_VOP1:
 744                         rk_clrsetreg(&cru->cru_clksel_con[31],
 745                                      3 << 14 | 0x1f << 8,
 746                                      0 << 14 | (div - 1) << 8);
 747                         break;
 748                 }
 749                 new_rate = rate;
 750                 break;
 751         }
 752         case PCLK_HDMI_CTRL:
 753                 /* enable pclk hdmi ctrl */
 754                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
 755
 756                 /* software reset hdmi */
 757                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
 758                 udelay(1);
 759                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
 760                 new_rate = rate;
 761                 break;
 762 #endif
 763         default:
 764                 return -ENOENT;
 765         }
 766
 767         return new_rate;
 768 }
 769
 770 static struct clk_ops rk3288_clk_ops = {
 771         .get_rate       = rk3288_clk_get_rate,
 772         .set_rate       = rk3288_clk_set_rate,
 773 };
 774
 775 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
 776 {
 777 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 778         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 779
 780         priv->cru = (struct rk3288_cru *)devfdt_get_addr(dev);
 781 #endif
 782
 783         return 0;
 784 }
 785
 786 static int rk3288_clk_probe(struct udevice *dev)
 787 {
 788         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 789
 790         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 791         if (IS_ERR(priv->grf))
 792                 return PTR_ERR(priv->grf);
 793 #ifdef CONFIG_SPL_BUILD
 794 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 795         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 796
 797         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 798 #endif
 799         rkclk_init(priv->cru, priv->grf);
 800 #endif
 801
 802         return 0;
 803 }
 804
 805 static int rk3288_clk_bind(struct udevice *dev)
 806 {
 807         int ret;
 808
 809         /* The reset driver does not have a device node, so bind it here */
 810         ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
 811         if (ret)
 812                 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
 813
 814         return 0;
 815 }
 816
 817 static const struct udevice_id rk3288_clk_ids[] = {
 818         { .compatible = "rockchip,rk3288-cru" },
 819         { }
 820 };
 821
 822 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
 823         .name           = "rockchip_rk3288_cru",
 824         .id             = UCLASS_CLK,
 825         .of_match       = rk3288_clk_ids,
 826         .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
 827         .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
 828         .ops            = &rk3288_clk_ops,
 829         .bind           = rk3288_clk_bind,
 830         .ofdata_to_platdata     = rk3288_clk_ofdata_to_platdata,
 831         .probe          = rk3288_clk_probe,
 832 };