2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cru_rk3368.h>
18 #include <asm/arch/hardware.h>
21 #include <dt-bindings/clock/rk3368-cru.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #if CONFIG_IS_ENABLED(OF_PLATDATA)
26 struct rk3368_clk_plat {
27 struct dtd_rockchip_rk3368_cru dtd;
37 #define OSC_HZ (24 * 1000 * 1000)
38 #define APLL_L_HZ (800 * 1000 * 1000)
39 #define APLL_B_HZ (816 * 1000 * 1000)
40 #define GPLL_HZ (576 * 1000 * 1000)
41 #define CPLL_HZ (400 * 1000 * 1000)
43 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
45 #define PLL_DIVISORS(hz, _nr, _no) { \
46 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
47 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
48 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
49 "divisors on line " __stringify(__LINE__));
51 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
52 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
53 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
54 #if !defined(CONFIG_TPL_BUILD)
55 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
56 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
60 static ulong rk3368_clk_get_rate(struct clk *clk);
62 /* Get pll rate by id */
63 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
64 enum rk3368_pll_id pll_id)
68 struct rk3368_pll *pll = &cru->pll[pll_id];
70 con = readl(&pll->con3);
72 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
76 con = readl(&pll->con0);
77 no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
78 nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
79 con = readl(&pll->con1);
80 nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
82 return (24 * nf / (nr * no)) * 1000000;
83 case PLL_MODE_DEEP_SLOW:
89 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
90 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
91 const struct pll_div *div)
93 struct rk3368_pll *pll = &cru->pll[pll_id];
94 /* All PLLs have same VCO and output frequency range restrictions*/
95 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
96 uint output_hz = vco_hz / div->no;
98 debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
99 pll, div->nf, div->nr, div->no, vco_hz, output_hz);
101 /* enter slow mode and reset pll */
102 rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
103 PLL_RESET << PLL_RESET_SHIFT);
105 rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
106 ((div->nr - 1) << PLL_NR_SHIFT) |
107 ((div->no - 1) << PLL_OD_SHIFT));
108 writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
110 * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
111 * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
113 clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
117 /* return from reset */
118 rk_clrreg(&pll->con3, PLL_RESET_MASK);
120 /* waiting for pll lock */
121 while (!(readl(&pll->con1) & PLL_LOCK_STA))
124 rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
125 PLL_MODE_NORMAL << PLL_MODE_SHIFT);
131 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
132 static void rkclk_init(struct rk3368_cru *cru)
134 u32 apllb, aplll, dpll, cpll, gpll;
136 rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
137 rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
138 #if !defined(CONFIG_TPL_BUILD)
140 * If we plan to return to the boot ROM, we can't increase the
141 * GPLL rate from the SPL stage.
143 rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
144 rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
147 apllb = rkclk_pll_get_rate(cru, APLLB);
148 aplll = rkclk_pll_get_rate(cru, APLLL);
149 dpll = rkclk_pll_get_rate(cru, DPLL);
150 cpll = rkclk_pll_get_rate(cru, CPLL);
151 gpll = rkclk_pll_get_rate(cru, GPLL);
153 debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
154 __func__, apllb, aplll, dpll, cpll, gpll);
158 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
159 static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
161 u32 div, con, con_id, rate;
178 con = readl(&cru->clksel_con[con_id]);
179 switch (con & MMC_PLL_SEL_MASK) {
180 case MMC_PLL_SEL_GPLL:
181 pll_rate = rkclk_pll_get_rate(cru, GPLL);
183 case MMC_PLL_SEL_24M:
186 case MMC_PLL_SEL_CPLL:
187 pll_rate = rkclk_pll_get_rate(cru, CPLL);
189 case MMC_PLL_SEL_USBPHY_480M:
193 div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
194 rate = DIV_TO_RATE(pll_rate, div);
196 debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate);
200 static ulong rk3368_mmc_find_best_rate_and_parent(struct clk *clk,
207 const ulong MHz = 1000000;
212 { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ },
213 { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ },
214 { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz }
217 debug("%s: target rate %ld\n", __func__, rate);
218 for (i = 0; i < ARRAY_SIZE(parents); ++i) {
220 * Find the largest rate no larger than the target-rate for
221 * the current parent.
223 ulong parent_rate = parents[i].rate;
224 u32 div = DIV_ROUND_UP(parent_rate, rate);
226 ulong new_rate = parent_rate / adj_div;
228 debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
229 __func__, rate, parents[i].mux, parents[i].rate, div);
231 /* Skip, if not representable */
232 if ((div - 1) > MMC_CLK_DIV_MASK)
235 /* Skip, if we already have a better (or equal) solution */
236 if (new_rate <= best_rate)
239 /* This is our new best rate. */
240 best_rate = new_rate;
241 *best_mux = parents[i].mux;
245 debug("%s: best_mux = %x, best_div = %d, best_rate = %ld\n",
246 __func__, *best_mux, *best_div, best_rate);
251 static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
253 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
254 struct rk3368_cru *cru = priv->cru;
255 ulong clk_id = clk->id;
256 u32 con_id, mux = 0, div = 0;
258 /* Find the best parent and rate */
259 rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);
275 rk_clrsetreg(&cru->clksel_con[con_id],
276 MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
279 return rk3368_mmc_get_clk(cru, clk_id);
283 #if IS_ENABLED(CONFIG_TPL_BUILD)
284 static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
286 const struct pll_div *dpll_cfg = NULL;
287 const ulong MHz = 1000000;
289 /* Fout = ((Fin /NR) * NF )/ NO */
290 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
291 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1);
292 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2);
296 dpll_cfg = &dpll_1200;
299 dpll_cfg = &dpll_1332;
302 dpll_cfg = &dpll_1600;
305 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
307 rkclk_set_pll(cru, DPLL, dpll_cfg);
313 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
314 static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
319 * The gmac clock can be derived either from an external clock
320 * or can be generated from internally by a divider from SCLK_MAC.
322 if (readl(&cru->clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) {
323 /* An external clock will always generate the right rate... */
326 u32 con = readl(&cru->clksel_con[43]);
330 if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
331 GMAC_PLL_SELECT_GENERAL)
333 else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
334 GMAC_PLL_SELECT_CODEC)
337 /* CPLL is not set */
340 div = DIV_ROUND_UP(pll_rate, set_rate) - 1;
342 rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK,
343 div << GMAC_DIV_CON_SHIFT);
345 debug("Unsupported div for gmac:%d\n", div);
347 return DIV_TO_RATE(pll_rate, div);
355 * RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
356 * to select either CPLL or GPLL as the clock-parent. The location within
357 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
361 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
367 * The entries are numbered relative to their offset from SCLK_SPI0.
369 static const struct spi_clkreg spi_clkregs[] = {
370 [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
371 [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
372 [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
375 static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
377 return (val >> shift) & ((1 << width) - 1);
380 static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
382 const struct spi_clkreg *spiclk = NULL;
386 case SCLK_SPI0 ... SCLK_SPI2:
387 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
391 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
395 val = readl(&cru->clksel_con[spiclk->reg]);
396 div = extract_bits(val, 7, spiclk->div_shift);
398 debug("%s: div 0x%x\n", __func__, div);
399 return DIV_TO_RATE(GPLL_HZ, div);
402 static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)
404 const struct spi_clkreg *spiclk = NULL;
407 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
408 assert(src_clk_div < 127);
411 case SCLK_SPI0 ... SCLK_SPI2:
412 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
416 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
420 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
421 ((0x7f << spiclk->div_shift) |
422 (0x1 << spiclk->sel_shift)),
423 ((src_clk_div << spiclk->div_shift) |
424 (1 << spiclk->sel_shift)));
426 return rk3368_spi_get_clk(cru, clk_id);
429 static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)
433 val = readl(&cru->clksel_con[25]);
434 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
435 CLK_SARADC_DIV_CON_WIDTH);
437 return DIV_TO_RATE(OSC_HZ, div);
440 static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)
444 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
445 assert(src_clk_div < 128);
447 rk_clrsetreg(&cru->clksel_con[25],
448 CLK_SARADC_DIV_CON_MASK,
449 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
451 return rk3368_saradc_get_clk(cru);
454 static ulong rk3368_clk_get_rate(struct clk *clk)
456 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
459 debug("%s: id %ld\n", __func__, clk->id);
462 rate = rkclk_pll_get_rate(priv->cru, CPLL);
465 rate = rkclk_pll_get_rate(priv->cru, GPLL);
467 case SCLK_SPI0 ... SCLK_SPI2:
468 rate = rk3368_spi_get_clk(priv->cru, clk->id);
470 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
473 rate = rk3368_mmc_get_clk(priv->cru, clk->id);
477 rate = rk3368_saradc_get_clk(priv->cru);
486 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
488 __maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
491 debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
493 case SCLK_SPI0 ... SCLK_SPI2:
494 ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
496 #if IS_ENABLED(CONFIG_TPL_BUILD)
498 ret = rk3368_ddr_set_clk(priv->cru, rate);
501 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
504 ret = rk3368_mmc_set_clk(clk, rate);
507 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
509 /* select the external clock */
510 ret = rk3368_gmac_set_clk(priv->cru, rate);
514 ret = rk3368_saradc_set_clk(priv->cru, rate);
523 static int rk3368_gmac_set_parent(struct clk *clk, struct clk *parent)
525 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
526 struct rk3368_cru *cru = priv->cru;
527 const char *clock_output_name;
531 * If the requested parent is in the same clock-controller and
532 * the id is SCLK_MAC ("sclk_mac"), switch to the internal
535 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
536 debug("%s: switching GAMC to SCLK_MAC\n", __func__);
537 rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
542 * Otherwise, we need to check the clock-output-names of the
543 * requested parent to see if the requested id is "ext_gmac".
545 ret = dev_read_string_index(parent->dev, "clock-output-names",
546 parent->id, &clock_output_name);
550 /* If this is "ext_gmac", switch to the external clock input */
551 if (!strcmp(clock_output_name, "ext_gmac")) {
552 debug("%s: switching GMAC to external clock\n", __func__);
553 rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
560 static int rk3368_clk_set_parent(struct clk *clk, struct clk *parent)
564 return rk3368_gmac_set_parent(clk, parent);
567 debug("%s: unsupported clk %ld\n", __func__, clk->id);
571 static struct clk_ops rk3368_clk_ops = {
572 .get_rate = rk3368_clk_get_rate,
573 .set_rate = rk3368_clk_set_rate,
574 .set_parent = rk3368_clk_set_parent,
577 static int rk3368_clk_probe(struct udevice *dev)
579 struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
580 #if CONFIG_IS_ENABLED(OF_PLATDATA)
581 struct rk3368_clk_plat *plat = dev_get_platdata(dev);
583 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
585 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
586 rkclk_init(priv->cru);
592 static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
594 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
595 struct rk3368_clk_priv *priv = dev_get_priv(dev);
597 priv->cru = dev_read_addr_ptr(dev);
603 static int rk3368_clk_bind(struct udevice *dev)
606 struct udevice *sys_child;
607 struct sysreset_reg *priv;
609 /* The reset driver does not have a device node, so bind it here */
610 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
613 debug("Warning: No sysreset driver: ret=%d\n", ret);
615 priv = malloc(sizeof(struct sysreset_reg));
616 priv->glb_srst_fst_value = offsetof(struct rk3368_cru,
618 priv->glb_srst_snd_value = offsetof(struct rk3368_cru,
620 sys_child->priv = priv;
623 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
624 ret = offsetof(struct rk3368_cru, softrst_con[0]);
625 ret = rockchip_reset_bind(dev, ret, 15);
627 debug("Warning: software reset driver bind faile\n");
633 static const struct udevice_id rk3368_clk_ids[] = {
634 { .compatible = "rockchip,rk3368-cru" },
638 U_BOOT_DRIVER(rockchip_rk3368_cru) = {
639 .name = "rockchip_rk3368_cru",
641 .of_match = rk3368_clk_ids,
642 .priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
643 #if CONFIG_IS_ENABLED(OF_PLATDATA)
644 .platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
646 .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
647 .ops = &rk3368_clk_ops,
648 .bind = rk3368_clk_bind,
649 .probe = rk3368_clk_probe,