2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cru_rv1108.h>
15 #include <asm/arch/hardware.h>
17 #include <dt-bindings/clock/rv1108-cru.h>
19 DECLARE_GLOBAL_DATA_PTR;
22 VCO_MAX_HZ = 2400U * 1000000,
23 VCO_MIN_HZ = 600 * 1000000,
24 OUTPUT_MAX_HZ = 2400U * 1000000,
25 OUTPUT_MIN_HZ = 24 * 1000000,
28 #define RATE_TO_DIV(input_rate, output_rate) \
29 ((input_rate) / (output_rate) - 1);
31 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
33 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
35 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
36 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
37 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
38 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
39 #hz "Hz cannot be hit with PLL "\
40 "divisors on line " __stringify(__LINE__));
43 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
44 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
46 static inline int rv1108_pll_id(enum rk_clk_id clk_id)
59 printf("invalid pll id:%d\n", clk_id);
67 static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
68 enum rk_clk_id clk_id)
70 uint32_t refdiv, fbdiv, postdiv1, postdiv2;
71 uint32_t con0, con1, con3;
72 int pll_id = rv1108_pll_id(clk_id);
73 struct rv1108_pll *pll = &cru->pll[pll_id];
76 con3 = readl(&pll->con3);
78 if (con3 & WORK_MODE_MASK) {
79 con0 = readl(&pll->con0);
80 con1 = readl(&pll->con1);
81 fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK;
82 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT;
83 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT;
84 refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT;
85 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
93 static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate)
95 uint32_t con = readl(&cru->clksel_con[24]);
99 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL)
100 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
102 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM);
104 /*default set 50MHZ for gmac*/
108 div = DIV_ROUND_UP(pll_rate, rate) - 1;
110 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK,
111 div << MAC_CLK_DIV_SHIFT);
113 debug("Unsupported div for gmac:%d\n", div);
115 return DIV_TO_RATE(pll_rate, div);
118 static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)
120 u32 con = readl(&cru->clksel_con[27]);
124 if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL)
125 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
127 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR);
129 div = DIV_ROUND_UP(pll_rate, rate) - 1;
131 rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK,
132 div << SFC_CLK_DIV_SHIFT);
134 debug("Unsupported sfc clk rate:%d\n", rate);
136 return DIV_TO_RATE(pll_rate, div);
139 static ulong rv1108_clk_get_rate(struct clk *clk)
141 struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
145 return rkclk_pll_get_rate(priv->cru, clk->id);
151 static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
153 struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
158 new_rate = rv1108_mac_set_clk(priv->cru, rate);
161 new_rate = rv1108_sfc_set_clk(priv->cru, rate);
170 static const struct clk_ops rv1108_clk_ops = {
171 .get_rate = rv1108_clk_get_rate,
172 .set_rate = rv1108_clk_set_rate,
175 static void rkclk_init(struct rv1108_cru *cru)
177 unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM);
178 unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR);
179 unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
181 rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK,
182 0 << MAC_CLK_DIV_SHIFT);
184 printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
187 static int rv1108_clk_probe(struct udevice *dev)
189 struct rv1108_clk_priv *priv = dev_get_priv(dev);
191 priv->cru = (struct rv1108_cru *)devfdt_get_addr(dev);
193 rkclk_init(priv->cru);
198 static int rv1108_clk_bind(struct udevice *dev)
202 /* The reset driver does not have a device node, so bind it here */
203 ret = device_bind_driver(gd->dm_root, "rv1108_sysreset", "reset", &dev);
205 error("No Rv1108 reset driver: ret=%d\n", ret);
210 static const struct udevice_id rv1108_clk_ids[] = {
211 { .compatible = "rockchip,rv1108-cru" },
215 U_BOOT_DRIVER(clk_rv1108) = {
216 .name = "clk_rv1108",
218 .of_match = rv1108_clk_ids,
219 .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
220 .ops = &rv1108_clk_ops,
221 .bind = rv1108_clk_bind,
222 .probe = rv1108_clk_probe,