2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 * Based on CAAM driver in drivers/crypto/caam in Linux
14 #include "desc_constr.h"
15 #ifdef CONFIG_FSL_CORENET
16 #include <asm/fsl_pamu.h>
19 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
20 #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
24 static inline void start_jr0(void)
26 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
27 u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
28 u32 scfgr = sec_in32(&sec->scfgr);
30 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
31 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
32 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
34 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
35 (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
36 (scfgr & SEC_SCFGR_VIRT_EN)))
37 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
39 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
40 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
41 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
45 static inline void jr_reset_liodn(void)
47 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
48 sec_out32(&sec->jrliodnr[0].ls, 0);
51 static inline void jr_disable_irq(void)
53 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
54 uint32_t jrcfg = sec_in32(®s->jrcfg1);
56 jrcfg = jrcfg | JR_INTMASK;
58 sec_out32(®s->jrcfg1, jrcfg);
61 static void jr_initregs(void)
63 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
64 phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring);
65 phys_addr_t op_base = virt_to_phys((void *)jr.output_ring);
67 #ifdef CONFIG_PHYS_64BIT
68 sec_out32(®s->irba_h, ip_base >> 32);
70 sec_out32(®s->irba_h, 0x0);
72 sec_out32(®s->irba_l, (uint32_t)ip_base);
73 #ifdef CONFIG_PHYS_64BIT
74 sec_out32(®s->orba_h, op_base >> 32);
76 sec_out32(®s->orba_h, 0x0);
78 sec_out32(®s->orba_l, (uint32_t)op_base);
79 sec_out32(®s->ors, JR_SIZE);
80 sec_out32(®s->irs, JR_SIZE);
86 static int jr_init(void)
88 memset(&jr, 0, sizeof(struct jobring));
90 jr.jq_id = DEFAULT_JR_ID;
93 #ifdef CONFIG_FSL_CORENET
94 jr.liodn = DEFAULT_JR_LIODN;
97 jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
98 JR_SIZE * sizeof(dma_addr_t));
102 jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring),
105 (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size);
109 memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
110 memset(jr.output_ring, 0, jr.op_size);
119 static int jr_sw_cleanup(void)
125 memset(jr.info, 0, sizeof(jr.info));
126 memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
127 memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
132 static int jr_hw_reset(void)
134 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
135 uint32_t timeout = 100000;
136 uint32_t jrint, jrcr;
138 sec_out32(®s->jrcr, JRCR_RESET);
140 jrint = sec_in32(®s->jrint);
141 } while (((jrint & JRINT_ERR_HALT_MASK) ==
142 JRINT_ERR_HALT_INPROGRESS) && --timeout);
144 jrint = sec_in32(®s->jrint);
145 if (((jrint & JRINT_ERR_HALT_MASK) !=
146 JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
150 sec_out32(®s->jrcr, JRCR_RESET);
152 jrcr = sec_in32(®s->jrcr);
153 } while ((jrcr & JRCR_RESET) && --timeout);
161 /* -1 --- error, can't enqueue -- no space available */
162 static int jr_enqueue(uint32_t *desc_addr,
163 void (*callback)(uint32_t status, void *arg),
166 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
169 int length = desc_len(desc_addr);
171 #ifdef CONFIG_PHYS_64BIT
172 uint32_t *addr_hi, *addr_lo;
175 /* The descriptor must be submitted to SEC block as per endianness
177 * So, if the endianness of Core and SEC block is different, each word
178 * of the descriptor will be byte-swapped.
180 for (i = 0; i < length; i++) {
181 desc_word = desc_addr[i];
182 sec_out32((uint32_t *)&desc_addr[i], desc_word);
185 phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
187 if (sec_in32(®s->irsa) == 0 ||
188 CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
191 jr.info[head].desc_phys_addr = desc_phys_addr;
192 jr.info[head].callback = (void *)callback;
193 jr.info[head].arg = arg;
194 jr.info[head].op_done = 0;
196 unsigned long start = (unsigned long)&jr.info[head] &
197 ~(ARCH_DMA_MINALIGN - 1);
198 unsigned long end = ALIGN((unsigned long)&jr.info[head] +
199 sizeof(struct jr_info), ARCH_DMA_MINALIGN);
200 flush_dcache_range(start, end);
202 #ifdef CONFIG_PHYS_64BIT
203 /* Write the 64 bit Descriptor address on Input Ring.
204 * The 32 bit hign and low part of the address will
205 * depend on endianness of SEC block.
207 #ifdef CONFIG_SYS_FSL_SEC_LE
208 addr_lo = (uint32_t *)(&jr.input_ring[head]);
209 addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1;
210 #elif defined(CONFIG_SYS_FSL_SEC_BE)
211 addr_hi = (uint32_t *)(&jr.input_ring[head]);
212 addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1;
213 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
215 sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
216 sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
219 /* Write the 32 bit Descriptor address on Input Ring. */
220 sec_out32(&jr.input_ring[head], desc_phys_addr);
221 #endif /* ifdef CONFIG_PHYS_64BIT */
223 start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
224 end = ALIGN((unsigned long)&jr.input_ring[head] +
225 sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
226 flush_dcache_range(start, end);
228 jr.head = (head + 1) & (jr.size - 1);
230 /* Invalidate output ring */
231 start = (unsigned long)jr.output_ring &
232 ~(ARCH_DMA_MINALIGN - 1);
233 end = ALIGN((unsigned long)jr.output_ring + jr.op_size,
235 invalidate_dcache_range(start, end);
237 sec_out32(®s->irja, 1);
242 static int jr_dequeue(void)
244 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
248 void (*callback)(uint32_t status, void *arg);
250 #ifdef CONFIG_PHYS_64BIT
251 uint32_t *addr_hi, *addr_lo;
256 while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
261 #ifdef CONFIG_PHYS_64BIT
262 /* Read the 64 bit Descriptor address from Output Ring.
263 * The 32 bit hign and low part of the address will
264 * depend on endianness of SEC block.
266 #ifdef CONFIG_SYS_FSL_SEC_LE
267 addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc);
268 addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
269 #elif defined(CONFIG_SYS_FSL_SEC_BE)
270 addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc);
271 addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
272 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
274 op_desc = ((u64)sec_in32(addr_hi) << 32) |
275 ((u64)sec_in32(addr_lo));
278 /* Read the 32 bit Descriptor address from Output Ring. */
279 addr = (uint32_t *)&jr.output_ring[jr.tail].desc;
280 op_desc = sec_in32(addr);
281 #endif /* ifdef CONFIG_PHYS_64BIT */
283 uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
285 for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
286 idx = (tail + i) & (jr.size - 1);
287 if (op_desc == jr.info[idx].desc_phys_addr) {
293 /* Error condition if match not found */
297 jr.info[idx].op_done = 1;
298 callback = (void *)jr.info[idx].callback;
299 arg = jr.info[idx].arg;
301 /* When the job on tail idx gets done, increment
302 * tail till the point where job completed out of oredr has
303 * been taken into account
307 tail = (tail + 1) & (jr.size - 1);
308 } while (jr.info[tail].op_done);
311 jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
313 sec_out32(®s->orjr, 1);
314 jr.info[idx].op_done = 0;
316 callback(status, arg);
322 static void desc_done(uint32_t status, void *arg)
324 struct result *x = arg;
326 caam_jr_strstatus(status);
330 int run_descriptor_jr(uint32_t *desc)
332 unsigned long long timeval = get_ticks();
333 unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
337 memset(&op, 0, sizeof(op));
339 ret = jr_enqueue(desc, desc_done, &op);
341 debug("Error in SEC enq\n");
346 timeval = get_ticks();
347 timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
348 while (op.done != 1) {
351 debug("Error in SEC deq\n");
356 if ((get_ticks() - timeval) > timeout) {
357 debug("SEC Dequeue timed out\n");
364 debug("Error %x\n", op.status);
373 if (jr_hw_reset() < 0)
376 /* Clean up the jobring structure maintained by software */
384 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
385 uint32_t mcfgr = sec_in32(&sec->mcfgr);
386 uint32_t timeout = 100000;
388 mcfgr |= MCFGR_SWRST;
389 sec_out32(&sec->mcfgr, mcfgr);
391 mcfgr |= MCFGR_DMA_RST;
392 sec_out32(&sec->mcfgr, mcfgr);
394 mcfgr = sec_in32(&sec->mcfgr);
395 } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
402 mcfgr = sec_in32(&sec->mcfgr);
403 } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
411 static int instantiate_rng(void)
417 ccsr_sec_t __iomem *sec =
418 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
419 struct rng4tst __iomem *rng =
420 (struct rng4tst __iomem *)&sec->rng;
422 memset(&op, 0, sizeof(struct result));
424 desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
426 printf("cannot allocate RNG init descriptor memory\n");
430 inline_cnstr_jobdesc_rng_instantiation(desc);
431 int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
432 flush_dcache_range((unsigned long)desc,
433 (unsigned long)desc + size);
435 ret = run_descriptor_jr(desc);
438 printf("RNG: Instantiation failed with error %x\n", ret);
440 rdsta_val = sec_in32(&rng->rdsta);
441 if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
447 static u8 get_rng_vid(void)
449 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
450 u32 cha_vid = sec_in32(&sec->chavid_ls);
452 return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
456 * By default, the TRNG runs for 200 clocks per sample;
457 * 1200 clocks per sample generates better entropy.
459 static void kick_trng(int ent_delay)
461 ccsr_sec_t __iomem *sec =
462 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
463 struct rng4tst __iomem *rng =
464 (struct rng4tst __iomem *)&sec->rng;
467 /* put RNG4 into program mode */
468 sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
469 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
470 * length (in system clocks) of each Entropy sample taken
472 val = sec_in32(&rng->rtsdctl);
473 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
474 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
475 sec_out32(&rng->rtsdctl, val);
476 /* min. freq. count, equal to 1/4 of the entropy sample length */
477 sec_out32(&rng->rtfreqmin, ent_delay >> 2);
478 /* disable maximum frequency count */
479 sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
481 * select raw sampling in both entropy shifter
482 * and statistical checker
484 sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
485 /* put RNG4 into run mode */
486 sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
489 static int rng_init(void)
491 int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
492 ccsr_sec_t __iomem *sec =
493 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
494 struct rng4tst __iomem *rng =
495 (struct rng4tst __iomem *)&sec->rng;
497 u32 rdsta = sec_in32(&rng->rdsta);
499 /* Check if RNG state 0 handler is already instantiated */
500 if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
505 * If either of the SH's were instantiated by somebody else
506 * then it is assumed that the entropy
507 * parameters are properly set and thus the function
508 * setting these (kick_trng(...)) is skipped.
509 * Also, if a handle was instantiated, do not change
510 * the TRNG parameters.
512 kick_trng(ent_delay);
515 * if instantiate_rng(...) fails, the loop will rerun
516 * and the kick_trng(...) function will modfiy the
517 * upper and lower limits of the entropy sampling
518 * interval, leading to a sucessful initialization of
521 ret = instantiate_rng();
522 } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
524 printf("RNG: Failed to instantiate RNG\n");
528 /* Enable RDB bit so that RNG works faster */
529 sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
536 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
537 uint32_t mcr = sec_in32(&sec->mcfgr);
540 #ifdef CONFIG_FSL_CORENET
547 * Modifying CAAM Read/Write Attributes
549 * For AXI Write - Cacheable, Write Back, Write allocate
550 * For AXI Read - Cacheable, Read allocate
551 * Only For LS2080a, to solve CAAM coherency issues
553 #ifdef CONFIG_LS2080A
554 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
555 mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
557 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
560 #ifdef CONFIG_PHYS_64BIT
561 mcr |= (1 << MCFGR_PS_SHIFT);
563 sec_out32(&sec->mcfgr, mcr);
565 #ifdef CONFIG_FSL_CORENET
566 liodnr = sec_in32(&sec->jrliodnr[0].ls);
567 liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
568 liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
573 printf("SEC initialization failed\n");
577 #ifdef CONFIG_FSL_CORENET
578 ret = sec_config_pamu_table(liodn_ns, liodn_s);
585 if (get_rng_vid() >= 4) {
586 if (rng_init() < 0) {
587 printf("RNG instantiation failed\n");
590 printf("SEC: RNG instantiated\n");