2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 * Based on CAAM driver in drivers/crypto/caam in Linux
14 #include "desc_constr.h"
16 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
17 #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
21 static inline void start_jr0(void)
23 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
24 u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
25 u32 scfgr = sec_in32(&sec->scfgr);
27 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
28 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
29 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
31 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
32 (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
33 (scfgr & SEC_SCFGR_VIRT_EN)))
34 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
36 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
37 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
38 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
42 static inline void jr_reset_liodn(void)
44 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
45 sec_out32(&sec->jrliodnr[0].ls, 0);
48 static inline void jr_disable_irq(void)
50 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
51 uint32_t jrcfg = sec_in32(®s->jrcfg1);
53 jrcfg = jrcfg | JR_INTMASK;
55 sec_out32(®s->jrcfg1, jrcfg);
58 static void jr_initregs(void)
60 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
61 phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring);
62 phys_addr_t op_base = virt_to_phys((void *)jr.output_ring);
64 #ifdef CONFIG_PHYS_64BIT
65 sec_out32(®s->irba_h, ip_base >> 32);
67 sec_out32(®s->irba_h, 0x0);
69 sec_out32(®s->irba_l, (uint32_t)ip_base);
70 #ifdef CONFIG_PHYS_64BIT
71 sec_out32(®s->orba_h, op_base >> 32);
73 sec_out32(®s->orba_h, 0x0);
75 sec_out32(®s->orba_l, (uint32_t)op_base);
76 sec_out32(®s->ors, JR_SIZE);
77 sec_out32(®s->irs, JR_SIZE);
83 static int jr_init(void)
85 memset(&jr, 0, sizeof(struct jobring));
87 jr.jq_id = DEFAULT_JR_ID;
90 #ifdef CONFIG_FSL_CORENET
91 jr.liodn = DEFAULT_JR_LIODN;
94 jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
95 JR_SIZE * sizeof(dma_addr_t));
99 jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring),
102 (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size);
106 memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
107 memset(jr.output_ring, 0, jr.op_size);
116 static int jr_sw_cleanup(void)
122 memset(jr.info, 0, sizeof(jr.info));
123 memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
124 memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
129 static int jr_hw_reset(void)
131 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
132 uint32_t timeout = 100000;
133 uint32_t jrint, jrcr;
135 sec_out32(®s->jrcr, JRCR_RESET);
137 jrint = sec_in32(®s->jrint);
138 } while (((jrint & JRINT_ERR_HALT_MASK) ==
139 JRINT_ERR_HALT_INPROGRESS) && --timeout);
141 jrint = sec_in32(®s->jrint);
142 if (((jrint & JRINT_ERR_HALT_MASK) !=
143 JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
147 sec_out32(®s->jrcr, JRCR_RESET);
149 jrcr = sec_in32(®s->jrcr);
150 } while ((jrcr & JRCR_RESET) && --timeout);
158 /* -1 --- error, can't enqueue -- no space available */
159 static int jr_enqueue(uint32_t *desc_addr,
160 void (*callback)(uint32_t status, void *arg),
163 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
166 int length = desc_len(desc_addr);
168 #ifdef CONFIG_PHYS_64BIT
169 uint32_t *addr_hi, *addr_lo;
172 /* The descriptor must be submitted to SEC block as per endianness
174 * So, if the endianness of Core and SEC block is different, each word
175 * of the descriptor will be byte-swapped.
177 for (i = 0; i < length; i++) {
178 desc_word = desc_addr[i];
179 sec_out32((uint32_t *)&desc_addr[i], desc_word);
182 phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
184 if (sec_in32(®s->irsa) == 0 ||
185 CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
188 jr.info[head].desc_phys_addr = desc_phys_addr;
189 jr.info[head].callback = (void *)callback;
190 jr.info[head].arg = arg;
191 jr.info[head].op_done = 0;
193 unsigned long start = (unsigned long)&jr.info[head] &
194 ~(ARCH_DMA_MINALIGN - 1);
195 unsigned long end = ALIGN((unsigned long)&jr.info[head] +
196 sizeof(struct jr_info), ARCH_DMA_MINALIGN);
197 flush_dcache_range(start, end);
199 #ifdef CONFIG_PHYS_64BIT
200 /* Write the 64 bit Descriptor address on Input Ring.
201 * The 32 bit hign and low part of the address will
202 * depend on endianness of SEC block.
204 #ifdef CONFIG_SYS_FSL_SEC_LE
205 addr_lo = (uint32_t *)(&jr.input_ring[head]);
206 addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1;
207 #elif defined(CONFIG_SYS_FSL_SEC_BE)
208 addr_hi = (uint32_t *)(&jr.input_ring[head]);
209 addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1;
210 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
212 sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
213 sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
216 /* Write the 32 bit Descriptor address on Input Ring. */
217 sec_out32(&jr.input_ring[head], desc_phys_addr);
218 #endif /* ifdef CONFIG_PHYS_64BIT */
220 start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
221 end = ALIGN((unsigned long)&jr.input_ring[head] +
222 sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
223 flush_dcache_range(start, end);
225 jr.head = (head + 1) & (jr.size - 1);
227 /* Invalidate output ring */
228 start = (unsigned long)jr.output_ring &
229 ~(ARCH_DMA_MINALIGN - 1);
230 end = ALIGN((unsigned long)jr.output_ring + jr.op_size,
232 invalidate_dcache_range(start, end);
234 sec_out32(®s->irja, 1);
239 static int jr_dequeue(void)
241 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
245 void (*callback)(uint32_t status, void *arg);
247 #ifdef CONFIG_PHYS_64BIT
248 uint32_t *addr_hi, *addr_lo;
253 while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
258 #ifdef CONFIG_PHYS_64BIT
259 /* Read the 64 bit Descriptor address from Output Ring.
260 * The 32 bit hign and low part of the address will
261 * depend on endianness of SEC block.
263 #ifdef CONFIG_SYS_FSL_SEC_LE
264 addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc);
265 addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
266 #elif defined(CONFIG_SYS_FSL_SEC_BE)
267 addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc);
268 addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
269 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
271 op_desc = ((u64)sec_in32(addr_hi) << 32) |
272 ((u64)sec_in32(addr_lo));
275 /* Read the 32 bit Descriptor address from Output Ring. */
276 addr = (uint32_t *)&jr.output_ring[jr.tail].desc;
277 op_desc = sec_in32(addr);
278 #endif /* ifdef CONFIG_PHYS_64BIT */
280 uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
282 for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
283 idx = (tail + i) & (jr.size - 1);
284 if (op_desc == jr.info[idx].desc_phys_addr) {
290 /* Error condition if match not found */
294 jr.info[idx].op_done = 1;
295 callback = (void *)jr.info[idx].callback;
296 arg = jr.info[idx].arg;
298 /* When the job on tail idx gets done, increment
299 * tail till the point where job completed out of oredr has
300 * been taken into account
304 tail = (tail + 1) & (jr.size - 1);
305 } while (jr.info[tail].op_done);
308 jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
310 sec_out32(®s->orjr, 1);
311 jr.info[idx].op_done = 0;
313 callback(status, arg);
319 static void desc_done(uint32_t status, void *arg)
321 struct result *x = arg;
323 caam_jr_strstatus(status);
327 int run_descriptor_jr(uint32_t *desc)
329 unsigned long long timeval = get_ticks();
330 unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
334 memset(&op, 0, sizeof(op));
336 ret = jr_enqueue(desc, desc_done, &op);
338 debug("Error in SEC enq\n");
343 timeval = get_ticks();
344 timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
345 while (op.done != 1) {
348 debug("Error in SEC deq\n");
353 if ((get_ticks() - timeval) > timeout) {
354 debug("SEC Dequeue timed out\n");
361 debug("Error %x\n", op.status);
370 if (jr_hw_reset() < 0)
373 /* Clean up the jobring structure maintained by software */
381 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
382 uint32_t mcfgr = sec_in32(&sec->mcfgr);
383 uint32_t timeout = 100000;
385 mcfgr |= MCFGR_SWRST;
386 sec_out32(&sec->mcfgr, mcfgr);
388 mcfgr |= MCFGR_DMA_RST;
389 sec_out32(&sec->mcfgr, mcfgr);
391 mcfgr = sec_in32(&sec->mcfgr);
392 } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
399 mcfgr = sec_in32(&sec->mcfgr);
400 } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
408 static int instantiate_rng(void)
414 ccsr_sec_t __iomem *sec =
415 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
416 struct rng4tst __iomem *rng =
417 (struct rng4tst __iomem *)&sec->rng;
419 memset(&op, 0, sizeof(struct result));
421 desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
423 printf("cannot allocate RNG init descriptor memory\n");
427 inline_cnstr_jobdesc_rng_instantiation(desc);
428 int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
429 flush_dcache_range((unsigned long)desc,
430 (unsigned long)desc + size);
432 ret = run_descriptor_jr(desc);
435 printf("RNG: Instantiation failed with error %x\n", ret);
437 rdsta_val = sec_in32(&rng->rdsta);
438 if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
444 static u8 get_rng_vid(void)
446 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
447 u32 cha_vid = sec_in32(&sec->chavid_ls);
449 return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
453 * By default, the TRNG runs for 200 clocks per sample;
454 * 1200 clocks per sample generates better entropy.
456 static void kick_trng(int ent_delay)
458 ccsr_sec_t __iomem *sec =
459 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
460 struct rng4tst __iomem *rng =
461 (struct rng4tst __iomem *)&sec->rng;
464 /* put RNG4 into program mode */
465 sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
466 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
467 * length (in system clocks) of each Entropy sample taken
469 val = sec_in32(&rng->rtsdctl);
470 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
471 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
472 sec_out32(&rng->rtsdctl, val);
473 /* min. freq. count, equal to 1/4 of the entropy sample length */
474 sec_out32(&rng->rtfreqmin, ent_delay >> 2);
475 /* disable maximum frequency count */
476 sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
478 * select raw sampling in both entropy shifter
479 * and statistical checker
481 sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
482 /* put RNG4 into run mode */
483 sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
486 static int rng_init(void)
488 int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
489 ccsr_sec_t __iomem *sec =
490 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
491 struct rng4tst __iomem *rng =
492 (struct rng4tst __iomem *)&sec->rng;
494 u32 rdsta = sec_in32(&rng->rdsta);
496 /* Check if RNG state 0 handler is already instantiated */
497 if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
502 * If either of the SH's were instantiated by somebody else
503 * then it is assumed that the entropy
504 * parameters are properly set and thus the function
505 * setting these (kick_trng(...)) is skipped.
506 * Also, if a handle was instantiated, do not change
507 * the TRNG parameters.
509 kick_trng(ent_delay);
512 * if instantiate_rng(...) fails, the loop will rerun
513 * and the kick_trng(...) function will modfiy the
514 * upper and lower limits of the entropy sampling
515 * interval, leading to a sucessful initialization of
518 ret = instantiate_rng();
519 } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
521 printf("RNG: Failed to instantiate RNG\n");
525 /* Enable RDB bit so that RNG works faster */
526 sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
533 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
534 uint32_t mcr = sec_in32(&sec->mcfgr);
537 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
538 #ifdef CONFIG_PHYS_64BIT
539 mcr |= (1 << MCFGR_PS_SHIFT);
541 sec_out32(&sec->mcfgr, mcr);
545 printf("SEC initialization failed\n");
549 if (get_rng_vid() >= 4) {
550 if (rng_init() < 0) {
551 printf("RNG instantiation failed\n");
554 printf("SEC: RNG instantiated\n");