2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
12 #include "sequencer_auto.h"
13 #include "sequencer_auto_ac_init.h"
14 #include "sequencer_auto_inst_init.h"
15 #include "sequencer_defines.h"
17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
18 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
21 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
23 static struct socfpga_sdr_reg_file *sdr_reg_file =
24 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
27 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
30 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
33 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
35 static struct socfpga_data_mgr *data_mgr =
36 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
38 static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
56 #define STATIC_IN_RTL_SIM 0
57 #define STATIC_SKIP_DELAY_LOOPS 0
59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
62 /* calibration steps requested by the rtl */
63 uint16_t dyn_calib_steps;
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
70 * The mask is set to include all bits when not-skipping, but is
74 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
80 struct param_type *param;
81 uint32_t curr_shadow_reg;
83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
84 uint32_t write_group, uint32_t use_dm,
85 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
91 * Only set the global stage if there was not been any other
94 if (gbl->error_stage == CAL_STAGE_NIL) {
95 gbl->error_substage = substage;
96 gbl->error_stage = stage;
97 gbl->error_group = group;
101 static void reg_file_set_group(u16 set_group)
103 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
106 static void reg_file_set_stage(u8 set_stage)
108 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
111 static void reg_file_set_sub_stage(u8 set_sub_stage)
113 set_sub_stage &= 0xff;
114 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
118 * phy_mgr_initialize() - Initialize PHY Manager
120 * Initialize PHY Manager.
122 static void phy_mgr_initialize(void)
126 debug("%s:%d\n", __func__, __LINE__);
127 /* Calibration has control over path to memory */
129 * In Hard PHY this is a 2-bit control:
133 writel(0x3, &phy_mgr_cfg->mux_sel);
135 /* USER memory clock is not stable we begin initialization */
136 writel(0, &phy_mgr_cfg->reset_mem_stbl);
138 /* USER calibration status all set to zero */
139 writel(0, &phy_mgr_cfg->cal_status);
141 writel(0, &phy_mgr_cfg->cal_debug_info);
143 /* Init params only if we do NOT skip calibration. */
144 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
147 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
148 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
149 param->read_correct_mask_vg = (1 << ratio) - 1;
150 param->write_correct_mask_vg = (1 << ratio) - 1;
151 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
152 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
153 ratio = RW_MGR_MEM_DATA_WIDTH /
154 RW_MGR_MEM_DATA_MASK_WIDTH;
155 param->dm_correct_mask = (1 << ratio) - 1;
159 * set_rank_and_odt_mask() - Set Rank and ODT mask
161 * @odt_mode: ODT mode, OFF or READ_WRITE
163 * Set Rank and ODT mask (On-Die Termination).
165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
171 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
174 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
175 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
177 /* Read: ODT = 0 ; Write: ODT = 1 */
181 case 2: /* 2 Ranks */
182 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
184 * - Dual-Slot , Single-Rank (1 CS per DIMM)
186 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
188 * Since MEM_NUMBER_OF_RANKS is 2, they
189 * are both single rank with 2 CS each
190 * (special for RDIMM).
192 * Read: Turn on ODT on the opposite rank
193 * Write: Turn on ODT on all ranks
195 odt_mask_0 = 0x3 & ~(1 << rank);
199 * - Single-Slot , Dual-Rank (2 CS per DIMM)
201 * Read: Turn on ODT off on all ranks
202 * Write: Turn on ODT on active rank
205 odt_mask_1 = 0x3 & (1 << rank);
208 case 4: /* 4 Ranks */
210 * ----------+-----------------------+
212 * Read From +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 0 |
216 * 1 | 1 | 0 | 0 | 0 |
217 * 2 | 0 | 0 | 0 | 1 |
218 * 3 | 0 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
222 * ----------+-----------------------+
224 * Write To +-----------------------+
225 * Rank | 3 | 2 | 1 | 0 |
226 * ----------+-----+-----+-----+-----+
227 * 0 | 0 | 1 | 0 | 1 |
228 * 1 | 1 | 0 | 1 | 0 |
229 * 2 | 0 | 1 | 0 | 1 |
230 * 3 | 1 | 0 | 1 | 0 |
231 * ----------+-----+-----+-----+-----+
255 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
256 ((0xFF & odt_mask_0) << 8) |
257 ((0xFF & odt_mask_1) << 16);
258 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
259 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
263 * scc_mgr_set() - Set SCC Manager register
264 * @off: Base offset in SCC Manager space
265 * @grp: Read/Write group
266 * @val: Value to be set
268 * This function sets the SCC Manager (Scan Chain Control Manager) register.
270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
272 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
276 * scc_mgr_initialize() - Initialize SCC Manager registers
278 * Initialize SCC Manager registers.
280 static void scc_mgr_initialize(void)
283 * Clear register file for HPS. 16 (2^4) is the size of the
284 * full register file in the scc mgr:
285 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
286 * MEM_IF_READ_DQS_WIDTH - 1);
290 for (i = 0; i < 16; i++) {
291 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
292 __func__, __LINE__, i);
293 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
299 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
304 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
309 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
314 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
319 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
325 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
335 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
341 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
342 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
346 /* load up dqs config settings */
347 static void scc_mgr_load_dqs(uint32_t dqs)
349 writel(dqs, &sdr_scc_mgr->dqs_ena);
352 /* load up dqs io config settings */
353 static void scc_mgr_load_dqs_io(void)
355 writel(0, &sdr_scc_mgr->dqs_io_ena);
358 /* load up dq config settings */
359 static void scc_mgr_load_dq(uint32_t dq_in_group)
361 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
364 /* load up dm config settings */
365 static void scc_mgr_load_dm(uint32_t dm)
367 writel(dm, &sdr_scc_mgr->dm_ena);
371 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
372 * @off: Base offset in SCC Manager space
373 * @grp: Read/Write group
374 * @val: Value to be set
375 * @update: If non-zero, trigger SCC Manager update for all ranks
377 * This function sets the SCC Manager (Scan Chain Control Manager) register
378 * and optionally triggers the SCC update for all ranks.
380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
385 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
386 r += NUM_RANKS_PER_SHADOW_REG) {
387 scc_mgr_set(off, grp, val);
389 if (update || (r == 0)) {
390 writel(grp, &sdr_scc_mgr->dqs_ena);
391 writel(0, &sdr_scc_mgr->update);
396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
399 * USER although the h/w doesn't support different phases per
400 * shadow register, for simplicity our scc manager modeling
401 * keeps different phase settings per shadow reg, and it's
402 * important for us to keep them in sync to match h/w.
403 * for efficiency, the scan chain update should occur only
406 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
407 read_group, phase, 0);
410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
414 * USER although the h/w doesn't support different phases per
415 * shadow register, for simplicity our scc manager modeling
416 * keeps different phase settings per shadow reg, and it's
417 * important for us to keep them in sync to match h/w.
418 * for efficiency, the scan chain update should occur only
421 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
422 write_group, phase, 0);
425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
429 * In shadow register mode, the T11 settings are stored in
430 * registers in the core, which are updated by the DQS_ENA
431 * signals. Not issuing the SCC_MGR_UPD command allows us to
432 * save lots of rank switching overhead, by calling
433 * select_shadow_regs_for_update with update_scan_chains
436 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
437 read_group, delay, 1);
438 writel(0, &sdr_scc_mgr->update);
442 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
443 * @write_group: Write group
444 * @delay: Delay value
446 * This function sets the OCT output delay in SCC manager.
448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
450 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
451 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
452 const int base = write_group * ratio;
455 * Load the setting in the SCC manager
456 * Although OCT affects only write data, the OCT delay is controlled
457 * by the DQS logic block which is instantiated once per read group.
458 * For protocols where a write group consists of multiple read groups,
459 * the setting must be set multiple times.
461 for (i = 0; i < ratio; i++)
462 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
466 * scc_mgr_set_hhp_extras() - Set HHP extras.
468 * Load the fixed setting in the SCC manager HHP extras.
470 static void scc_mgr_set_hhp_extras(void)
473 * Load the fixed setting in the SCC manager
474 * bits: 0:0 = 1'b1 - DQS bypass
475 * bits: 1:1 = 1'b1 - DQ bypass
476 * bits: 4:2 = 3'b001 - rfifo_mode
477 * bits: 6:5 = 2'b01 - rfifo clock_select
478 * bits: 7:7 = 1'b0 - separate gating from ungating setting
479 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
481 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
482 (1 << 2) | (1 << 1) | (1 << 0);
483 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
484 SCC_MGR_HHP_GLOBALS_OFFSET |
485 SCC_MGR_HHP_EXTRAS_OFFSET;
487 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
490 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
495 * scc_mgr_zero_all() - Zero all DQS config
497 * Zero all DQS config.
499 static void scc_mgr_zero_all(void)
504 * USER Zero all DQS config settings, across all groups and all
507 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
508 r += NUM_RANKS_PER_SHADOW_REG) {
509 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
511 * The phases actually don't exist on a per-rank basis,
512 * but there's no harm updating them several times, so
513 * let's keep the code simple.
515 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
516 scc_mgr_set_dqs_en_phase(i, 0);
517 scc_mgr_set_dqs_en_delay(i, 0);
520 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
521 scc_mgr_set_dqdqs_output_phase(i, 0);
522 /* Arria V/Cyclone V don't have out2. */
523 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
527 /* Multicast to all DQS group enables. */
528 writel(0xff, &sdr_scc_mgr->dqs_ena);
529 writel(0, &sdr_scc_mgr->update);
533 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
534 * @write_group: Write group
536 * Set bypass mode and trigger SCC update.
538 static void scc_set_bypass_mode(const u32 write_group)
540 /* Multicast to all DQ enables. */
541 writel(0xff, &sdr_scc_mgr->dq_ena);
542 writel(0xff, &sdr_scc_mgr->dm_ena);
544 /* Update current DQS IO enable. */
545 writel(0, &sdr_scc_mgr->dqs_io_ena);
547 /* Update the DQS logic. */
548 writel(write_group, &sdr_scc_mgr->dqs_ena);
551 writel(0, &sdr_scc_mgr->update);
555 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
556 * @write_group: Write group
558 * Load DQS settings for Write Group, do not trigger SCC update.
560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
562 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
563 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
564 const int base = write_group * ratio;
567 * Load the setting in the SCC manager
568 * Although OCT affects only write data, the OCT delay is controlled
569 * by the DQS logic block which is instantiated once per read group.
570 * For protocols where a write group consists of multiple read groups,
571 * the setting must be set multiple times.
573 for (i = 0; i < ratio; i++)
574 writel(base + i, &sdr_scc_mgr->dqs_ena);
578 * scc_mgr_zero_group() - Zero all configs for a group
580 * Zero DQ, DM, DQS and OCT configs for a group.
582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
586 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
587 r += NUM_RANKS_PER_SHADOW_REG) {
588 /* Zero all DQ config settings. */
589 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
590 scc_mgr_set_dq_out1_delay(i, 0);
592 scc_mgr_set_dq_in_delay(i, 0);
595 /* Multicast to all DQ enables. */
596 writel(0xff, &sdr_scc_mgr->dq_ena);
598 /* Zero all DM config settings. */
599 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
600 scc_mgr_set_dm_out1_delay(i, 0);
602 /* Multicast to all DM enables. */
603 writel(0xff, &sdr_scc_mgr->dm_ena);
605 /* Zero all DQS IO settings. */
607 scc_mgr_set_dqs_io_in_delay(0);
609 /* Arria V/Cyclone V don't have out2. */
610 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
611 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
612 scc_mgr_load_dqs_for_write_group(write_group);
614 /* Multicast to all DQS IO enables (only 1 in total). */
615 writel(0, &sdr_scc_mgr->dqs_io_ena);
617 /* Hit update to zero everything. */
618 writel(0, &sdr_scc_mgr->update);
623 * apply and load a particular input delay for the DQ pins in a group
624 * group_bgn is the index of the first dq pin (in the write group)
626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
630 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
631 scc_mgr_set_dq_in_delay(p, delay);
637 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
638 * @delay: Delay value
640 * Apply and load a particular output delay for the DQ pins in a group.
642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
646 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
647 scc_mgr_set_dq_out1_delay(i, delay);
652 /* apply and load a particular output delay for the DM pins in a group */
653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
657 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
658 scc_mgr_set_dm_out1_delay(i, delay1);
664 /* apply and load delay on both DQS and OCT out1 */
665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
668 scc_mgr_set_dqs_out1_delay(delay);
669 scc_mgr_load_dqs_io();
671 scc_mgr_set_oct_out1_delay(write_group, delay);
672 scc_mgr_load_dqs_for_write_group(write_group);
676 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
677 * @write_group: Write group
678 * @delay: Delay value
680 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
688 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
692 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
696 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
697 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
698 debug_cond(DLEVEL == 1,
699 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
700 __func__, __LINE__, write_group, delay, new_delay,
701 IO_IO_OUT2_DELAY_MAX,
702 new_delay - IO_IO_OUT2_DELAY_MAX);
703 new_delay -= IO_IO_OUT2_DELAY_MAX;
704 scc_mgr_set_dqs_out1_delay(new_delay);
707 scc_mgr_load_dqs_io();
710 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
711 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
712 debug_cond(DLEVEL == 1,
713 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
714 __func__, __LINE__, write_group, delay,
715 new_delay, IO_IO_OUT2_DELAY_MAX,
716 new_delay - IO_IO_OUT2_DELAY_MAX);
717 new_delay -= IO_IO_OUT2_DELAY_MAX;
718 scc_mgr_set_oct_out1_delay(write_group, new_delay);
721 scc_mgr_load_dqs_for_write_group(write_group);
725 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
726 * @write_group: Write group
727 * @delay: Delay value
729 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
737 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
738 r += NUM_RANKS_PER_SHADOW_REG) {
739 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
740 writel(0, &sdr_scc_mgr->update);
745 * set_jump_as_return() - Return instruction optimization
747 * Optimization used to recover some slots in ddr3 inst_rom could be
748 * applied to other protocols if we wanted to
750 static void set_jump_as_return(void)
753 * To save space, we replace return with jump to special shared
754 * RETURN instruction so we set the counter to large value so that
757 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
758 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
762 * should always use constants as argument to ensure all computations are
763 * performed at compile time
765 static void delay_for_n_mem_clocks(const uint32_t clocks)
772 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
775 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
776 /* scale (rounding up) to get afi clocks */
779 * Note, we don't bother accounting for being off a little bit
780 * because of a few extra instructions in outer loops
781 * Note, the loops have a test at the end, and do the test before
782 * the decrement, and so always perform the loop
783 * 1 time more than the counter value
785 if (afi_clocks == 0) {
787 } else if (afi_clocks <= 0x100) {
788 inner = afi_clocks-1;
791 } else if (afi_clocks <= 0x10000) {
793 outer = (afi_clocks-1) >> 8;
798 c_loop = (afi_clocks-1) >> 16;
802 * rom instructions are structured as follows:
804 * IDLE_LOOP2: jnz cntr0, TARGET_A
805 * IDLE_LOOP1: jnz cntr1, TARGET_B
808 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
809 * TARGET_B is set to IDLE_LOOP2 as well
811 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
812 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
814 * a little confusing, but it helps save precious space in the inst_rom
815 * and sequencer rom and keeps the delays more accurate and reduces
818 if (afi_clocks <= 0x100) {
819 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
820 &sdr_rw_load_mgr_regs->load_cntr1);
822 writel(RW_MGR_IDLE_LOOP1,
823 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
825 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
826 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
828 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
829 &sdr_rw_load_mgr_regs->load_cntr0);
831 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
832 &sdr_rw_load_mgr_regs->load_cntr1);
834 writel(RW_MGR_IDLE_LOOP2,
835 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
837 writel(RW_MGR_IDLE_LOOP2,
838 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
840 /* hack to get around compiler not being smart enough */
841 if (afi_clocks <= 0x10000) {
842 /* only need to run once */
843 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
844 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
847 writel(RW_MGR_IDLE_LOOP2,
848 SDR_PHYGRP_RWMGRGRP_ADDRESS |
849 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
850 } while (c_loop-- != 0);
853 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
857 * rw_mgr_mem_init_load_regs() - Load instruction registers
858 * @cntr0: Counter 0 value
859 * @cntr1: Counter 1 value
860 * @cntr2: Counter 2 value
861 * @jump: Jump instruction value
863 * Load instruction registers.
865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
867 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
868 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
872 &sdr_rw_load_mgr_regs->load_cntr0);
873 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
874 &sdr_rw_load_mgr_regs->load_cntr1);
875 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
876 &sdr_rw_load_mgr_regs->load_cntr2);
878 /* Load jump address */
879 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
880 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
881 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
883 /* Execute count instruction */
884 writel(jump, grpaddr);
888 * rw_mgr_mem_load_user() - Load user calibration values
889 * @fin1: Final instruction 1
890 * @fin2: Final instruction 2
891 * @precharge: If 1, precharge the banks at the end
893 * Load user calibration values and optionally precharge the banks.
895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
898 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
899 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
902 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
903 if (param->skip_ranks[r]) {
904 /* request to skip the rank */
909 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
911 /* precharge all banks ... */
913 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
916 * USER Use Mirror-ed commands for odd ranks if address
919 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
920 set_jump_as_return();
921 writel(RW_MGR_MRS2_MIRR, grpaddr);
922 delay_for_n_mem_clocks(4);
923 set_jump_as_return();
924 writel(RW_MGR_MRS3_MIRR, grpaddr);
925 delay_for_n_mem_clocks(4);
926 set_jump_as_return();
927 writel(RW_MGR_MRS1_MIRR, grpaddr);
928 delay_for_n_mem_clocks(4);
929 set_jump_as_return();
930 writel(fin1, grpaddr);
932 set_jump_as_return();
933 writel(RW_MGR_MRS2, grpaddr);
934 delay_for_n_mem_clocks(4);
935 set_jump_as_return();
936 writel(RW_MGR_MRS3, grpaddr);
937 delay_for_n_mem_clocks(4);
938 set_jump_as_return();
939 writel(RW_MGR_MRS1, grpaddr);
940 set_jump_as_return();
941 writel(fin2, grpaddr);
947 set_jump_as_return();
948 writel(RW_MGR_ZQCL, grpaddr);
950 /* tZQinit = tDLLK = 512 ck cycles */
951 delay_for_n_mem_clocks(512);
956 * rw_mgr_mem_initialize() - Initialize RW Manager
958 * Initialize RW Manager.
960 static void rw_mgr_mem_initialize(void)
962 debug("%s:%d\n", __func__, __LINE__);
964 /* The reset / cke part of initialization is broadcasted to all ranks */
965 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
966 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
969 * Here's how you load register for a loop
970 * Counters are located @ 0x800
971 * Jump address are located @ 0xC00
972 * For both, registers 0 to 3 are selected using bits 3 and 2, like
973 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
974 * I know this ain't pretty, but Avalon bus throws away the 2 least
978 /* Start with memory RESET activated */
983 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
984 * If a and b are the number of iteration in 2 nested loops
985 * it takes the following number of cycles to complete the operation:
986 * number_of_cycles = ((2 + n) * a + 2) * b
987 * where n is the number of instruction in the inner loop
988 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
991 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
993 RW_MGR_INIT_RESET_0_CKE_0);
995 /* Indicate that memory is stable. */
996 writel(1, &phy_mgr_cfg->reset_mem_stbl);
999 * transition the RESET to high
1004 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005 * If a and b are the number of iteration in 2 nested loops
1006 * it takes the following number of cycles to complete the operation
1007 * number_of_cycles = ((2 + n) * a + 2) * b
1008 * where n is the number of instruction in the inner loop
1009 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1012 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013 SEQ_TRESET_CNTR2_VAL,
1014 RW_MGR_INIT_RESET_1_CKE_0);
1016 /* Bring up clock enable. */
1018 /* tXRP < 250 ck cycles */
1019 delay_for_n_mem_clocks(250);
1021 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1026 * At the end of calibration we have to program the user settings in, and
1027 * USER hand off the memory to the user.
1029 static void rw_mgr_mem_handoff(void)
1031 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1033 * USER need to wait tMOD (12CK or 15ns) time before issuing
1034 * other commands, but we will have plenty of NIOS cycles before
1035 * actual handoff so its okay.
1040 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041 * @rank_bgn: Rank number
1042 * @group: Read/Write Group
1043 * @all_ranks: Test all ranks
1045 * Performs a guaranteed read on the patterns we are going to use during a
1046 * read test to ensure memory works.
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050 const u32 all_ranks)
1052 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054 const u32 addr_offset =
1055 (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056 const u32 rank_end = all_ranks ?
1057 RW_MGR_MEM_NUMBER_OF_RANKS :
1058 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061 const u32 correct_mask_vg = param->read_correct_mask_vg;
1063 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1067 bit_chk = param->read_correct_mask;
1069 for (r = rank_bgn; r < rank_end; r++) {
1070 /* Request to skip the rank */
1071 if (param->skip_ranks[r])
1075 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1077 /* Load up a constant bursts of read commands */
1078 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079 writel(RW_MGR_GUARANTEED_READ,
1080 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1082 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083 writel(RW_MGR_GUARANTEED_READ_CONT,
1084 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1087 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1089 /* Reset the FIFOs to get pointers to known state. */
1090 writel(0, &phy_mgr_cmd->fifo_reset);
1091 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093 writel(RW_MGR_GUARANTEED_READ,
1094 addr + addr_offset + (vg << 2));
1096 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097 tmp_bit_chk <<= shift_ratio;
1098 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1101 bit_chk &= tmp_bit_chk;
1104 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1106 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1108 if (bit_chk != param->read_correct_mask)
1111 debug_cond(DLEVEL == 1,
1112 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113 __func__, __LINE__, group, bit_chk,
1114 param->read_correct_mask, ret);
1120 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121 * @rank_bgn: Rank number
1122 * @all_ranks: Test all ranks
1124 * Load up the patterns we are going to use during a read test.
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127 const int all_ranks)
1129 const u32 rank_end = all_ranks ?
1130 RW_MGR_MEM_NUMBER_OF_RANKS :
1131 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1134 debug("%s:%d\n", __func__, __LINE__);
1136 for (r = rank_bgn; r < rank_end; r++) {
1137 if (param->skip_ranks[r])
1138 /* request to skip the rank */
1142 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1144 /* Load up a constant bursts */
1145 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1147 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1150 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1152 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1155 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1157 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1160 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1162 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1165 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1169 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1173 * try a read and see if it returns correct data back. has dummy reads
1174 * inserted into the mix used to align dqs enable. has more thorough checks
1175 * than the regular read test.
1177 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1178 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1179 uint32_t all_groups, uint32_t all_ranks)
1182 uint32_t correct_mask_vg;
1183 uint32_t tmp_bit_chk;
1184 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1185 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1187 uint32_t base_rw_mgr;
1189 *bit_chk = param->read_correct_mask;
1190 correct_mask_vg = param->read_correct_mask_vg;
1192 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1193 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1195 for (r = rank_bgn; r < rank_end; r++) {
1196 if (param->skip_ranks[r])
1197 /* request to skip the rank */
1201 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1203 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1205 writel(RW_MGR_READ_B2B_WAIT1,
1206 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1208 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1209 writel(RW_MGR_READ_B2B_WAIT2,
1210 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1212 if (quick_read_mode)
1213 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1214 /* need at least two (1+1) reads to capture failures */
1215 else if (all_groups)
1216 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1218 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1220 writel(RW_MGR_READ_B2B,
1221 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1223 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1224 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1225 &sdr_rw_load_mgr_regs->load_cntr3);
1227 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1229 writel(RW_MGR_READ_B2B,
1230 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1233 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1234 /* reset the fifos to get pointers to known state */
1235 writel(0, &phy_mgr_cmd->fifo_reset);
1236 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1237 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1239 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1240 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1243 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1245 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1247 writel(RW_MGR_READ_B2B, addr +
1248 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1251 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1252 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1257 *bit_chk &= tmp_bit_chk;
1260 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1261 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1264 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1265 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1266 (%u == %u) => %lu", __func__, __LINE__, group,
1267 all_groups, *bit_chk, param->read_correct_mask,
1268 (long unsigned int)(*bit_chk ==
1269 param->read_correct_mask));
1270 return *bit_chk == param->read_correct_mask;
1272 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1273 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1274 (%u != %lu) => %lu\n", __func__, __LINE__,
1275 group, all_groups, *bit_chk, (long unsigned int)0,
1276 (long unsigned int)(*bit_chk != 0x00));
1277 return *bit_chk != 0x00;
1281 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1282 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1283 uint32_t all_groups)
1285 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1286 bit_chk, all_groups, 1);
1290 * rw_mgr_incr_vfifo() - Increase VFIFO value
1291 * @grp: Read/Write group
1294 * Increase VFIFO value.
1296 static void rw_mgr_incr_vfifo(const u32 grp, u32 *v)
1298 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1303 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1304 * @grp: Read/Write group
1307 * Decrease VFIFO value.
1309 static void rw_mgr_decr_vfifo(const u32 grp, u32 *v)
1313 for (i = 0; i < VFIFO_SIZE - 1; i++)
1314 rw_mgr_incr_vfifo(grp, v);
1317 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1320 uint32_t fail_cnt = 0;
1321 uint32_t test_status;
1323 for (v = 0; v < VFIFO_SIZE; ) {
1324 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1325 __func__, __LINE__, v);
1326 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1327 (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1335 /* fiddle with FIFO */
1336 rw_mgr_incr_vfifo(grp, &v);
1339 if (v >= VFIFO_SIZE) {
1340 /* no failing read found!! Something must have gone wrong */
1341 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1342 __func__, __LINE__);
1350 * sdr_find_phase() - Find DQS enable phase
1351 * @working: If 1, look for working phase, if 0, look for non-working phase
1352 * @grp: Read/Write group
1354 * @work: Working window position
1356 * @p: DQS Phase Iterator
1358 * Find working or non-working DQS enable phase setting.
1360 static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
1364 const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1366 for (; *i < end; (*i)++) {
1370 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++) {
1371 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1373 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1374 PASS_ONE_BIT, &bit_chk, 0);
1381 *work += IO_DELAY_PER_OPA_TAP;
1384 if (*p > IO_DQS_EN_PHASE_MAX) {
1385 /* Fiddle with FIFO. */
1386 rw_mgr_incr_vfifo(grp, v);
1396 * sdr_working_phase() - Find working DQS enable phase
1397 * @grp: Read/Write group
1398 * @work_bgn: Working window start position
1400 * @d: dtaps output value
1401 * @p: DQS Phase Iterator
1404 * Find working DQS enable phase setting.
1406 static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *d,
1409 const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1410 IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1415 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1417 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1418 ret = sdr_find_phase(1, grp, v, work_bgn, i, p);
1421 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1424 /* Cannot find working solution */
1425 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1426 __func__, __LINE__);
1431 * sdr_backup_phase() - Find DQS enable backup phase
1432 * @grp: Read/Write group
1433 * @work_bgn: Working window start position
1435 * @p: DQS Phase Iterator
1437 * Find DQS enable backup phase setting.
1439 static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *p)
1441 u32 tmp_delay, bit_chk, d;
1444 /* Special case code for backing up a phase */
1446 *p = IO_DQS_EN_PHASE_MAX;
1447 rw_mgr_decr_vfifo(grp, v);
1451 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1452 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1454 for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
1455 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1457 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1458 PASS_ONE_BIT, &bit_chk, 0);
1460 *work_bgn = tmp_delay;
1464 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1467 /* Restore VFIFO to old state before we decremented it (if needed). */
1469 if (*p > IO_DQS_EN_PHASE_MAX) {
1471 rw_mgr_incr_vfifo(grp, v);
1474 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1478 * sdr_nonworking_phase() - Find non-working DQS enable phase
1479 * @grp: Read/Write group
1480 * @work_end: Working window end position
1482 * @p: DQS Phase Iterator
1485 * Find non-working DQS enable phase setting.
1487 static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *v,
1493 *work_end += IO_DELAY_PER_OPA_TAP;
1494 if (*p > IO_DQS_EN_PHASE_MAX) {
1495 /* Fiddle with FIFO. */
1497 rw_mgr_incr_vfifo(grp, v);
1500 ret = sdr_find_phase(0, grp, v, work_end, i, p);
1502 /* Cannot see edge of failing read. */
1503 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1504 __func__, __LINE__);
1511 * sdr_find_window_center() - Find center of the working DQS window.
1512 * @grp: Read/Write group
1513 * @work_bgn: First working settings
1514 * @work_end: Last working settings
1517 * Find center of the working DQS enable window.
1519 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1520 const u32 work_end, const u32 val)
1522 u32 bit_chk, work_mid, v = val;
1526 work_mid = (work_bgn + work_end) / 2;
1528 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1529 work_bgn, work_end, work_mid);
1530 /* Get the middle delay to be less than a VFIFO delay */
1531 tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1533 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1534 work_mid %= tmp_delay;
1535 debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1537 tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1538 if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1539 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1540 p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1542 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1544 d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1545 if (d > IO_DQS_EN_DELAY_MAX)
1546 d = IO_DQS_EN_DELAY_MAX;
1547 tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1549 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1551 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1552 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1555 * push vfifo until we can successfully calibrate. We can do this
1556 * because the largest possible margin in 1 VFIFO cycle.
1558 for (i = 0; i < VFIFO_SIZE; i++) {
1559 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1561 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1564 debug_cond(DLEVEL == 2,
1565 "%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
1566 __func__, __LINE__, v, p, d);
1570 /* Fiddle with FIFO. */
1571 rw_mgr_incr_vfifo(grp, &v);
1574 debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1575 __func__, __LINE__);
1579 /* find a good dqs enable to use */
1580 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1582 uint32_t v, d, p, i;
1584 uint32_t dtaps_per_ptap;
1585 uint32_t work_bgn, work_end;
1586 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1588 debug("%s:%d %u\n", __func__, __LINE__, grp);
1590 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1592 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1593 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1595 /* ************************************************************** */
1596 /* * Step 0 : Determine number of delay taps for each phase tap * */
1597 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1599 /* ********************************************************* */
1600 /* * Step 1 : First push vfifo until we get a failing read * */
1601 v = find_vfifo_read(grp, &bit_chk);
1603 /* ******************************************************** */
1604 /* * step 2: find first working phase, increment in ptaps * */
1606 if (sdr_working_phase(grp, &work_bgn, &v, &d, &p, &i))
1609 work_end = work_bgn;
1612 * If d is 0 then the working window covers a phase tap and
1613 * we can follow the old procedure otherwise, we've found the beginning,
1614 * and we need to increment the dtaps until we find the end.
1617 /* ********************************************************* */
1618 /* * step 3a: if we have room, back off by one and
1619 increment in dtaps * */
1621 sdr_backup_phase(grp, &work_bgn, &v, &p);
1623 /* ********************************************************* */
1624 /* * step 4a: go forward from working phase to non working
1625 phase, increment in ptaps * */
1626 if (sdr_nonworking_phase(grp, &work_end, &v, &p, &i))
1629 /* ********************************************************* */
1630 /* * step 5a: back off one from last, increment in dtaps * */
1632 /* Special case code for backing up a phase */
1634 p = IO_DQS_EN_PHASE_MAX;
1635 rw_mgr_decr_vfifo(grp, &v);
1640 work_end -= IO_DELAY_PER_OPA_TAP;
1641 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1643 /* * The actual increment of dtaps is done outside of
1644 the if/else loop to share code */
1647 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1648 vfifo=%u ptap=%u\n", __func__, __LINE__,
1651 /* ******************************************************* */
1652 /* * step 3-5b: Find the right edge of the window using
1654 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1655 ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1658 work_end = work_bgn;
1661 /* The dtap increment to find the failing edge is done here */
1662 for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1663 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1664 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1665 end-2: dtap=%u\n", __func__, __LINE__, d);
1666 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1668 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1675 /* Go back to working dtap */
1677 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1679 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1680 ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1681 v, p, d-1, work_end);
1683 if (work_end < work_bgn) {
1685 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1686 failed\n", __func__, __LINE__);
1690 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1691 __func__, __LINE__, work_bgn, work_end);
1693 /* *************************************************************** */
1695 * * We need to calculate the number of dtaps that equal a ptap
1696 * * To do that we'll back up a ptap and re-find the edge of the
1697 * * window using dtaps
1700 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1701 for tracking\n", __func__, __LINE__);
1703 /* Special case code for backing up a phase */
1705 p = IO_DQS_EN_PHASE_MAX;
1706 rw_mgr_decr_vfifo(grp, &v);
1707 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1708 cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1712 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1713 phase only: v=%u p=%u", __func__, __LINE__,
1717 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1720 * Increase dtap until we first see a passing read (in case the
1721 * window is smaller than a ptap),
1722 * and then a failing read to mark the edge of the window again
1725 /* Find a passing read */
1726 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1727 __func__, __LINE__);
1728 found_passing_read = 0;
1729 found_failing_read = 0;
1730 initial_failing_dtap = d;
1731 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1732 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1733 read d=%u\n", __func__, __LINE__, d);
1734 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1736 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1739 found_passing_read = 1;
1744 if (found_passing_read) {
1745 /* Find a failing read */
1746 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1747 read\n", __func__, __LINE__);
1748 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1749 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1750 testing read d=%u\n", __func__, __LINE__, d);
1751 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1753 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1754 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1755 found_failing_read = 1;
1760 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1761 calculate dtaps", __func__, __LINE__);
1762 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1766 * The dynamically calculated dtaps_per_ptap is only valid if we
1767 * found a passing/failing read. If we didn't, it means d hit the max
1768 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1769 * statically calculated value.
1771 if (found_passing_read && found_failing_read)
1772 dtaps_per_ptap = d - initial_failing_dtap;
1774 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1775 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1776 - %u = %u", __func__, __LINE__, d,
1777 initial_failing_dtap, dtaps_per_ptap);
1779 /* ******************************************** */
1780 /* * step 6: Find the centre of the window * */
1781 if (sdr_find_window_centre(grp, work_bgn, work_end, v))
1782 return 0; /* FIXME: Old code, return 0 means failure :-( */
1787 /* per-bit deskew DQ and center */
1788 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1789 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1790 uint32_t use_read_test, uint32_t update_fom)
1792 uint32_t i, p, d, min_index;
1794 * Store these as signed since there are comparisons with
1798 uint32_t sticky_bit_chk;
1799 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1800 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1801 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1803 int32_t orig_mid_min, mid_min;
1804 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1806 int32_t dq_margin, dqs_margin;
1808 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1811 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1813 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1814 start_dqs = readl(addr + (read_group << 2));
1815 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1816 start_dqs_en = readl(addr + ((read_group << 2)
1817 - IO_DQS_EN_DELAY_OFFSET));
1819 /* set the left and right edge of each bit to an illegal value */
1820 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1822 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1823 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1824 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1827 /* Search for the left edge of the window for each bit */
1828 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1829 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1831 writel(0, &sdr_scc_mgr->update);
1834 * Stop searching when the read test doesn't pass AND when
1835 * we've seen a passing read on every bit.
1837 if (use_read_test) {
1838 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1839 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1842 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1845 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1846 (read_group - (write_group *
1847 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1848 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1849 stop = (bit_chk == 0);
1851 sticky_bit_chk = sticky_bit_chk | bit_chk;
1852 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1853 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1854 && %u", __func__, __LINE__, d,
1856 param->read_correct_mask, stop);
1861 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1863 /* Remember a passing test as the
1867 /* If a left edge has not been seen yet,
1868 then a future passing test will mark
1869 this edge as the right edge */
1871 IO_IO_IN_DELAY_MAX + 1) {
1872 right_edge[i] = -(d + 1);
1875 bit_chk = bit_chk >> 1;
1880 /* Reset DQ delay chains to 0 */
1881 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1883 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1884 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1885 %d right_edge[%u]: %d\n", __func__, __LINE__,
1886 i, left_edge[i], i, right_edge[i]);
1889 * Check for cases where we haven't found the left edge,
1890 * which makes our assignment of the the right edge invalid.
1891 * Reset it to the illegal value.
1893 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1894 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1895 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1896 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1897 right_edge[%u]: %d\n", __func__, __LINE__,
1902 * Reset sticky bit (except for bits where we have seen
1903 * both the left and right edge).
1905 sticky_bit_chk = sticky_bit_chk << 1;
1906 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1907 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1908 sticky_bit_chk = sticky_bit_chk | 1;
1915 /* Search for the right edge of the window for each bit */
1916 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1917 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1918 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1919 uint32_t delay = d + start_dqs_en;
1920 if (delay > IO_DQS_EN_DELAY_MAX)
1921 delay = IO_DQS_EN_DELAY_MAX;
1922 scc_mgr_set_dqs_en_delay(read_group, delay);
1924 scc_mgr_load_dqs(read_group);
1926 writel(0, &sdr_scc_mgr->update);
1929 * Stop searching when the read test doesn't pass AND when
1930 * we've seen a passing read on every bit.
1932 if (use_read_test) {
1933 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1934 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1937 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1940 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1941 (read_group - (write_group *
1942 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1943 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1944 stop = (bit_chk == 0);
1946 sticky_bit_chk = sticky_bit_chk | bit_chk;
1947 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1949 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1950 %u && %u", __func__, __LINE__, d,
1951 sticky_bit_chk, param->read_correct_mask, stop);
1956 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1958 /* Remember a passing test as
1963 /* If a right edge has not been
1964 seen yet, then a future passing
1965 test will mark this edge as the
1967 if (right_edge[i] ==
1968 IO_IO_IN_DELAY_MAX + 1) {
1969 left_edge[i] = -(d + 1);
1972 /* d = 0 failed, but it passed
1973 when testing the left edge,
1974 so it must be marginal,
1976 if (right_edge[i] ==
1977 IO_IO_IN_DELAY_MAX + 1 &&
1983 /* If a right edge has not been
1984 seen yet, then a future passing
1985 test will mark this edge as the
1987 else if (right_edge[i] ==
1988 IO_IO_IN_DELAY_MAX +
1990 left_edge[i] = -(d + 1);
1995 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
1996 d=%u]: ", __func__, __LINE__, d);
1997 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
1998 (int)(bit_chk & 1), i, left_edge[i]);
1999 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2001 bit_chk = bit_chk >> 1;
2006 /* Check that all bits have a window */
2007 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2008 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2009 %d right_edge[%u]: %d", __func__, __LINE__,
2010 i, left_edge[i], i, right_edge[i]);
2011 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2012 == IO_IO_IN_DELAY_MAX + 1)) {
2014 * Restore delay chain settings before letting the loop
2015 * in rw_mgr_mem_calibrate_vfifo to retry different
2016 * dqs/ck relationships.
2018 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2019 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2020 scc_mgr_set_dqs_en_delay(read_group,
2023 scc_mgr_load_dqs(read_group);
2024 writel(0, &sdr_scc_mgr->update);
2026 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2027 find edge [%u]: %d %d", __func__, __LINE__,
2028 i, left_edge[i], right_edge[i]);
2029 if (use_read_test) {
2030 set_failing_group_stage(read_group *
2031 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2033 CAL_SUBSTAGE_VFIFO_CENTER);
2035 set_failing_group_stage(read_group *
2036 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2037 CAL_STAGE_VFIFO_AFTER_WRITES,
2038 CAL_SUBSTAGE_VFIFO_CENTER);
2044 /* Find middle of window for each DQ bit */
2045 mid_min = left_edge[0] - right_edge[0];
2047 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2048 mid = left_edge[i] - right_edge[i];
2049 if (mid < mid_min) {
2056 * -mid_min/2 represents the amount that we need to move DQS.
2057 * If mid_min is odd and positive we'll need to add one to
2058 * make sure the rounding in further calculations is correct
2059 * (always bias to the right), so just add 1 for all positive values.
2064 mid_min = mid_min / 2;
2066 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2067 __func__, __LINE__, mid_min, min_index);
2069 /* Determine the amount we can change DQS (which is -mid_min) */
2070 orig_mid_min = mid_min;
2071 new_dqs = start_dqs - mid_min;
2072 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2073 new_dqs = IO_DQS_IN_DELAY_MAX;
2074 else if (new_dqs < 0)
2077 mid_min = start_dqs - new_dqs;
2078 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2081 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2082 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2083 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2084 else if (start_dqs_en - mid_min < 0)
2085 mid_min += start_dqs_en - mid_min;
2087 new_dqs = start_dqs - mid_min;
2089 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2090 new_dqs=%d mid_min=%d\n", start_dqs,
2091 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2094 /* Initialize data for export structures */
2095 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2096 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2098 /* add delay to bring centre of all DQ windows to the same "level" */
2099 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2100 /* Use values before divide by 2 to reduce round off error */
2101 shift_dq = (left_edge[i] - right_edge[i] -
2102 (left_edge[min_index] - right_edge[min_index]))/2 +
2103 (orig_mid_min - mid_min);
2105 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2106 shift_dq[%u]=%d\n", i, shift_dq);
2108 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2109 temp_dq_in_delay1 = readl(addr + (p << 2));
2110 temp_dq_in_delay2 = readl(addr + (i << 2));
2112 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2113 (int32_t)IO_IO_IN_DELAY_MAX) {
2114 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2115 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2116 shift_dq = -(int32_t)temp_dq_in_delay1;
2118 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2119 shift_dq[%u]=%d\n", i, shift_dq);
2120 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2121 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2124 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2125 left_edge[i] - shift_dq + (-mid_min),
2126 right_edge[i] + shift_dq - (-mid_min));
2127 /* To determine values for export structures */
2128 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2129 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2131 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2132 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2135 final_dqs = new_dqs;
2136 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2137 final_dqs_en = start_dqs_en - mid_min;
2140 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2141 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2142 scc_mgr_load_dqs(read_group);
2146 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2147 scc_mgr_load_dqs(read_group);
2148 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2149 dqs_margin=%d", __func__, __LINE__,
2150 dq_margin, dqs_margin);
2153 * Do not remove this line as it makes sure all of our decisions
2154 * have been applied. Apply the update bit.
2156 writel(0, &sdr_scc_mgr->update);
2158 return (dq_margin >= 0) && (dqs_margin >= 0);
2162 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2163 * @rw_group: Read/Write Group
2164 * @phase: DQ/DQS phase
2166 * Because initially no communication ca be reliably performed with the memory
2167 * device, the sequencer uses a guaranteed write mechanism to write data into
2168 * the memory device.
2170 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2175 /* Set a particular DQ/DQS phase. */
2176 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2178 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2179 __func__, __LINE__, rw_group, phase);
2182 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2183 * Load up the patterns used by read calibration using the
2184 * current DQDQS phase.
2186 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2188 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2192 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2193 * Back-to-Back reads of the patterns used for calibration.
2195 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2197 debug_cond(DLEVEL == 1,
2198 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2199 __func__, __LINE__, rw_group, phase);
2204 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2205 * @rw_group: Read/Write Group
2206 * @test_bgn: Rank at which the test begins
2208 * DQS enable calibration ensures reliable capture of the DQ signal without
2209 * glitches on the DQS line.
2211 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2215 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2216 * DQS and DQS Eanble Signal Relationships.
2219 /* We start at zero, so have one less dq to devide among */
2220 const u32 delay_step = IO_IO_IN_DELAY_MAX /
2221 (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2225 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2227 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2228 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2229 r += NUM_RANKS_PER_SHADOW_REG) {
2230 for (i = 0, p = test_bgn, d = 0;
2231 i < RW_MGR_MEM_DQ_PER_READ_DQS;
2232 i++, p++, d += delay_step) {
2233 debug_cond(DLEVEL == 1,
2234 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2235 __func__, __LINE__, rw_group, r, i, p, d);
2237 scc_mgr_set_dq_in_delay(p, d);
2241 writel(0, &sdr_scc_mgr->update);
2245 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2246 * dq_in_delay values
2248 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2250 debug_cond(DLEVEL == 1,
2251 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2252 __func__, __LINE__, rw_group, found);
2254 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2255 r += NUM_RANKS_PER_SHADOW_REG) {
2256 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2257 writel(0, &sdr_scc_mgr->update);
2268 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2269 * @rw_group: Read/Write Group
2270 * @test_bgn: Rank at which the test begins
2271 * @use_read_test: Perform a read test
2272 * @update_fom: Update FOM
2274 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2278 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2279 const int use_read_test,
2280 const int update_fom)
2283 int ret, grp_calibrated;
2287 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2288 * Read per-bit deskew can be done on a per shadow register basis.
2291 for (rank_bgn = 0, sr = 0;
2292 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2293 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2294 /* Check if this set of ranks should be skipped entirely. */
2295 if (param->skip_shadow_regs[sr])
2298 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2308 if (!grp_calibrated)
2315 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2316 * @rw_group: Read/Write Group
2317 * @test_bgn: Rank at which the test begins
2319 * Stage 1: Calibrate the read valid prediction FIFO.
2321 * This function implements UniPHY calibration Stage 1, as explained in
2322 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2324 * - read valid prediction will consist of finding:
2325 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2326 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2327 * - we also do a per-bit deskew on the DQ lines.
2329 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2332 uint32_t dtaps_per_ptap;
2333 uint32_t failed_substage;
2337 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2339 /* Update info for sims */
2340 reg_file_set_group(rw_group);
2341 reg_file_set_stage(CAL_STAGE_VFIFO);
2342 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2344 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2346 /* USER Determine number of delay taps for each phase tap. */
2347 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2348 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2350 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2352 * In RLDRAMX we may be messing the delay of pins in
2353 * the same write rw_group but outside of the current read
2354 * the rw_group, but that's ok because we haven't calibrated
2358 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2362 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2363 /* 1) Guaranteed Write */
2364 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2368 /* 2) DQS Enable Calibration */
2369 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2372 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2376 /* 3) Centering DQ/DQS */
2378 * If doing read after write calibration, do not update
2379 * FOM now. Do it then.
2381 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2384 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2393 /* Calibration Stage 1 failed. */
2394 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2397 /* Calibration Stage 1 completed OK. */
2400 * Reset the delay chains back to zero if they have moved > 1
2401 * (check for > 1 because loop will increase d even when pass in
2405 scc_mgr_zero_group(rw_group, 1);
2410 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2411 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2414 uint32_t rank_bgn, sr;
2415 uint32_t grp_calibrated;
2416 uint32_t write_group;
2418 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2420 /* update info for sims */
2422 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2423 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2425 write_group = read_group;
2427 /* update info for sims */
2428 reg_file_set_group(read_group);
2431 /* Read per-bit deskew can be done on a per shadow register basis */
2432 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2433 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2434 /* Determine if this set of ranks should be skipped entirely */
2435 if (!param->skip_shadow_regs[sr]) {
2436 /* This is the last calibration round, update FOM here */
2437 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2448 if (grp_calibrated == 0) {
2449 set_failing_group_stage(write_group,
2450 CAL_STAGE_VFIFO_AFTER_WRITES,
2451 CAL_SUBSTAGE_VFIFO_CENTER);
2458 /* Calibrate LFIFO to find smallest read latency */
2459 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2464 debug("%s:%d\n", __func__, __LINE__);
2466 /* update info for sims */
2467 reg_file_set_stage(CAL_STAGE_LFIFO);
2468 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2470 /* Load up the patterns used by read calibration for all ranks */
2471 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2475 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2476 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2477 __func__, __LINE__, gbl->curr_read_lat);
2479 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2487 /* reduce read latency and see if things are working */
2489 gbl->curr_read_lat--;
2490 } while (gbl->curr_read_lat > 0);
2492 /* reset the fifos to get pointers to known state */
2494 writel(0, &phy_mgr_cmd->fifo_reset);
2497 /* add a fudge factor to the read latency that was determined */
2498 gbl->curr_read_lat += 2;
2499 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2500 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2501 read_lat=%u\n", __func__, __LINE__,
2502 gbl->curr_read_lat);
2505 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2506 CAL_SUBSTAGE_READ_LATENCY);
2508 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2509 read_lat=%u\n", __func__, __LINE__,
2510 gbl->curr_read_lat);
2516 * issue write test command.
2517 * two variants are provided. one that just tests a write pattern and
2518 * another that tests datamask functionality.
2520 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2523 uint32_t mcc_instruction;
2524 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2525 ENABLE_SUPER_QUICK_CALIBRATION);
2526 uint32_t rw_wl_nop_cycles;
2530 * Set counter and jump addresses for the right
2531 * number of NOP cycles.
2532 * The number of supported NOP cycles can range from -1 to infinity
2533 * Three different cases are handled:
2535 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2536 * mechanism will be used to insert the right number of NOPs
2538 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2539 * issuing the write command will jump straight to the
2540 * micro-instruction that turns on DQS (for DDRx), or outputs write
2541 * data (for RLD), skipping
2542 * the NOP micro-instruction all together
2544 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2545 * turned on in the same micro-instruction that issues the write
2546 * command. Then we need
2547 * to directly jump to the micro-instruction that sends out the data
2549 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2550 * (2 and 3). One jump-counter (0) is used to perform multiple
2551 * write-read operations.
2552 * one counter left to issue this command in "multiple-group" mode
2555 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2557 if (rw_wl_nop_cycles == -1) {
2559 * CNTR 2 - We want to execute the special write operation that
2560 * turns on DQS right away and then skip directly to the
2561 * instruction that sends out the data. We set the counter to a
2562 * large number so that the jump is always taken.
2564 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2566 /* CNTR 3 - Not used */
2568 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2569 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2570 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2571 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2572 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2574 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2575 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2576 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2577 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2578 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2580 } else if (rw_wl_nop_cycles == 0) {
2582 * CNTR 2 - We want to skip the NOP operation and go straight
2583 * to the DQS enable instruction. We set the counter to a large
2584 * number so that the jump is always taken.
2586 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2588 /* CNTR 3 - Not used */
2590 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2591 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2592 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2594 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2595 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2596 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2600 * CNTR 2 - In this case we want to execute the next instruction
2601 * and NOT take the jump. So we set the counter to 0. The jump
2602 * address doesn't count.
2604 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2605 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2608 * CNTR 3 - Set the nop counter to the number of cycles we
2609 * need to loop for, minus 1.
2611 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2613 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2614 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2615 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2617 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2618 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2619 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2623 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2624 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2626 if (quick_write_mode)
2627 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2629 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2631 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2634 * CNTR 1 - This is used to ensure enough time elapses
2635 * for read data to come back.
2637 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2640 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2641 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2643 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2644 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2647 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2648 writel(mcc_instruction, addr + (group << 2));
2651 /* Test writes, can check for a single bit pass or multiple bit pass */
2652 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2653 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2654 uint32_t *bit_chk, uint32_t all_ranks)
2657 uint32_t correct_mask_vg;
2658 uint32_t tmp_bit_chk;
2660 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2661 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2662 uint32_t addr_rw_mgr;
2663 uint32_t base_rw_mgr;
2665 *bit_chk = param->write_correct_mask;
2666 correct_mask_vg = param->write_correct_mask_vg;
2668 for (r = rank_bgn; r < rank_end; r++) {
2669 if (param->skip_ranks[r]) {
2670 /* request to skip the rank */
2675 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2678 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2679 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2680 /* reset the fifos to get pointers to known state */
2681 writel(0, &phy_mgr_cmd->fifo_reset);
2683 tmp_bit_chk = tmp_bit_chk <<
2684 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2685 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2686 rw_mgr_mem_calibrate_write_test_issue(write_group *
2687 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2690 base_rw_mgr = readl(addr_rw_mgr);
2691 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2695 *bit_chk &= tmp_bit_chk;
2699 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2700 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2701 %u => %lu", write_group, use_dm,
2702 *bit_chk, param->write_correct_mask,
2703 (long unsigned int)(*bit_chk ==
2704 param->write_correct_mask));
2705 return *bit_chk == param->write_correct_mask;
2707 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2708 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2709 write_group, use_dm, *bit_chk);
2710 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2711 (long unsigned int)(*bit_chk != 0));
2712 return *bit_chk != 0x00;
2717 * center all windows. do per-bit-deskew to possibly increase size of
2720 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2721 uint32_t write_group, uint32_t test_bgn)
2723 uint32_t i, p, min_index;
2726 * Store these as signed since there are comparisons with
2730 uint32_t sticky_bit_chk;
2731 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2732 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2734 int32_t mid_min, orig_mid_min;
2735 int32_t new_dqs, start_dqs, shift_dq;
2736 int32_t dq_margin, dqs_margin, dm_margin;
2738 uint32_t temp_dq_out1_delay;
2741 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2745 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2746 start_dqs = readl(addr +
2747 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2749 /* per-bit deskew */
2752 * set the left and right edge of each bit to an illegal value
2753 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2756 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2757 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2758 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2761 /* Search for the left edge of the window for each bit */
2762 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2763 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2765 writel(0, &sdr_scc_mgr->update);
2768 * Stop searching when the read test doesn't pass AND when
2769 * we've seen a passing read on every bit.
2771 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2772 0, PASS_ONE_BIT, &bit_chk, 0);
2773 sticky_bit_chk = sticky_bit_chk | bit_chk;
2774 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2775 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2776 == %u && %u [bit_chk= %u ]\n",
2777 d, sticky_bit_chk, param->write_correct_mask,
2783 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2786 * Remember a passing test as the
2792 * If a left edge has not been seen
2793 * yet, then a future passing test will
2794 * mark this edge as the right edge.
2797 IO_IO_OUT1_DELAY_MAX + 1) {
2798 right_edge[i] = -(d + 1);
2801 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2802 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2803 (int)(bit_chk & 1), i, left_edge[i]);
2804 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2806 bit_chk = bit_chk >> 1;
2811 /* Reset DQ delay chains to 0 */
2812 scc_mgr_apply_group_dq_out1_delay(0);
2814 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2815 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2816 %d right_edge[%u]: %d\n", __func__, __LINE__,
2817 i, left_edge[i], i, right_edge[i]);
2820 * Check for cases where we haven't found the left edge,
2821 * which makes our assignment of the the right edge invalid.
2822 * Reset it to the illegal value.
2824 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2825 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2826 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2827 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2828 right_edge[%u]: %d\n", __func__, __LINE__,
2833 * Reset sticky bit (except for bits where we have
2834 * seen the left edge).
2836 sticky_bit_chk = sticky_bit_chk << 1;
2837 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2838 sticky_bit_chk = sticky_bit_chk | 1;
2844 /* Search for the right edge of the window for each bit */
2845 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2846 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2849 writel(0, &sdr_scc_mgr->update);
2852 * Stop searching when the read test doesn't pass AND when
2853 * we've seen a passing read on every bit.
2855 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2856 0, PASS_ONE_BIT, &bit_chk, 0);
2858 sticky_bit_chk = sticky_bit_chk | bit_chk;
2859 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2861 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2862 %u && %u\n", d, sticky_bit_chk,
2863 param->write_correct_mask, stop);
2867 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2869 /* d = 0 failed, but it passed when
2870 testing the left edge, so it must be
2871 marginal, set it to -1 */
2872 if (right_edge[i] ==
2873 IO_IO_OUT1_DELAY_MAX + 1 &&
2875 IO_IO_OUT1_DELAY_MAX + 1) {
2882 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2885 * Remember a passing test as
2892 * If a right edge has not
2893 * been seen yet, then a future
2894 * passing test will mark this
2895 * edge as the left edge.
2897 if (right_edge[i] ==
2898 IO_IO_OUT1_DELAY_MAX + 1)
2899 left_edge[i] = -(d + 1);
2902 * d = 0 failed, but it passed
2903 * when testing the left edge,
2904 * so it must be marginal, set
2907 if (right_edge[i] ==
2908 IO_IO_OUT1_DELAY_MAX + 1 &&
2910 IO_IO_OUT1_DELAY_MAX + 1)
2913 * If a right edge has not been
2914 * seen yet, then a future
2915 * passing test will mark this
2916 * edge as the left edge.
2918 else if (right_edge[i] ==
2919 IO_IO_OUT1_DELAY_MAX +
2921 left_edge[i] = -(d + 1);
2924 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2925 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2926 (int)(bit_chk & 1), i, left_edge[i]);
2927 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2929 bit_chk = bit_chk >> 1;
2934 /* Check that all bits have a window */
2935 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2936 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2937 %d right_edge[%u]: %d", __func__, __LINE__,
2938 i, left_edge[i], i, right_edge[i]);
2939 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2940 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2941 set_failing_group_stage(test_bgn + i,
2943 CAL_SUBSTAGE_WRITES_CENTER);
2948 /* Find middle of window for each DQ bit */
2949 mid_min = left_edge[0] - right_edge[0];
2951 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2952 mid = left_edge[i] - right_edge[i];
2953 if (mid < mid_min) {
2960 * -mid_min/2 represents the amount that we need to move DQS.
2961 * If mid_min is odd and positive we'll need to add one to
2962 * make sure the rounding in further calculations is correct
2963 * (always bias to the right), so just add 1 for all positive values.
2967 mid_min = mid_min / 2;
2968 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2971 /* Determine the amount we can change DQS (which is -mid_min) */
2972 orig_mid_min = mid_min;
2973 new_dqs = start_dqs;
2975 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2976 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2977 /* Initialize data for export structures */
2978 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2979 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2981 /* add delay to bring centre of all DQ windows to the same "level" */
2982 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2983 /* Use values before divide by 2 to reduce round off error */
2984 shift_dq = (left_edge[i] - right_edge[i] -
2985 (left_edge[min_index] - right_edge[min_index]))/2 +
2986 (orig_mid_min - mid_min);
2988 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2989 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2991 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2992 temp_dq_out1_delay = readl(addr + (i << 2));
2993 if (shift_dq + (int32_t)temp_dq_out1_delay >
2994 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2995 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2996 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2997 shift_dq = -(int32_t)temp_dq_out1_delay;
2999 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
3001 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
3004 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
3005 left_edge[i] - shift_dq + (-mid_min),
3006 right_edge[i] + shift_dq - (-mid_min));
3007 /* To determine values for export structures */
3008 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
3009 dq_margin = left_edge[i] - shift_dq + (-mid_min);
3011 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
3012 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
3016 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3017 writel(0, &sdr_scc_mgr->update);
3020 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3023 * set the left and right edge of each bit to an illegal value,
3024 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3026 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3027 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3028 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3029 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3030 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
3031 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
3032 int32_t win_best = 0;
3034 /* Search for the/part of the window with DM shift */
3035 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3036 scc_mgr_apply_group_dm_out1_delay(d);
3037 writel(0, &sdr_scc_mgr->update);
3039 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3040 PASS_ALL_BITS, &bit_chk,
3042 /* USE Set current end of the window */
3045 * If a starting edge of our window has not been seen
3046 * this is our current start of the DM window.
3048 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3052 * If current window is bigger than best seen.
3053 * Set best seen to be current window.
3055 if ((end_curr-bgn_curr+1) > win_best) {
3056 win_best = end_curr-bgn_curr+1;
3057 bgn_best = bgn_curr;
3058 end_best = end_curr;
3061 /* We just saw a failing test. Reset temp edge */
3062 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3063 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3068 /* Reset DM delay chains to 0 */
3069 scc_mgr_apply_group_dm_out1_delay(0);
3072 * Check to see if the current window nudges up aganist 0 delay.
3073 * If so we need to continue the search by shifting DQS otherwise DQS
3074 * search begins as a new search. */
3075 if (end_curr != 0) {
3076 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3077 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3080 /* Search for the/part of the window with DQS shifts */
3081 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3083 * Note: This only shifts DQS, so are we limiting ourselve to
3084 * width of DQ unnecessarily.
3086 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3089 writel(0, &sdr_scc_mgr->update);
3090 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3091 PASS_ALL_BITS, &bit_chk,
3093 /* USE Set current end of the window */
3096 * If a beginning edge of our window has not been seen
3097 * this is our current begin of the DM window.
3099 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3103 * If current window is bigger than best seen. Set best
3104 * seen to be current window.
3106 if ((end_curr-bgn_curr+1) > win_best) {
3107 win_best = end_curr-bgn_curr+1;
3108 bgn_best = bgn_curr;
3109 end_best = end_curr;
3112 /* We just saw a failing test. Reset temp edge */
3113 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3114 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3116 /* Early exit optimization: if ther remaining delay
3117 chain space is less than already seen largest window
3120 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3126 /* assign left and right edge for cal and reporting; */
3127 left_edge[0] = -1*bgn_best;
3128 right_edge[0] = end_best;
3130 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3131 __LINE__, left_edge[0], right_edge[0]);
3133 /* Move DQS (back to orig) */
3134 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3138 /* Find middle of window for the DM bit */
3139 mid = (left_edge[0] - right_edge[0]) / 2;
3141 /* only move right, since we are not moving DQS/DQ */
3145 /* dm_marign should fail if we never find a window */
3149 dm_margin = left_edge[0] - mid;
3151 scc_mgr_apply_group_dm_out1_delay(mid);
3152 writel(0, &sdr_scc_mgr->update);
3154 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3155 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3156 right_edge[0], mid, dm_margin);
3158 gbl->fom_out += dq_margin + dqs_margin;
3160 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3161 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3162 dq_margin, dqs_margin, dm_margin);
3165 * Do not remove this line as it makes sure all of our
3166 * decisions have been applied.
3168 writel(0, &sdr_scc_mgr->update);
3169 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3172 /* calibrate the write operations */
3173 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3176 /* update info for sims */
3177 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3179 reg_file_set_stage(CAL_STAGE_WRITES);
3180 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3182 reg_file_set_group(g);
3184 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3185 set_failing_group_stage(g, CAL_STAGE_WRITES,
3186 CAL_SUBSTAGE_WRITES_CENTER);
3194 * mem_precharge_and_activate() - Precharge all banks and activate
3196 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3198 static void mem_precharge_and_activate(void)
3202 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3203 /* Test if the rank should be skipped. */
3204 if (param->skip_ranks[r])
3208 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3210 /* Precharge all banks. */
3211 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3212 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3214 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3215 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3216 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3218 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3219 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3220 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3222 /* Activate rows. */
3223 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3224 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3229 * mem_init_latency() - Configure memory RLAT and WLAT settings
3231 * Configure memory RLAT and WLAT parameters.
3233 static void mem_init_latency(void)
3236 * For AV/CV, LFIFO is hardened and always runs at full rate
3237 * so max latency in AFI clocks, used here, is correspondingly
3240 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3243 debug("%s:%d\n", __func__, __LINE__);
3246 * Read in write latency.
3247 * WL for Hard PHY does not include additive latency.
3249 wlat = readl(&data_mgr->t_wl_add);
3250 wlat += readl(&data_mgr->mem_t_add);
3252 gbl->rw_wl_nop_cycles = wlat - 1;
3254 /* Read in readl latency. */
3255 rlat = readl(&data_mgr->t_rl_add);
3257 /* Set a pretty high read latency initially. */
3258 gbl->curr_read_lat = rlat + 16;
3259 if (gbl->curr_read_lat > max_latency)
3260 gbl->curr_read_lat = max_latency;
3262 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3264 /* Advertise write latency. */
3265 writel(wlat, &phy_mgr_cfg->afi_wlat);
3269 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3271 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3273 static void mem_skip_calibrate(void)
3275 uint32_t vfifo_offset;
3278 debug("%s:%d\n", __func__, __LINE__);
3279 /* Need to update every shadow register set used by the interface */
3280 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3281 r += NUM_RANKS_PER_SHADOW_REG) {
3283 * Set output phase alignment settings appropriate for
3286 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3287 scc_mgr_set_dqs_en_phase(i, 0);
3288 #if IO_DLL_CHAIN_LENGTH == 6
3289 scc_mgr_set_dqdqs_output_phase(i, 6);
3291 scc_mgr_set_dqdqs_output_phase(i, 7);
3296 * Write data arrives to the I/O two cycles before write
3297 * latency is reached (720 deg).
3298 * -> due to bit-slip in a/c bus
3299 * -> to allow board skew where dqs is longer than ck
3300 * -> how often can this happen!?
3301 * -> can claim back some ptaps for high freq
3302 * support if we can relax this, but i digress...
3304 * The write_clk leads mem_ck by 90 deg
3305 * The minimum ptap of the OPA is 180 deg
3306 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3307 * The write_clk is always delayed by 2 ptaps
3309 * Hence, to make DQS aligned to CK, we need to delay
3311 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3313 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3314 * gives us the number of ptaps, which simplies to:
3316 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3318 scc_mgr_set_dqdqs_output_phase(i,
3319 1.25 * IO_DLL_CHAIN_LENGTH - 2);
3321 writel(0xff, &sdr_scc_mgr->dqs_ena);
3322 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3324 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3325 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3326 SCC_MGR_GROUP_COUNTER_OFFSET);
3328 writel(0xff, &sdr_scc_mgr->dq_ena);
3329 writel(0xff, &sdr_scc_mgr->dm_ena);
3330 writel(0, &sdr_scc_mgr->update);
3333 /* Compensate for simulation model behaviour */
3334 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3335 scc_mgr_set_dqs_bus_in_delay(i, 10);
3336 scc_mgr_load_dqs(i);
3338 writel(0, &sdr_scc_mgr->update);
3341 * ArriaV has hard FIFOs that can only be initialized by incrementing
3344 vfifo_offset = CALIB_VFIFO_OFFSET;
3345 for (j = 0; j < vfifo_offset; j++)
3346 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3347 writel(0, &phy_mgr_cmd->fifo_reset);
3350 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3351 * setting from generation-time constant.
3353 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3354 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3358 * mem_calibrate() - Memory calibration entry point.
3360 * Perform memory calibration.
3362 static uint32_t mem_calibrate(void)
3365 uint32_t rank_bgn, sr;
3366 uint32_t write_group, write_test_bgn;
3367 uint32_t read_group, read_test_bgn;
3368 uint32_t run_groups, current_run;
3369 uint32_t failing_groups = 0;
3370 uint32_t group_failed = 0;
3372 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3373 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3375 debug("%s:%d\n", __func__, __LINE__);
3377 /* Initialize the data settings */
3378 gbl->error_substage = CAL_SUBSTAGE_NIL;
3379 gbl->error_stage = CAL_STAGE_NIL;
3380 gbl->error_group = 0xff;
3384 /* Initialize WLAT and RLAT. */
3387 /* Initialize bit slips. */
3388 mem_precharge_and_activate();
3390 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3391 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3392 SCC_MGR_GROUP_COUNTER_OFFSET);
3393 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3395 scc_mgr_set_hhp_extras();
3397 scc_set_bypass_mode(i);
3400 /* Calibration is skipped. */
3401 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3403 * Set VFIFO and LFIFO to instant-on settings in skip
3406 mem_skip_calibrate();
3409 * Do not remove this line as it makes sure all of our
3410 * decisions have been applied.
3412 writel(0, &sdr_scc_mgr->update);
3416 /* Calibration is not skipped. */
3417 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3419 * Zero all delay chain/phase settings for all
3420 * groups and all shadow register sets.
3424 run_groups = ~param->skip_groups;
3426 for (write_group = 0, write_test_bgn = 0; write_group
3427 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3428 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3430 /* Initialize the group failure */
3433 current_run = run_groups & ((1 <<
3434 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3435 run_groups = run_groups >>
3436 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3438 if (current_run == 0)
3441 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3442 SCC_MGR_GROUP_COUNTER_OFFSET);
3443 scc_mgr_zero_group(write_group, 0);
3445 for (read_group = write_group * rwdqs_ratio,
3447 read_group < (write_group + 1) * rwdqs_ratio;
3449 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3450 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3453 /* Calibrate the VFIFO */
3454 if (rw_mgr_mem_calibrate_vfifo(read_group,
3458 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3461 /* The group failed, we're done. */
3465 /* Calibrate the output side */
3466 for (rank_bgn = 0, sr = 0;
3467 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3468 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3469 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3472 /* Not needed in quick mode! */
3473 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3477 * Determine if this set of ranks
3478 * should be skipped entirely.
3480 if (param->skip_shadow_regs[sr])
3483 /* Calibrate WRITEs */
3484 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3485 write_group, write_test_bgn))
3489 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3493 /* Some group failed, we're done. */
3497 for (read_group = write_group * rwdqs_ratio,
3499 read_group < (write_group + 1) * rwdqs_ratio;
3501 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3502 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3505 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3509 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3512 /* The group failed, we're done. */
3516 /* No group failed, continue as usual. */
3519 grp_failed: /* A group failed, increment the counter. */
3524 * USER If there are any failing groups then report
3527 if (failing_groups != 0)
3530 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3534 * If we're skipping groups as part of debug,
3535 * don't calibrate LFIFO.
3537 if (param->skip_groups != 0)
3540 /* Calibrate the LFIFO */
3541 if (!rw_mgr_mem_calibrate_lfifo())
3546 * Do not remove this line as it makes sure all of our decisions
3547 * have been applied.
3549 writel(0, &sdr_scc_mgr->update);
3554 * run_mem_calibrate() - Perform memory calibration
3556 * This function triggers the entire memory calibration procedure.
3558 static int run_mem_calibrate(void)
3562 debug("%s:%d\n", __func__, __LINE__);
3564 /* Reset pass/fail status shown on afi_cal_success/fail */
3565 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3567 /* Stop tracking manager. */
3568 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3570 phy_mgr_initialize();
3571 rw_mgr_mem_initialize();
3573 /* Perform the actual memory calibration. */
3574 pass = mem_calibrate();
3576 mem_precharge_and_activate();
3577 writel(0, &phy_mgr_cmd->fifo_reset);
3580 rw_mgr_mem_handoff();
3582 * In Hard PHY this is a 2-bit control:
3584 * 1: DDIO Mux Select
3586 writel(0x2, &phy_mgr_cfg->mux_sel);
3588 /* Start tracking manager. */
3589 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3595 * debug_mem_calibrate() - Report result of memory calibration
3596 * @pass: Value indicating whether calibration passed or failed
3598 * This function reports the results of the memory calibration
3599 * and writes debug information into the register file.
3601 static void debug_mem_calibrate(int pass)
3603 uint32_t debug_info;
3606 printf("%s: CALIBRATION PASSED\n", __FILE__);
3611 if (gbl->fom_in > 0xff)
3614 if (gbl->fom_out > 0xff)
3615 gbl->fom_out = 0xff;
3617 /* Update the FOM in the register file */
3618 debug_info = gbl->fom_in;
3619 debug_info |= gbl->fom_out << 8;
3620 writel(debug_info, &sdr_reg_file->fom);
3622 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3623 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3625 printf("%s: CALIBRATION FAILED\n", __FILE__);
3627 debug_info = gbl->error_stage;
3628 debug_info |= gbl->error_substage << 8;
3629 debug_info |= gbl->error_group << 16;
3631 writel(debug_info, &sdr_reg_file->failing_stage);
3632 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3633 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3635 /* Update the failing group/stage in the register file */
3636 debug_info = gbl->error_stage;
3637 debug_info |= gbl->error_substage << 8;
3638 debug_info |= gbl->error_group << 16;
3639 writel(debug_info, &sdr_reg_file->failing_stage);
3642 printf("%s: Calibration complete\n", __FILE__);
3646 * hc_initialize_rom_data() - Initialize ROM data
3648 * Initialize ROM data.
3650 static void hc_initialize_rom_data(void)
3654 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3655 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3656 writel(inst_rom_init[i], addr + (i << 2));
3658 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3659 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3660 writel(ac_rom_init[i], addr + (i << 2));
3664 * initialize_reg_file() - Initialize SDR register file
3666 * Initialize SDR register file.
3668 static void initialize_reg_file(void)
3670 /* Initialize the register file with the correct data */
3671 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3672 writel(0, &sdr_reg_file->debug_data_addr);
3673 writel(0, &sdr_reg_file->cur_stage);
3674 writel(0, &sdr_reg_file->fom);
3675 writel(0, &sdr_reg_file->failing_stage);
3676 writel(0, &sdr_reg_file->debug1);
3677 writel(0, &sdr_reg_file->debug2);
3681 * initialize_hps_phy() - Initialize HPS PHY
3683 * Initialize HPS PHY.
3685 static void initialize_hps_phy(void)
3689 * Tracking also gets configured here because it's in the
3692 uint32_t trk_sample_count = 7500;
3693 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3695 * Format is number of outer loops in the 16 MSB, sample
3700 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3701 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3702 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3703 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3704 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3705 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3707 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3708 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3710 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3711 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3713 writel(reg, &sdr_ctrl->phy_ctrl0);
3716 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3718 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3719 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3720 trk_long_idle_sample_count);
3721 writel(reg, &sdr_ctrl->phy_ctrl1);
3724 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3725 trk_long_idle_sample_count >>
3726 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3727 writel(reg, &sdr_ctrl->phy_ctrl2);
3731 * initialize_tracking() - Initialize tracking
3733 * Initialize the register file with usable initial data.
3735 static void initialize_tracking(void)
3738 * Initialize the register file with the correct data.
3739 * Compute usable version of value in case we skip full
3740 * computation later.
3742 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3743 &sdr_reg_file->dtaps_per_ptap);
3745 /* trk_sample_count */
3746 writel(7500, &sdr_reg_file->trk_sample_count);
3748 /* longidle outer loop [15:0] */
3749 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3752 * longidle sample count [31:24]
3753 * trfc, worst case of 933Mhz 4Gb [23:16]
3754 * trcd, worst case [15:8]
3757 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3758 &sdr_reg_file->delays);
3761 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3762 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3763 &sdr_reg_file->trk_rw_mgr_addr);
3765 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3766 &sdr_reg_file->trk_read_dqs_width);
3769 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3770 &sdr_reg_file->trk_rfsh);
3773 int sdram_calibration_full(void)
3775 struct param_type my_param;
3776 struct gbl_type my_gbl;
3779 memset(&my_param, 0, sizeof(my_param));
3780 memset(&my_gbl, 0, sizeof(my_gbl));
3785 /* Set the calibration enabled by default */
3786 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3788 * Only sweep all groups (regardless of fail state) by default
3789 * Set enabled read test by default.
3791 #if DISABLE_GUARANTEED_READ
3792 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3794 /* Initialize the register file */
3795 initialize_reg_file();
3797 /* Initialize any PHY CSR */
3798 initialize_hps_phy();
3800 scc_mgr_initialize();
3802 initialize_tracking();
3804 printf("%s: Preparing to start memory calibration\n", __FILE__);
3806 debug("%s:%d\n", __func__, __LINE__);
3807 debug_cond(DLEVEL == 1,
3808 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3809 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3810 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3811 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3812 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3813 debug_cond(DLEVEL == 1,
3814 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3815 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3816 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3817 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3818 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3819 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3820 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3821 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3822 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3823 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3824 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3825 IO_IO_OUT2_DELAY_MAX);
3826 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3827 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3829 hc_initialize_rom_data();
3831 /* update info for sims */
3832 reg_file_set_stage(CAL_STAGE_NIL);
3833 reg_file_set_group(0);
3836 * Load global needed for those actions that require
3837 * some dynamic calibration support.
3839 dyn_calib_steps = STATIC_CALIB_STEPS;
3841 * Load global to allow dynamic selection of delay loop settings
3842 * based on calibration mode.
3844 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3845 skip_delay_mask = 0xff;
3847 skip_delay_mask = 0x0;
3849 pass = run_mem_calibrate();
3850 debug_mem_calibrate(pass);