2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
12 #include "sequencer_auto.h"
13 #include "sequencer_auto_ac_init.h"
14 #include "sequencer_auto_inst_init.h"
15 #include "sequencer_defines.h"
17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
18 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
21 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
23 static struct socfpga_sdr_reg_file *sdr_reg_file =
24 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
27 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
30 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
33 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
35 static struct socfpga_data_mgr *data_mgr =
36 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
38 static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
56 #define STATIC_IN_RTL_SIM 0
57 #define STATIC_SKIP_DELAY_LOOPS 0
59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
62 /* calibration steps requested by the rtl */
63 uint16_t dyn_calib_steps;
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
70 * The mask is set to include all bits when not-skipping, but is
74 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
80 struct param_type *param;
81 uint32_t curr_shadow_reg;
83 static void set_failing_group_stage(uint32_t group, uint32_t stage,
87 * Only set the global stage if there was not been any other
90 if (gbl->error_stage == CAL_STAGE_NIL) {
91 gbl->error_substage = substage;
92 gbl->error_stage = stage;
93 gbl->error_group = group;
97 static void reg_file_set_group(u16 set_group)
99 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
102 static void reg_file_set_stage(u8 set_stage)
104 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
107 static void reg_file_set_sub_stage(u8 set_sub_stage)
109 set_sub_stage &= 0xff;
110 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
114 * phy_mgr_initialize() - Initialize PHY Manager
116 * Initialize PHY Manager.
118 static void phy_mgr_initialize(void)
122 debug("%s:%d\n", __func__, __LINE__);
123 /* Calibration has control over path to memory */
125 * In Hard PHY this is a 2-bit control:
129 writel(0x3, &phy_mgr_cfg->mux_sel);
131 /* USER memory clock is not stable we begin initialization */
132 writel(0, &phy_mgr_cfg->reset_mem_stbl);
134 /* USER calibration status all set to zero */
135 writel(0, &phy_mgr_cfg->cal_status);
137 writel(0, &phy_mgr_cfg->cal_debug_info);
139 /* Init params only if we do NOT skip calibration. */
140 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
143 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
144 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
145 param->read_correct_mask_vg = (1 << ratio) - 1;
146 param->write_correct_mask_vg = (1 << ratio) - 1;
147 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
148 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
149 ratio = RW_MGR_MEM_DATA_WIDTH /
150 RW_MGR_MEM_DATA_MASK_WIDTH;
151 param->dm_correct_mask = (1 << ratio) - 1;
155 * set_rank_and_odt_mask() - Set Rank and ODT mask
157 * @odt_mode: ODT mode, OFF or READ_WRITE
159 * Set Rank and ODT mask (On-Die Termination).
161 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
167 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
170 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
171 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
173 /* Read: ODT = 0 ; Write: ODT = 1 */
177 case 2: /* 2 Ranks */
178 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
180 * - Dual-Slot , Single-Rank (1 CS per DIMM)
182 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
184 * Since MEM_NUMBER_OF_RANKS is 2, they
185 * are both single rank with 2 CS each
186 * (special for RDIMM).
188 * Read: Turn on ODT on the opposite rank
189 * Write: Turn on ODT on all ranks
191 odt_mask_0 = 0x3 & ~(1 << rank);
195 * - Single-Slot , Dual-Rank (2 CS per DIMM)
197 * Read: Turn on ODT off on all ranks
198 * Write: Turn on ODT on active rank
201 odt_mask_1 = 0x3 & (1 << rank);
204 case 4: /* 4 Ranks */
206 * ----------+-----------------------+
208 * Read From +-----------------------+
209 * Rank | 3 | 2 | 1 | 0 |
210 * ----------+-----+-----+-----+-----+
211 * 0 | 0 | 1 | 0 | 0 |
212 * 1 | 1 | 0 | 0 | 0 |
213 * 2 | 0 | 0 | 0 | 1 |
214 * 3 | 0 | 0 | 1 | 0 |
215 * ----------+-----+-----+-----+-----+
218 * ----------+-----------------------+
220 * Write To +-----------------------+
221 * Rank | 3 | 2 | 1 | 0 |
222 * ----------+-----+-----+-----+-----+
223 * 0 | 0 | 1 | 0 | 1 |
224 * 1 | 1 | 0 | 1 | 0 |
225 * 2 | 0 | 1 | 0 | 1 |
226 * 3 | 1 | 0 | 1 | 0 |
227 * ----------+-----+-----+-----+-----+
251 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
252 ((0xFF & odt_mask_0) << 8) |
253 ((0xFF & odt_mask_1) << 16);
254 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
255 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
259 * scc_mgr_set() - Set SCC Manager register
260 * @off: Base offset in SCC Manager space
261 * @grp: Read/Write group
262 * @val: Value to be set
264 * This function sets the SCC Manager (Scan Chain Control Manager) register.
266 static void scc_mgr_set(u32 off, u32 grp, u32 val)
268 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
272 * scc_mgr_initialize() - Initialize SCC Manager registers
274 * Initialize SCC Manager registers.
276 static void scc_mgr_initialize(void)
279 * Clear register file for HPS. 16 (2^4) is the size of the
280 * full register file in the scc mgr:
281 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
282 * MEM_IF_READ_DQS_WIDTH - 1);
286 for (i = 0; i < 16; i++) {
287 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
288 __func__, __LINE__, i);
289 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
293 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
295 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
298 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
300 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
303 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
305 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
308 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
310 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
313 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
315 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
319 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
321 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
324 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
326 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
329 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
331 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
335 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
337 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
338 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
342 /* load up dqs config settings */
343 static void scc_mgr_load_dqs(uint32_t dqs)
345 writel(dqs, &sdr_scc_mgr->dqs_ena);
348 /* load up dqs io config settings */
349 static void scc_mgr_load_dqs_io(void)
351 writel(0, &sdr_scc_mgr->dqs_io_ena);
354 /* load up dq config settings */
355 static void scc_mgr_load_dq(uint32_t dq_in_group)
357 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
360 /* load up dm config settings */
361 static void scc_mgr_load_dm(uint32_t dm)
363 writel(dm, &sdr_scc_mgr->dm_ena);
367 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
368 * @off: Base offset in SCC Manager space
369 * @grp: Read/Write group
370 * @val: Value to be set
371 * @update: If non-zero, trigger SCC Manager update for all ranks
373 * This function sets the SCC Manager (Scan Chain Control Manager) register
374 * and optionally triggers the SCC update for all ranks.
376 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
381 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
382 r += NUM_RANKS_PER_SHADOW_REG) {
383 scc_mgr_set(off, grp, val);
385 if (update || (r == 0)) {
386 writel(grp, &sdr_scc_mgr->dqs_ena);
387 writel(0, &sdr_scc_mgr->update);
392 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
395 * USER although the h/w doesn't support different phases per
396 * shadow register, for simplicity our scc manager modeling
397 * keeps different phase settings per shadow reg, and it's
398 * important for us to keep them in sync to match h/w.
399 * for efficiency, the scan chain update should occur only
402 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
403 read_group, phase, 0);
406 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
410 * USER although the h/w doesn't support different phases per
411 * shadow register, for simplicity our scc manager modeling
412 * keeps different phase settings per shadow reg, and it's
413 * important for us to keep them in sync to match h/w.
414 * for efficiency, the scan chain update should occur only
417 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
418 write_group, phase, 0);
421 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
425 * In shadow register mode, the T11 settings are stored in
426 * registers in the core, which are updated by the DQS_ENA
427 * signals. Not issuing the SCC_MGR_UPD command allows us to
428 * save lots of rank switching overhead, by calling
429 * select_shadow_regs_for_update with update_scan_chains
432 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
433 read_group, delay, 1);
434 writel(0, &sdr_scc_mgr->update);
438 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
439 * @write_group: Write group
440 * @delay: Delay value
442 * This function sets the OCT output delay in SCC manager.
444 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
446 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
447 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
448 const int base = write_group * ratio;
451 * Load the setting in the SCC manager
452 * Although OCT affects only write data, the OCT delay is controlled
453 * by the DQS logic block which is instantiated once per read group.
454 * For protocols where a write group consists of multiple read groups,
455 * the setting must be set multiple times.
457 for (i = 0; i < ratio; i++)
458 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
462 * scc_mgr_set_hhp_extras() - Set HHP extras.
464 * Load the fixed setting in the SCC manager HHP extras.
466 static void scc_mgr_set_hhp_extras(void)
469 * Load the fixed setting in the SCC manager
470 * bits: 0:0 = 1'b1 - DQS bypass
471 * bits: 1:1 = 1'b1 - DQ bypass
472 * bits: 4:2 = 3'b001 - rfifo_mode
473 * bits: 6:5 = 2'b01 - rfifo clock_select
474 * bits: 7:7 = 1'b0 - separate gating from ungating setting
475 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
477 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
478 (1 << 2) | (1 << 1) | (1 << 0);
479 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
480 SCC_MGR_HHP_GLOBALS_OFFSET |
481 SCC_MGR_HHP_EXTRAS_OFFSET;
483 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
486 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
491 * scc_mgr_zero_all() - Zero all DQS config
493 * Zero all DQS config.
495 static void scc_mgr_zero_all(void)
500 * USER Zero all DQS config settings, across all groups and all
503 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
504 r += NUM_RANKS_PER_SHADOW_REG) {
505 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
507 * The phases actually don't exist on a per-rank basis,
508 * but there's no harm updating them several times, so
509 * let's keep the code simple.
511 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
512 scc_mgr_set_dqs_en_phase(i, 0);
513 scc_mgr_set_dqs_en_delay(i, 0);
516 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
517 scc_mgr_set_dqdqs_output_phase(i, 0);
518 /* Arria V/Cyclone V don't have out2. */
519 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
523 /* Multicast to all DQS group enables. */
524 writel(0xff, &sdr_scc_mgr->dqs_ena);
525 writel(0, &sdr_scc_mgr->update);
529 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
530 * @write_group: Write group
532 * Set bypass mode and trigger SCC update.
534 static void scc_set_bypass_mode(const u32 write_group)
536 /* Multicast to all DQ enables. */
537 writel(0xff, &sdr_scc_mgr->dq_ena);
538 writel(0xff, &sdr_scc_mgr->dm_ena);
540 /* Update current DQS IO enable. */
541 writel(0, &sdr_scc_mgr->dqs_io_ena);
543 /* Update the DQS logic. */
544 writel(write_group, &sdr_scc_mgr->dqs_ena);
547 writel(0, &sdr_scc_mgr->update);
551 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
552 * @write_group: Write group
554 * Load DQS settings for Write Group, do not trigger SCC update.
556 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
558 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
559 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
560 const int base = write_group * ratio;
563 * Load the setting in the SCC manager
564 * Although OCT affects only write data, the OCT delay is controlled
565 * by the DQS logic block which is instantiated once per read group.
566 * For protocols where a write group consists of multiple read groups,
567 * the setting must be set multiple times.
569 for (i = 0; i < ratio; i++)
570 writel(base + i, &sdr_scc_mgr->dqs_ena);
574 * scc_mgr_zero_group() - Zero all configs for a group
576 * Zero DQ, DM, DQS and OCT configs for a group.
578 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
582 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
583 r += NUM_RANKS_PER_SHADOW_REG) {
584 /* Zero all DQ config settings. */
585 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
586 scc_mgr_set_dq_out1_delay(i, 0);
588 scc_mgr_set_dq_in_delay(i, 0);
591 /* Multicast to all DQ enables. */
592 writel(0xff, &sdr_scc_mgr->dq_ena);
594 /* Zero all DM config settings. */
595 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
596 scc_mgr_set_dm_out1_delay(i, 0);
598 /* Multicast to all DM enables. */
599 writel(0xff, &sdr_scc_mgr->dm_ena);
601 /* Zero all DQS IO settings. */
603 scc_mgr_set_dqs_io_in_delay(0);
605 /* Arria V/Cyclone V don't have out2. */
606 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
607 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
608 scc_mgr_load_dqs_for_write_group(write_group);
610 /* Multicast to all DQS IO enables (only 1 in total). */
611 writel(0, &sdr_scc_mgr->dqs_io_ena);
613 /* Hit update to zero everything. */
614 writel(0, &sdr_scc_mgr->update);
619 * apply and load a particular input delay for the DQ pins in a group
620 * group_bgn is the index of the first dq pin (in the write group)
622 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
626 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
627 scc_mgr_set_dq_in_delay(p, delay);
633 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
634 * @delay: Delay value
636 * Apply and load a particular output delay for the DQ pins in a group.
638 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
642 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
643 scc_mgr_set_dq_out1_delay(i, delay);
648 /* apply and load a particular output delay for the DM pins in a group */
649 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
653 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
654 scc_mgr_set_dm_out1_delay(i, delay1);
660 /* apply and load delay on both DQS and OCT out1 */
661 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
664 scc_mgr_set_dqs_out1_delay(delay);
665 scc_mgr_load_dqs_io();
667 scc_mgr_set_oct_out1_delay(write_group, delay);
668 scc_mgr_load_dqs_for_write_group(write_group);
672 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
673 * @write_group: Write group
674 * @delay: Delay value
676 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
678 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
684 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
688 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
692 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
693 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
694 debug_cond(DLEVEL == 1,
695 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
696 __func__, __LINE__, write_group, delay, new_delay,
697 IO_IO_OUT2_DELAY_MAX,
698 new_delay - IO_IO_OUT2_DELAY_MAX);
699 new_delay -= IO_IO_OUT2_DELAY_MAX;
700 scc_mgr_set_dqs_out1_delay(new_delay);
703 scc_mgr_load_dqs_io();
706 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
707 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
708 debug_cond(DLEVEL == 1,
709 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
710 __func__, __LINE__, write_group, delay,
711 new_delay, IO_IO_OUT2_DELAY_MAX,
712 new_delay - IO_IO_OUT2_DELAY_MAX);
713 new_delay -= IO_IO_OUT2_DELAY_MAX;
714 scc_mgr_set_oct_out1_delay(write_group, new_delay);
717 scc_mgr_load_dqs_for_write_group(write_group);
721 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
722 * @write_group: Write group
723 * @delay: Delay value
725 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
728 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
733 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
734 r += NUM_RANKS_PER_SHADOW_REG) {
735 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
736 writel(0, &sdr_scc_mgr->update);
741 * set_jump_as_return() - Return instruction optimization
743 * Optimization used to recover some slots in ddr3 inst_rom could be
744 * applied to other protocols if we wanted to
746 static void set_jump_as_return(void)
749 * To save space, we replace return with jump to special shared
750 * RETURN instruction so we set the counter to large value so that
753 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
754 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
758 * should always use constants as argument to ensure all computations are
759 * performed at compile time
761 static void delay_for_n_mem_clocks(const uint32_t clocks)
768 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
771 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
772 /* scale (rounding up) to get afi clocks */
775 * Note, we don't bother accounting for being off a little bit
776 * because of a few extra instructions in outer loops
777 * Note, the loops have a test at the end, and do the test before
778 * the decrement, and so always perform the loop
779 * 1 time more than the counter value
781 if (afi_clocks == 0) {
783 } else if (afi_clocks <= 0x100) {
784 inner = afi_clocks-1;
787 } else if (afi_clocks <= 0x10000) {
789 outer = (afi_clocks-1) >> 8;
794 c_loop = (afi_clocks-1) >> 16;
798 * rom instructions are structured as follows:
800 * IDLE_LOOP2: jnz cntr0, TARGET_A
801 * IDLE_LOOP1: jnz cntr1, TARGET_B
804 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
805 * TARGET_B is set to IDLE_LOOP2 as well
807 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
808 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
810 * a little confusing, but it helps save precious space in the inst_rom
811 * and sequencer rom and keeps the delays more accurate and reduces
814 if (afi_clocks <= 0x100) {
815 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
816 &sdr_rw_load_mgr_regs->load_cntr1);
818 writel(RW_MGR_IDLE_LOOP1,
819 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
821 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
822 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
824 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
825 &sdr_rw_load_mgr_regs->load_cntr0);
827 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
828 &sdr_rw_load_mgr_regs->load_cntr1);
830 writel(RW_MGR_IDLE_LOOP2,
831 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
833 writel(RW_MGR_IDLE_LOOP2,
834 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
836 /* hack to get around compiler not being smart enough */
837 if (afi_clocks <= 0x10000) {
838 /* only need to run once */
839 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
840 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
843 writel(RW_MGR_IDLE_LOOP2,
844 SDR_PHYGRP_RWMGRGRP_ADDRESS |
845 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
846 } while (c_loop-- != 0);
849 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
853 * rw_mgr_mem_init_load_regs() - Load instruction registers
854 * @cntr0: Counter 0 value
855 * @cntr1: Counter 1 value
856 * @cntr2: Counter 2 value
857 * @jump: Jump instruction value
859 * Load instruction registers.
861 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
863 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
864 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
867 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
868 &sdr_rw_load_mgr_regs->load_cntr0);
869 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
870 &sdr_rw_load_mgr_regs->load_cntr1);
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
872 &sdr_rw_load_mgr_regs->load_cntr2);
874 /* Load jump address */
875 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
876 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
877 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
879 /* Execute count instruction */
880 writel(jump, grpaddr);
884 * rw_mgr_mem_load_user() - Load user calibration values
885 * @fin1: Final instruction 1
886 * @fin2: Final instruction 2
887 * @precharge: If 1, precharge the banks at the end
889 * Load user calibration values and optionally precharge the banks.
891 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
894 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
895 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
898 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
899 if (param->skip_ranks[r]) {
900 /* request to skip the rank */
905 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
907 /* precharge all banks ... */
909 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
912 * USER Use Mirror-ed commands for odd ranks if address
915 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
916 set_jump_as_return();
917 writel(RW_MGR_MRS2_MIRR, grpaddr);
918 delay_for_n_mem_clocks(4);
919 set_jump_as_return();
920 writel(RW_MGR_MRS3_MIRR, grpaddr);
921 delay_for_n_mem_clocks(4);
922 set_jump_as_return();
923 writel(RW_MGR_MRS1_MIRR, grpaddr);
924 delay_for_n_mem_clocks(4);
925 set_jump_as_return();
926 writel(fin1, grpaddr);
928 set_jump_as_return();
929 writel(RW_MGR_MRS2, grpaddr);
930 delay_for_n_mem_clocks(4);
931 set_jump_as_return();
932 writel(RW_MGR_MRS3, grpaddr);
933 delay_for_n_mem_clocks(4);
934 set_jump_as_return();
935 writel(RW_MGR_MRS1, grpaddr);
936 set_jump_as_return();
937 writel(fin2, grpaddr);
943 set_jump_as_return();
944 writel(RW_MGR_ZQCL, grpaddr);
946 /* tZQinit = tDLLK = 512 ck cycles */
947 delay_for_n_mem_clocks(512);
952 * rw_mgr_mem_initialize() - Initialize RW Manager
954 * Initialize RW Manager.
956 static void rw_mgr_mem_initialize(void)
958 debug("%s:%d\n", __func__, __LINE__);
960 /* The reset / cke part of initialization is broadcasted to all ranks */
961 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
962 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
965 * Here's how you load register for a loop
966 * Counters are located @ 0x800
967 * Jump address are located @ 0xC00
968 * For both, registers 0 to 3 are selected using bits 3 and 2, like
969 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
970 * I know this ain't pretty, but Avalon bus throws away the 2 least
974 /* Start with memory RESET activated */
979 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
980 * If a and b are the number of iteration in 2 nested loops
981 * it takes the following number of cycles to complete the operation:
982 * number_of_cycles = ((2 + n) * a + 2) * b
983 * where n is the number of instruction in the inner loop
984 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
987 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
989 RW_MGR_INIT_RESET_0_CKE_0);
991 /* Indicate that memory is stable. */
992 writel(1, &phy_mgr_cfg->reset_mem_stbl);
995 * transition the RESET to high
1000 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1001 * If a and b are the number of iteration in 2 nested loops
1002 * it takes the following number of cycles to complete the operation
1003 * number_of_cycles = ((2 + n) * a + 2) * b
1004 * where n is the number of instruction in the inner loop
1005 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1008 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1009 SEQ_TRESET_CNTR2_VAL,
1010 RW_MGR_INIT_RESET_1_CKE_0);
1012 /* Bring up clock enable. */
1014 /* tXRP < 250 ck cycles */
1015 delay_for_n_mem_clocks(250);
1017 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022 * At the end of calibration we have to program the user settings in, and
1023 * USER hand off the memory to the user.
1025 static void rw_mgr_mem_handoff(void)
1027 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1029 * USER need to wait tMOD (12CK or 15ns) time before issuing
1030 * other commands, but we will have plenty of NIOS cycles before
1031 * actual handoff so its okay.
1036 * issue write test command.
1037 * two variants are provided. one that just tests a write pattern and
1038 * another that tests datamask functionality.
1040 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
1043 uint32_t mcc_instruction;
1044 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
1045 ENABLE_SUPER_QUICK_CALIBRATION);
1046 uint32_t rw_wl_nop_cycles;
1050 * Set counter and jump addresses for the right
1051 * number of NOP cycles.
1052 * The number of supported NOP cycles can range from -1 to infinity
1053 * Three different cases are handled:
1055 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
1056 * mechanism will be used to insert the right number of NOPs
1058 * 2. For a number of NOP cycles equals to 0, the micro-instruction
1059 * issuing the write command will jump straight to the
1060 * micro-instruction that turns on DQS (for DDRx), or outputs write
1061 * data (for RLD), skipping
1062 * the NOP micro-instruction all together
1064 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
1065 * turned on in the same micro-instruction that issues the write
1066 * command. Then we need
1067 * to directly jump to the micro-instruction that sends out the data
1069 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
1070 * (2 and 3). One jump-counter (0) is used to perform multiple
1071 * write-read operations.
1072 * one counter left to issue this command in "multiple-group" mode
1075 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
1077 if (rw_wl_nop_cycles == -1) {
1079 * CNTR 2 - We want to execute the special write operation that
1080 * turns on DQS right away and then skip directly to the
1081 * instruction that sends out the data. We set the counter to a
1082 * large number so that the jump is always taken.
1084 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1086 /* CNTR 3 - Not used */
1088 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
1089 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
1090 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1091 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
1092 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1094 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
1095 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
1096 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1097 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
1098 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1100 } else if (rw_wl_nop_cycles == 0) {
1102 * CNTR 2 - We want to skip the NOP operation and go straight
1103 * to the DQS enable instruction. We set the counter to a large
1104 * number so that the jump is always taken.
1106 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1108 /* CNTR 3 - Not used */
1110 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
1111 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
1112 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1114 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
1115 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
1116 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1120 * CNTR 2 - In this case we want to execute the next instruction
1121 * and NOT take the jump. So we set the counter to 0. The jump
1122 * address doesn't count.
1124 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
1125 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1128 * CNTR 3 - Set the nop counter to the number of cycles we
1129 * need to loop for, minus 1.
1131 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
1133 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
1134 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
1135 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1137 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
1138 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
1139 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1143 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1144 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1146 if (quick_write_mode)
1147 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
1149 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
1151 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1154 * CNTR 1 - This is used to ensure enough time elapses
1155 * for read data to come back.
1157 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
1160 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
1161 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1163 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
1164 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1167 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1168 writel(mcc_instruction, addr + (group << 2));
1171 /* Test writes, can check for a single bit pass or multiple bit pass */
1172 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
1173 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
1174 uint32_t *bit_chk, uint32_t all_ranks)
1177 uint32_t correct_mask_vg;
1178 uint32_t tmp_bit_chk;
1180 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1181 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1182 uint32_t addr_rw_mgr;
1183 uint32_t base_rw_mgr;
1185 *bit_chk = param->write_correct_mask;
1186 correct_mask_vg = param->write_correct_mask_vg;
1188 for (r = rank_bgn; r < rank_end; r++) {
1189 if (param->skip_ranks[r]) {
1190 /* request to skip the rank */
1195 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1198 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
1199 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
1200 /* reset the fifos to get pointers to known state */
1201 writel(0, &phy_mgr_cmd->fifo_reset);
1203 tmp_bit_chk = tmp_bit_chk <<
1204 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
1205 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
1206 rw_mgr_mem_calibrate_write_test_issue(write_group *
1207 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
1210 base_rw_mgr = readl(addr_rw_mgr);
1211 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1215 *bit_chk &= tmp_bit_chk;
1219 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1220 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
1221 %u => %lu", write_group, use_dm,
1222 *bit_chk, param->write_correct_mask,
1223 (long unsigned int)(*bit_chk ==
1224 param->write_correct_mask));
1225 return *bit_chk == param->write_correct_mask;
1227 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1228 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
1229 write_group, use_dm, *bit_chk);
1230 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
1231 (long unsigned int)(*bit_chk != 0));
1232 return *bit_chk != 0x00;
1237 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1238 * @rank_bgn: Rank number
1239 * @group: Read/Write Group
1240 * @all_ranks: Test all ranks
1242 * Performs a guaranteed read on the patterns we are going to use during a
1243 * read test to ensure memory works.
1246 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1247 const u32 all_ranks)
1249 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1250 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1251 const u32 addr_offset =
1252 (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1253 const u32 rank_end = all_ranks ?
1254 RW_MGR_MEM_NUMBER_OF_RANKS :
1255 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1256 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1257 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1258 const u32 correct_mask_vg = param->read_correct_mask_vg;
1260 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1264 bit_chk = param->read_correct_mask;
1266 for (r = rank_bgn; r < rank_end; r++) {
1267 /* Request to skip the rank */
1268 if (param->skip_ranks[r])
1272 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1274 /* Load up a constant bursts of read commands */
1275 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1276 writel(RW_MGR_GUARANTEED_READ,
1277 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1279 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1280 writel(RW_MGR_GUARANTEED_READ_CONT,
1281 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1284 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1286 /* Reset the FIFOs to get pointers to known state. */
1287 writel(0, &phy_mgr_cmd->fifo_reset);
1288 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1289 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1290 writel(RW_MGR_GUARANTEED_READ,
1291 addr + addr_offset + (vg << 2));
1293 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1294 tmp_bit_chk <<= shift_ratio;
1295 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1298 bit_chk &= tmp_bit_chk;
1301 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1303 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1305 if (bit_chk != param->read_correct_mask)
1308 debug_cond(DLEVEL == 1,
1309 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1310 __func__, __LINE__, group, bit_chk,
1311 param->read_correct_mask, ret);
1317 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1318 * @rank_bgn: Rank number
1319 * @all_ranks: Test all ranks
1321 * Load up the patterns we are going to use during a read test.
1323 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1324 const int all_ranks)
1326 const u32 rank_end = all_ranks ?
1327 RW_MGR_MEM_NUMBER_OF_RANKS :
1328 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1331 debug("%s:%d\n", __func__, __LINE__);
1333 for (r = rank_bgn; r < rank_end; r++) {
1334 if (param->skip_ranks[r])
1335 /* request to skip the rank */
1339 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1341 /* Load up a constant bursts */
1342 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1344 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1345 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1347 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1349 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1350 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1352 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1354 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1355 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1357 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1359 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1360 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1362 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1363 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1366 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1370 * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
1371 * @rank_bgn: Rank number
1372 * @group: Read/Write group
1373 * @num_tries: Number of retries of the test
1374 * @all_correct: All bits must be correct in the mask
1375 * @bit_chk: Resulting bit mask after the test
1376 * @all_groups: Test all R/W groups
1377 * @all_ranks: Test all ranks
1379 * Try a read and see if it returns correct data back. Test has dummy reads
1380 * inserted into the mix used to align DQS enable. Test has more thorough
1381 * checks than the regular read test.
1384 rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
1385 const u32 num_tries, const u32 all_correct,
1387 const u32 all_groups, const u32 all_ranks)
1389 const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1390 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1391 const u32 quick_read_mode =
1392 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1393 ENABLE_SUPER_QUICK_CALIBRATION);
1394 u32 correct_mask_vg = param->read_correct_mask_vg;
1401 *bit_chk = param->read_correct_mask;
1403 for (r = rank_bgn; r < rank_end; r++) {
1404 if (param->skip_ranks[r])
1405 /* request to skip the rank */
1409 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1411 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1413 writel(RW_MGR_READ_B2B_WAIT1,
1414 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1416 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1417 writel(RW_MGR_READ_B2B_WAIT2,
1418 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1420 if (quick_read_mode)
1421 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1422 /* need at least two (1+1) reads to capture failures */
1423 else if (all_groups)
1424 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1426 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1428 writel(RW_MGR_READ_B2B,
1429 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1431 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1432 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1433 &sdr_rw_load_mgr_regs->load_cntr3);
1435 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1437 writel(RW_MGR_READ_B2B,
1438 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1441 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
1443 /* Reset the FIFOs to get pointers to known state. */
1444 writel(0, &phy_mgr_cmd->fifo_reset);
1445 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1446 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1449 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1450 RW_MGR_RUN_ALL_GROUPS_OFFSET;
1452 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1453 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1456 writel(RW_MGR_READ_B2B, addr +
1457 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1460 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1461 tmp_bit_chk <<= RW_MGR_MEM_DQ_PER_READ_DQS /
1462 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1463 tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
1466 *bit_chk &= tmp_bit_chk;
1469 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1470 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1472 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1475 ret = (*bit_chk == param->read_correct_mask);
1476 debug_cond(DLEVEL == 2,
1477 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1478 __func__, __LINE__, group, all_groups, *bit_chk,
1479 param->read_correct_mask, ret);
1481 ret = (*bit_chk != 0x00);
1482 debug_cond(DLEVEL == 2,
1483 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1484 __func__, __LINE__, group, all_groups, *bit_chk,
1492 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1493 * @grp: Read/Write group
1494 * @num_tries: Number of retries of the test
1495 * @all_correct: All bits must be correct in the mask
1496 * @all_groups: Test all R/W groups
1498 * Perform a READ test across all memory ranks.
1501 rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
1502 const u32 all_correct,
1503 const u32 all_groups)
1506 return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
1507 &bit_chk, all_groups, 1);
1511 * rw_mgr_incr_vfifo() - Increase VFIFO value
1512 * @grp: Read/Write group
1514 * Increase VFIFO value.
1516 static void rw_mgr_incr_vfifo(const u32 grp)
1518 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1522 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1523 * @grp: Read/Write group
1525 * Decrease VFIFO value.
1527 static void rw_mgr_decr_vfifo(const u32 grp)
1531 for (i = 0; i < VFIFO_SIZE - 1; i++)
1532 rw_mgr_incr_vfifo(grp);
1536 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1537 * @grp: Read/Write group
1539 * Push VFIFO until a failing read happens.
1541 static int find_vfifo_failing_read(const u32 grp)
1543 u32 v, ret, fail_cnt = 0;
1545 for (v = 0; v < VFIFO_SIZE; v++) {
1546 debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
1547 __func__, __LINE__, v);
1548 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1557 /* Fiddle with FIFO. */
1558 rw_mgr_incr_vfifo(grp);
1561 /* No failing read found! Something must have gone wrong. */
1562 debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1567 * sdr_find_phase_delay() - Find DQS enable phase or delay
1568 * @working: If 1, look for working phase/delay, if 0, look for non-working
1569 * @delay: If 1, look for delay, if 0, look for phase
1570 * @grp: Read/Write group
1571 * @work: Working window position
1572 * @work_inc: Working window increment
1573 * @pd: DQS Phase/Delay Iterator
1575 * Find working or non-working DQS enable phase setting.
1577 static int sdr_find_phase_delay(int working, int delay, const u32 grp,
1578 u32 *work, const u32 work_inc, u32 *pd)
1580 const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
1583 for (; *pd <= max; (*pd)++) {
1585 scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
1587 scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
1589 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1604 * sdr_find_phase() - Find DQS enable phase
1605 * @working: If 1, look for working phase, if 0, look for non-working phase
1606 * @grp: Read/Write group
1607 * @work: Working window position
1609 * @p: DQS Phase Iterator
1611 * Find working or non-working DQS enable phase setting.
1613 static int sdr_find_phase(int working, const u32 grp, u32 *work,
1616 const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1619 for (; *i < end; (*i)++) {
1623 ret = sdr_find_phase_delay(working, 0, grp, work,
1624 IO_DELAY_PER_OPA_TAP, p);
1628 if (*p > IO_DQS_EN_PHASE_MAX) {
1629 /* Fiddle with FIFO. */
1630 rw_mgr_incr_vfifo(grp);
1640 * sdr_working_phase() - Find working DQS enable phase
1641 * @grp: Read/Write group
1642 * @work_bgn: Working window start position
1643 * @d: dtaps output value
1644 * @p: DQS Phase Iterator
1647 * Find working DQS enable phase setting.
1649 static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
1652 const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1653 IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1658 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1660 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1661 ret = sdr_find_phase(1, grp, work_bgn, i, p);
1664 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1667 /* Cannot find working solution */
1668 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1669 __func__, __LINE__);
1674 * sdr_backup_phase() - Find DQS enable backup phase
1675 * @grp: Read/Write group
1676 * @work_bgn: Working window start position
1677 * @p: DQS Phase Iterator
1679 * Find DQS enable backup phase setting.
1681 static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
1686 /* Special case code for backing up a phase */
1688 *p = IO_DQS_EN_PHASE_MAX;
1689 rw_mgr_decr_vfifo(grp);
1693 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1694 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1696 for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
1697 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1699 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1702 *work_bgn = tmp_delay;
1706 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1709 /* Restore VFIFO to old state before we decremented it (if needed). */
1711 if (*p > IO_DQS_EN_PHASE_MAX) {
1713 rw_mgr_incr_vfifo(grp);
1716 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1720 * sdr_nonworking_phase() - Find non-working DQS enable phase
1721 * @grp: Read/Write group
1722 * @work_end: Working window end position
1723 * @p: DQS Phase Iterator
1726 * Find non-working DQS enable phase setting.
1728 static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
1733 *work_end += IO_DELAY_PER_OPA_TAP;
1734 if (*p > IO_DQS_EN_PHASE_MAX) {
1735 /* Fiddle with FIFO. */
1737 rw_mgr_incr_vfifo(grp);
1740 ret = sdr_find_phase(0, grp, work_end, i, p);
1742 /* Cannot see edge of failing read. */
1743 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1744 __func__, __LINE__);
1751 * sdr_find_window_center() - Find center of the working DQS window.
1752 * @grp: Read/Write group
1753 * @work_bgn: First working settings
1754 * @work_end: Last working settings
1756 * Find center of the working DQS enable window.
1758 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1765 work_mid = (work_bgn + work_end) / 2;
1767 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1768 work_bgn, work_end, work_mid);
1769 /* Get the middle delay to be less than a VFIFO delay */
1770 tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1772 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1773 work_mid %= tmp_delay;
1774 debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1776 tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1777 if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1778 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1779 p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1781 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1783 d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1784 if (d > IO_DQS_EN_DELAY_MAX)
1785 d = IO_DQS_EN_DELAY_MAX;
1786 tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1788 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1790 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1791 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1794 * push vfifo until we can successfully calibrate. We can do this
1795 * because the largest possible margin in 1 VFIFO cycle.
1797 for (i = 0; i < VFIFO_SIZE; i++) {
1798 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
1799 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1802 debug_cond(DLEVEL == 2,
1803 "%s:%d center: found: ptap=%u dtap=%u\n",
1804 __func__, __LINE__, p, d);
1808 /* Fiddle with FIFO. */
1809 rw_mgr_incr_vfifo(grp);
1812 debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1813 __func__, __LINE__);
1818 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1819 * @grp: Read/Write Group
1821 * Find a good DQS enable to use.
1823 static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
1827 u32 work_bgn, work_end;
1828 u32 found_passing_read, found_failing_read, initial_failing_dtap;
1831 debug("%s:%d %u\n", __func__, __LINE__, grp);
1833 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1835 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1836 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1838 /* Step 0: Determine number of delay taps for each phase tap. */
1839 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1841 /* Step 1: First push vfifo until we get a failing read. */
1842 find_vfifo_failing_read(grp);
1844 /* Step 2: Find first working phase, increment in ptaps. */
1846 ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
1850 work_end = work_bgn;
1853 * If d is 0 then the working window covers a phase tap and we can
1854 * follow the old procedure. Otherwise, we've found the beginning
1855 * and we need to increment the dtaps until we find the end.
1859 * Step 3a: If we have room, back off by one and
1860 * increment in dtaps.
1862 sdr_backup_phase(grp, &work_bgn, &p);
1865 * Step 4a: go forward from working phase to non working
1866 * phase, increment in ptaps.
1868 ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
1872 /* Step 5a: Back off one from last, increment in dtaps. */
1874 /* Special case code for backing up a phase */
1876 p = IO_DQS_EN_PHASE_MAX;
1877 rw_mgr_decr_vfifo(grp);
1882 work_end -= IO_DELAY_PER_OPA_TAP;
1883 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1887 debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
1888 __func__, __LINE__, p);
1891 /* The dtap increment to find the failing edge is done here. */
1892 sdr_find_phase_delay(0, 1, grp, &work_end,
1893 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
1895 /* Go back to working dtap */
1897 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1899 debug_cond(DLEVEL == 2,
1900 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1901 __func__, __LINE__, p, d - 1, work_end);
1903 if (work_end < work_bgn) {
1905 debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
1906 __func__, __LINE__);
1910 debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
1911 __func__, __LINE__, work_bgn, work_end);
1914 * We need to calculate the number of dtaps that equal a ptap.
1915 * To do that we'll back up a ptap and re-find the edge of the
1916 * window using dtaps
1918 debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1919 __func__, __LINE__);
1921 /* Special case code for backing up a phase */
1923 p = IO_DQS_EN_PHASE_MAX;
1924 rw_mgr_decr_vfifo(grp);
1925 debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
1926 __func__, __LINE__, p);
1929 debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
1930 __func__, __LINE__, p);
1933 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1936 * Increase dtap until we first see a passing read (in case the
1937 * window is smaller than a ptap), and then a failing read to
1938 * mark the edge of the window again.
1941 /* Find a passing read. */
1942 debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
1943 __func__, __LINE__);
1945 initial_failing_dtap = d;
1947 found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
1948 if (found_passing_read) {
1949 /* Find a failing read. */
1950 debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
1951 __func__, __LINE__);
1953 found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
1956 debug_cond(DLEVEL == 1,
1957 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1958 __func__, __LINE__);
1962 * The dynamically calculated dtaps_per_ptap is only valid if we
1963 * found a passing/failing read. If we didn't, it means d hit the max
1964 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1965 * statically calculated value.
1967 if (found_passing_read && found_failing_read)
1968 dtaps_per_ptap = d - initial_failing_dtap;
1970 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1971 debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1972 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
1974 /* Step 6: Find the centre of the window. */
1975 ret = sdr_find_window_center(grp, work_bgn, work_end);
1981 * search_stop_check() - Check if the detected edge is valid
1982 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1984 * @rank_bgn: Rank number
1985 * @write_group: Write Group
1986 * @read_group: Read Group
1987 * @bit_chk: Resulting bit mask after the test
1988 * @sticky_bit_chk: Resulting sticky bit mask after the test
1989 * @use_read_test: Perform read test
1991 * Test if the found edge is valid.
1993 static u32 search_stop_check(const int write, const int d, const int rank_bgn,
1994 const u32 write_group, const u32 read_group,
1995 u32 *bit_chk, u32 *sticky_bit_chk,
1996 const u32 use_read_test)
1998 const u32 ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
1999 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
2000 const u32 correct_mask = write ? param->write_correct_mask :
2001 param->read_correct_mask;
2002 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2003 RW_MGR_MEM_DQ_PER_READ_DQS;
2006 * Stop searching when the read test doesn't pass AND when
2007 * we've seen a passing read on every bit.
2009 if (write) { /* WRITE-ONLY */
2010 ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2013 } else if (use_read_test) { /* READ-ONLY */
2014 ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group,
2016 PASS_ONE_BIT, bit_chk,
2018 } else { /* READ-ONLY */
2019 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0,
2020 PASS_ONE_BIT, bit_chk, 0);
2021 *bit_chk = *bit_chk >> (per_dqs *
2022 (read_group - (write_group * ratio)));
2023 ret = (*bit_chk == 0);
2025 *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
2026 ret = ret && (*sticky_bit_chk == correct_mask);
2027 debug_cond(DLEVEL == 2,
2028 "%s:%d center(left): dtap=%u => %u == %u && %u",
2029 __func__, __LINE__, d,
2030 *sticky_bit_chk, correct_mask, ret);
2035 * search_left_edge() - Find left edge of DQ/DQS working phase
2036 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2037 * @rank_bgn: Rank number
2038 * @write_group: Write Group
2039 * @read_group: Read Group
2040 * @test_bgn: Rank number to begin the test
2041 * @sticky_bit_chk: Resulting sticky bit mask after the test
2042 * @left_edge: Left edge of the DQ/DQS phase
2043 * @right_edge: Right edge of the DQ/DQS phase
2044 * @use_read_test: Perform read test
2046 * Find left edge of DQ/DQS working phase.
2048 static void search_left_edge(const int write, const int rank_bgn,
2049 const u32 write_group, const u32 read_group, const u32 test_bgn,
2050 u32 *sticky_bit_chk,
2051 int *left_edge, int *right_edge, const u32 use_read_test)
2053 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
2054 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
2055 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2056 RW_MGR_MEM_DQ_PER_READ_DQS;
2060 for (d = 0; d <= dqs_max; d++) {
2062 scc_mgr_apply_group_dq_out1_delay(d);
2064 scc_mgr_apply_group_dq_in_delay(test_bgn, d);
2066 writel(0, &sdr_scc_mgr->update);
2068 stop = search_stop_check(write, d, rank_bgn, write_group,
2069 read_group, &bit_chk, sticky_bit_chk,
2075 for (i = 0; i < per_dqs; i++) {
2078 * Remember a passing test as
2084 * If a left edge has not been seen
2085 * yet, then a future passing test
2086 * will mark this edge as the right
2089 if (left_edge[i] == delay_max + 1)
2090 right_edge[i] = -(d + 1);
2096 /* Reset DQ delay chains to 0 */
2098 scc_mgr_apply_group_dq_out1_delay(0);
2100 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2102 *sticky_bit_chk = 0;
2103 for (i = per_dqs - 1; i >= 0; i--) {
2104 debug_cond(DLEVEL == 2,
2105 "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
2106 __func__, __LINE__, i, left_edge[i],
2110 * Check for cases where we haven't found the left edge,
2111 * which makes our assignment of the the right edge invalid.
2112 * Reset it to the illegal value.
2114 if ((left_edge[i] == delay_max + 1) &&
2115 (right_edge[i] != delay_max + 1)) {
2116 right_edge[i] = delay_max + 1;
2117 debug_cond(DLEVEL == 2,
2118 "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
2119 __func__, __LINE__, i, right_edge[i]);
2124 * READ: except for bits where we have seen both
2125 * the left and right edge.
2126 * WRITE: except for bits where we have seen the
2129 *sticky_bit_chk <<= 1;
2131 if (left_edge[i] != delay_max + 1)
2132 *sticky_bit_chk |= 1;
2134 if ((left_edge[i] != delay_max + 1) &&
2135 (right_edge[i] != delay_max + 1))
2136 *sticky_bit_chk |= 1;
2144 * search_right_edge() - Find right edge of DQ/DQS working phase
2145 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2146 * @rank_bgn: Rank number
2147 * @write_group: Write Group
2148 * @read_group: Read Group
2149 * @start_dqs: DQS start phase
2150 * @start_dqs_en: DQS enable start phase
2151 * @sticky_bit_chk: Resulting sticky bit mask after the test
2152 * @left_edge: Left edge of the DQ/DQS phase
2153 * @right_edge: Right edge of the DQ/DQS phase
2154 * @use_read_test: Perform read test
2156 * Find right edge of DQ/DQS working phase.
2158 static int search_right_edge(const int write, const int rank_bgn,
2159 const u32 write_group, const u32 read_group,
2160 const int start_dqs, const int start_dqs_en,
2161 u32 *sticky_bit_chk,
2162 int *left_edge, int *right_edge, const u32 use_read_test)
2164 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
2165 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
2166 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2167 RW_MGR_MEM_DQ_PER_READ_DQS;
2171 for (d = 0; d <= dqs_max - start_dqs; d++) {
2172 if (write) { /* WRITE-ONLY */
2173 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2175 } else { /* READ-ONLY */
2176 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
2177 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2178 uint32_t delay = d + start_dqs_en;
2179 if (delay > IO_DQS_EN_DELAY_MAX)
2180 delay = IO_DQS_EN_DELAY_MAX;
2181 scc_mgr_set_dqs_en_delay(read_group, delay);
2183 scc_mgr_load_dqs(read_group);
2186 writel(0, &sdr_scc_mgr->update);
2188 stop = search_stop_check(write, d, rank_bgn, write_group,
2189 read_group, &bit_chk, sticky_bit_chk,
2192 if (write && (d == 0)) { /* WRITE-ONLY */
2193 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2195 * d = 0 failed, but it passed when
2196 * testing the left edge, so it must be
2197 * marginal, set it to -1
2199 if (right_edge[i] == delay_max + 1 &&
2200 left_edge[i] != delay_max + 1)
2208 for (i = 0; i < per_dqs; i++) {
2211 * Remember a passing test as
2218 * If a right edge has not
2219 * been seen yet, then a future
2220 * passing test will mark this
2221 * edge as the left edge.
2223 if (right_edge[i] == delay_max + 1)
2224 left_edge[i] = -(d + 1);
2227 * d = 0 failed, but it passed
2228 * when testing the left edge,
2229 * so it must be marginal, set
2232 if (right_edge[i] == delay_max + 1 &&
2233 left_edge[i] != delay_max + 1)
2236 * If a right edge has not been
2237 * seen yet, then a future
2238 * passing test will mark this
2239 * edge as the left edge.
2241 else if (right_edge[i] == delay_max + 1)
2242 left_edge[i] = -(d + 1);
2246 debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ",
2247 __func__, __LINE__, d);
2248 debug_cond(DLEVEL == 2,
2249 "bit_chk_test=%i left_edge[%u]: %d ",
2250 bit_chk & 1, i, left_edge[i]);
2251 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2257 /* Check that all bits have a window */
2258 for (i = 0; i < per_dqs; i++) {
2259 debug_cond(DLEVEL == 2,
2260 "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
2261 __func__, __LINE__, i, left_edge[i],
2263 if ((left_edge[i] == dqs_max + 1) ||
2264 (right_edge[i] == dqs_max + 1))
2265 return i + 1; /* FIXME: If we fail, retval > 0 */
2272 * get_window_mid_index() - Find the best middle setting of DQ/DQS phase
2273 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2274 * @left_edge: Left edge of the DQ/DQS phase
2275 * @right_edge: Right edge of the DQ/DQS phase
2276 * @mid_min: Best DQ/DQS phase middle setting
2278 * Find index and value of the middle of the DQ/DQS working phase.
2280 static int get_window_mid_index(const int write, int *left_edge,
2281 int *right_edge, int *mid_min)
2283 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2284 RW_MGR_MEM_DQ_PER_READ_DQS;
2285 int i, mid, min_index;
2287 /* Find middle of window for each DQ bit */
2288 *mid_min = left_edge[0] - right_edge[0];
2290 for (i = 1; i < per_dqs; i++) {
2291 mid = left_edge[i] - right_edge[i];
2292 if (mid < *mid_min) {
2299 * -mid_min/2 represents the amount that we need to move DQS.
2300 * If mid_min is odd and positive we'll need to add one to make
2301 * sure the rounding in further calculations is correct (always
2302 * bias to the right), so just add 1 for all positive values.
2306 *mid_min = *mid_min / 2;
2308 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
2309 __func__, __LINE__, *mid_min, min_index);
2314 * center_dq_windows() - Center the DQ/DQS windows
2315 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2316 * @left_edge: Left edge of the DQ/DQS phase
2317 * @right_edge: Right edge of the DQ/DQS phase
2318 * @mid_min: Adjusted DQ/DQS phase middle setting
2319 * @orig_mid_min: Original DQ/DQS phase middle setting
2320 * @min_index: DQ/DQS phase middle setting index
2321 * @test_bgn: Rank number to begin the test
2322 * @dq_margin: Amount of shift for the DQ
2323 * @dqs_margin: Amount of shift for the DQS
2325 * Align the DQ/DQS windows in each group.
2327 static void center_dq_windows(const int write, int *left_edge, int *right_edge,
2328 const int mid_min, const int orig_mid_min,
2329 const int min_index, const int test_bgn,
2330 int *dq_margin, int *dqs_margin)
2332 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
2333 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2334 RW_MGR_MEM_DQ_PER_READ_DQS;
2335 const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
2336 SCC_MGR_IO_IN_DELAY_OFFSET;
2337 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
2339 u32 temp_dq_io_delay1, temp_dq_io_delay2;
2342 /* Initialize data for export structures */
2343 *dqs_margin = delay_max + 1;
2344 *dq_margin = delay_max + 1;
2346 /* add delay to bring centre of all DQ windows to the same "level" */
2347 for (i = 0, p = test_bgn; i < per_dqs; i++, p++) {
2348 /* Use values before divide by 2 to reduce round off error */
2349 shift_dq = (left_edge[i] - right_edge[i] -
2350 (left_edge[min_index] - right_edge[min_index]))/2 +
2351 (orig_mid_min - mid_min);
2353 debug_cond(DLEVEL == 2,
2354 "vfifo_center: before: shift_dq[%u]=%d\n",
2357 temp_dq_io_delay1 = readl(addr + (p << 2));
2358 temp_dq_io_delay2 = readl(addr + (i << 2));
2360 if (shift_dq + temp_dq_io_delay1 > delay_max)
2361 shift_dq = delay_max - temp_dq_io_delay2;
2362 else if (shift_dq + temp_dq_io_delay1 < 0)
2363 shift_dq = -temp_dq_io_delay1;
2365 debug_cond(DLEVEL == 2,
2366 "vfifo_center: after: shift_dq[%u]=%d\n",
2370 scc_mgr_set_dq_out1_delay(i, temp_dq_io_delay1 + shift_dq);
2372 scc_mgr_set_dq_in_delay(p, temp_dq_io_delay1 + shift_dq);
2376 debug_cond(DLEVEL == 2,
2377 "vfifo_center: margin[%u]=[%d,%d]\n", i,
2378 left_edge[i] - shift_dq + (-mid_min),
2379 right_edge[i] + shift_dq - (-mid_min));
2381 /* To determine values for export structures */
2382 if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin)
2383 *dq_margin = left_edge[i] - shift_dq + (-mid_min);
2385 if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
2386 *dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2392 * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering
2393 * @rank_bgn: Rank number
2394 * @rw_group: Read/Write Group
2395 * @test_bgn: Rank at which the test begins
2396 * @use_read_test: Perform a read test
2397 * @update_fom: Update FOM
2399 * Per-bit deskew DQ and centering.
2401 static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
2402 const u32 rw_group, const u32 test_bgn,
2403 const int use_read_test, const int update_fom)
2406 SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
2409 * Store these as signed since there are comparisons with
2412 uint32_t sticky_bit_chk;
2413 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2414 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2415 int32_t orig_mid_min, mid_min;
2416 int32_t new_dqs, start_dqs, start_dqs_en, final_dqs_en;
2417 int32_t dq_margin, dqs_margin;
2421 debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
2423 start_dqs = readl(addr);
2424 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2425 start_dqs_en = readl(addr - IO_DQS_EN_DELAY_OFFSET);
2427 /* set the left and right edge of each bit to an illegal value */
2428 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
2430 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2431 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2432 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2435 /* Search for the left edge of the window for each bit */
2436 search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn,
2438 left_edge, right_edge, use_read_test);
2441 /* Search for the right edge of the window for each bit */
2442 ret = search_right_edge(0, rank_bgn, rw_group, rw_group,
2443 start_dqs, start_dqs_en,
2445 left_edge, right_edge, use_read_test);
2448 * Restore delay chain settings before letting the loop
2449 * in rw_mgr_mem_calibrate_vfifo to retry different
2450 * dqs/ck relationships.
2452 scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
2453 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2454 scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
2456 scc_mgr_load_dqs(rw_group);
2457 writel(0, &sdr_scc_mgr->update);
2459 debug_cond(DLEVEL == 1,
2460 "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
2461 __func__, __LINE__, i, left_edge[i], right_edge[i]);
2462 if (use_read_test) {
2463 set_failing_group_stage(rw_group *
2464 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2466 CAL_SUBSTAGE_VFIFO_CENTER);
2468 set_failing_group_stage(rw_group *
2469 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2470 CAL_STAGE_VFIFO_AFTER_WRITES,
2471 CAL_SUBSTAGE_VFIFO_CENTER);
2476 min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min);
2478 /* Determine the amount we can change DQS (which is -mid_min) */
2479 orig_mid_min = mid_min;
2480 new_dqs = start_dqs - mid_min;
2481 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2482 new_dqs = IO_DQS_IN_DELAY_MAX;
2483 else if (new_dqs < 0)
2486 mid_min = start_dqs - new_dqs;
2487 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2490 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2491 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2492 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2493 else if (start_dqs_en - mid_min < 0)
2494 mid_min += start_dqs_en - mid_min;
2496 new_dqs = start_dqs - mid_min;
2498 debug_cond(DLEVEL == 1,
2499 "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
2501 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2504 /* Add delay to bring centre of all DQ windows to the same "level". */
2505 center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min,
2506 min_index, test_bgn, &dq_margin, &dqs_margin);
2509 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2510 final_dqs_en = start_dqs_en - mid_min;
2511 scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
2512 scc_mgr_load_dqs(rw_group);
2516 scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
2517 scc_mgr_load_dqs(rw_group);
2518 debug_cond(DLEVEL == 2,
2519 "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
2520 __func__, __LINE__, dq_margin, dqs_margin);
2523 * Do not remove this line as it makes sure all of our decisions
2524 * have been applied. Apply the update bit.
2526 writel(0, &sdr_scc_mgr->update);
2528 if ((dq_margin < 0) || (dqs_margin < 0))
2535 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2536 * @rw_group: Read/Write Group
2537 * @phase: DQ/DQS phase
2539 * Because initially no communication ca be reliably performed with the memory
2540 * device, the sequencer uses a guaranteed write mechanism to write data into
2541 * the memory device.
2543 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2548 /* Set a particular DQ/DQS phase. */
2549 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2551 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2552 __func__, __LINE__, rw_group, phase);
2555 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2556 * Load up the patterns used by read calibration using the
2557 * current DQDQS phase.
2559 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2561 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2565 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2566 * Back-to-Back reads of the patterns used for calibration.
2568 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2570 debug_cond(DLEVEL == 1,
2571 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2572 __func__, __LINE__, rw_group, phase);
2577 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2578 * @rw_group: Read/Write Group
2579 * @test_bgn: Rank at which the test begins
2581 * DQS enable calibration ensures reliable capture of the DQ signal without
2582 * glitches on the DQS line.
2584 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2588 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2589 * DQS and DQS Eanble Signal Relationships.
2592 /* We start at zero, so have one less dq to devide among */
2593 const u32 delay_step = IO_IO_IN_DELAY_MAX /
2594 (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2598 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2600 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2601 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2602 r += NUM_RANKS_PER_SHADOW_REG) {
2603 for (i = 0, p = test_bgn, d = 0;
2604 i < RW_MGR_MEM_DQ_PER_READ_DQS;
2605 i++, p++, d += delay_step) {
2606 debug_cond(DLEVEL == 1,
2607 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2608 __func__, __LINE__, rw_group, r, i, p, d);
2610 scc_mgr_set_dq_in_delay(p, d);
2614 writel(0, &sdr_scc_mgr->update);
2618 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2619 * dq_in_delay values
2621 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2623 debug_cond(DLEVEL == 1,
2624 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2625 __func__, __LINE__, rw_group, !ret);
2627 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2628 r += NUM_RANKS_PER_SHADOW_REG) {
2629 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2630 writel(0, &sdr_scc_mgr->update);
2637 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2638 * @rw_group: Read/Write Group
2639 * @test_bgn: Rank at which the test begins
2640 * @use_read_test: Perform a read test
2641 * @update_fom: Update FOM
2643 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2647 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2648 const int use_read_test,
2649 const int update_fom)
2652 int ret, grp_calibrated;
2656 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2657 * Read per-bit deskew can be done on a per shadow register basis.
2660 for (rank_bgn = 0, sr = 0;
2661 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2662 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2663 /* Check if this set of ranks should be skipped entirely. */
2664 if (param->skip_shadow_regs[sr])
2667 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2677 if (!grp_calibrated)
2684 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2685 * @rw_group: Read/Write Group
2686 * @test_bgn: Rank at which the test begins
2688 * Stage 1: Calibrate the read valid prediction FIFO.
2690 * This function implements UniPHY calibration Stage 1, as explained in
2691 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2693 * - read valid prediction will consist of finding:
2694 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2695 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2696 * - we also do a per-bit deskew on the DQ lines.
2698 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2701 uint32_t dtaps_per_ptap;
2702 uint32_t failed_substage;
2706 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2708 /* Update info for sims */
2709 reg_file_set_group(rw_group);
2710 reg_file_set_stage(CAL_STAGE_VFIFO);
2711 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2713 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2715 /* USER Determine number of delay taps for each phase tap. */
2716 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2717 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2719 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2721 * In RLDRAMX we may be messing the delay of pins in
2722 * the same write rw_group but outside of the current read
2723 * the rw_group, but that's ok because we haven't calibrated
2727 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2731 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2732 /* 1) Guaranteed Write */
2733 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2737 /* 2) DQS Enable Calibration */
2738 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2741 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2745 /* 3) Centering DQ/DQS */
2747 * If doing read after write calibration, do not update
2748 * FOM now. Do it then.
2750 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2753 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2762 /* Calibration Stage 1 failed. */
2763 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2766 /* Calibration Stage 1 completed OK. */
2769 * Reset the delay chains back to zero if they have moved > 1
2770 * (check for > 1 because loop will increase d even when pass in
2774 scc_mgr_zero_group(rw_group, 1);
2779 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2780 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2783 uint32_t rank_bgn, sr;
2784 uint32_t grp_calibrated;
2785 uint32_t write_group;
2787 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2789 /* update info for sims */
2791 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2792 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2794 write_group = read_group;
2796 /* update info for sims */
2797 reg_file_set_group(read_group);
2800 /* Read per-bit deskew can be done on a per shadow register basis */
2801 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2802 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2803 /* Determine if this set of ranks should be skipped entirely */
2804 if (!param->skip_shadow_regs[sr]) {
2805 /* This is the last calibration round, update FOM here */
2806 if (rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2816 if (grp_calibrated == 0) {
2817 set_failing_group_stage(write_group,
2818 CAL_STAGE_VFIFO_AFTER_WRITES,
2819 CAL_SUBSTAGE_VFIFO_CENTER);
2826 /* Calibrate LFIFO to find smallest read latency */
2827 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2831 debug("%s:%d\n", __func__, __LINE__);
2833 /* update info for sims */
2834 reg_file_set_stage(CAL_STAGE_LFIFO);
2835 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2837 /* Load up the patterns used by read calibration for all ranks */
2838 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2842 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2843 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2844 __func__, __LINE__, gbl->curr_read_lat);
2846 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2854 /* reduce read latency and see if things are working */
2856 gbl->curr_read_lat--;
2857 } while (gbl->curr_read_lat > 0);
2859 /* reset the fifos to get pointers to known state */
2861 writel(0, &phy_mgr_cmd->fifo_reset);
2864 /* add a fudge factor to the read latency that was determined */
2865 gbl->curr_read_lat += 2;
2866 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2867 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2868 read_lat=%u\n", __func__, __LINE__,
2869 gbl->curr_read_lat);
2872 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2873 CAL_SUBSTAGE_READ_LATENCY);
2875 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2876 read_lat=%u\n", __func__, __LINE__,
2877 gbl->curr_read_lat);
2883 * search_window() - Search for the/part of the window with DM/DQS shift
2884 * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
2885 * @rank_bgn: Rank number
2886 * @write_group: Write Group
2887 * @bgn_curr: Current window begin
2888 * @end_curr: Current window end
2889 * @bgn_best: Current best window begin
2890 * @end_best: Current best window end
2891 * @win_best: Size of the best window
2892 * @new_dqs: New DQS value (only applicable if search_dm = 0).
2894 * Search for the/part of the window with DM/DQS shift.
2896 static void search_window(const int search_dm,
2897 const u32 rank_bgn, const u32 write_group,
2898 int *bgn_curr, int *end_curr, int *bgn_best,
2899 int *end_best, int *win_best, int new_dqs)
2902 const int max = IO_IO_OUT1_DELAY_MAX - new_dqs;
2905 /* Search for the/part of the window with DM/DQS shift. */
2906 for (di = max; di >= 0; di -= DELTA_D) {
2909 scc_mgr_apply_group_dm_out1_delay(d);
2911 /* For DQS, we go from 0...max */
2914 * Note: This only shifts DQS, so are we limiting ourselve to
2915 * width of DQ unnecessarily.
2917 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2921 writel(0, &sdr_scc_mgr->update);
2923 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2924 PASS_ALL_BITS, &bit_chk,
2926 /* Set current end of the window. */
2927 *end_curr = search_dm ? -d : d;
2930 * If a starting edge of our window has not been seen
2931 * this is our current start of the DM window.
2933 if (*bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2934 *bgn_curr = search_dm ? -d : d;
2937 * If current window is bigger than best seen.
2938 * Set best seen to be current window.
2940 if ((*end_curr - *bgn_curr + 1) > *win_best) {
2941 *win_best = *end_curr - *bgn_curr + 1;
2942 *bgn_best = *bgn_curr;
2943 *end_best = *end_curr;
2946 /* We just saw a failing test. Reset temp edge. */
2947 *bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2948 *end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2950 /* Early exit is only applicable to DQS. */
2955 * Early exit optimization: if the remaining delay
2956 * chain space is less than already seen largest
2957 * window we can exit.
2959 if (*win_best - 1 > IO_IO_OUT1_DELAY_MAX - new_dqs - d)
2966 * rw_mgr_mem_calibrate_writes_center() - Center all windows
2967 * @rank_bgn: Rank number
2968 * @write_group: Write group
2969 * @test_bgn: Rank at which the test begins
2971 * Center all windows. Do per-bit-deskew to possibly increase size of
2975 rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
2981 int left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2982 int right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2984 int mid_min, orig_mid_min;
2985 int new_dqs, start_dqs;
2986 int dq_margin, dqs_margin, dm_margin;
2987 int bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2988 int end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2989 int bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2990 int end_best = IO_IO_OUT1_DELAY_MAX + 1;
2995 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2999 start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
3000 SCC_MGR_IO_OUT1_DELAY_OFFSET) +
3001 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
3003 /* Per-bit deskew. */
3006 * Set the left and right edge of each bit to an illegal value.
3007 * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
3010 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
3011 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
3012 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
3015 /* Search for the left edge of the window for each bit. */
3016 search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
3018 left_edge, right_edge, 0);
3020 /* Search for the right edge of the window for each bit. */
3021 ret = search_right_edge(1, rank_bgn, write_group, 0,
3024 left_edge, right_edge, 0);
3026 set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
3027 CAL_SUBSTAGE_WRITES_CENTER);
3031 min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
3033 /* Determine the amount we can change DQS (which is -mid_min). */
3034 orig_mid_min = mid_min;
3035 new_dqs = start_dqs;
3037 debug_cond(DLEVEL == 1,
3038 "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
3039 __func__, __LINE__, start_dqs, new_dqs, mid_min);
3041 /* Add delay to bring centre of all DQ windows to the same "level". */
3042 center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min,
3043 min_index, 0, &dq_margin, &dqs_margin);
3046 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3047 writel(0, &sdr_scc_mgr->update);
3050 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3053 * Set the left and right edge of each bit to an illegal value.
3054 * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
3056 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3057 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3059 /* Search for the/part of the window with DM shift. */
3060 search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr,
3061 &bgn_best, &end_best, &win_best, 0);
3063 /* Reset DM delay chains to 0. */
3064 scc_mgr_apply_group_dm_out1_delay(0);
3067 * Check to see if the current window nudges up aganist 0 delay.
3068 * If so we need to continue the search by shifting DQS otherwise DQS
3069 * search begins as a new search.
3071 if (end_curr != 0) {
3072 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3073 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3076 /* Search for the/part of the window with DQS shifts. */
3077 search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr,
3078 &bgn_best, &end_best, &win_best, new_dqs);
3080 /* Assign left and right edge for cal and reporting. */
3081 left_edge[0] = -1 * bgn_best;
3082 right_edge[0] = end_best;
3084 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n",
3085 __func__, __LINE__, left_edge[0], right_edge[0]);
3087 /* Move DQS (back to orig). */
3088 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3092 /* Find middle of window for the DM bit. */
3093 mid = (left_edge[0] - right_edge[0]) / 2;
3095 /* Only move right, since we are not moving DQS/DQ. */
3099 /* dm_marign should fail if we never find a window. */
3103 dm_margin = left_edge[0] - mid;
3105 scc_mgr_apply_group_dm_out1_delay(mid);
3106 writel(0, &sdr_scc_mgr->update);
3108 debug_cond(DLEVEL == 2,
3109 "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
3110 __func__, __LINE__, left_edge[0], right_edge[0],
3112 /* Export values. */
3113 gbl->fom_out += dq_margin + dqs_margin;
3115 debug_cond(DLEVEL == 2,
3116 "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
3117 __func__, __LINE__, dq_margin, dqs_margin, dm_margin);
3120 * Do not remove this line as it makes sure all of our
3121 * decisions have been applied.
3123 writel(0, &sdr_scc_mgr->update);
3125 if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0))
3132 * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
3133 * @rank_bgn: Rank number
3134 * @group: Read/Write Group
3135 * @test_bgn: Rank at which the test begins
3137 * Stage 2: Write Calibration Part One.
3139 * This function implements UniPHY calibration Stage 2, as explained in
3140 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
3142 static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
3147 /* Update info for sims */
3148 debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
3150 reg_file_set_group(group);
3151 reg_file_set_stage(CAL_STAGE_WRITES);
3152 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3154 ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
3156 set_failing_group_stage(group, CAL_STAGE_WRITES,
3157 CAL_SUBSTAGE_WRITES_CENTER);
3163 * mem_precharge_and_activate() - Precharge all banks and activate
3165 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3167 static void mem_precharge_and_activate(void)
3171 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3172 /* Test if the rank should be skipped. */
3173 if (param->skip_ranks[r])
3177 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3179 /* Precharge all banks. */
3180 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3181 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3183 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3184 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3185 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3187 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3188 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3189 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3191 /* Activate rows. */
3192 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3193 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3198 * mem_init_latency() - Configure memory RLAT and WLAT settings
3200 * Configure memory RLAT and WLAT parameters.
3202 static void mem_init_latency(void)
3205 * For AV/CV, LFIFO is hardened and always runs at full rate
3206 * so max latency in AFI clocks, used here, is correspondingly
3209 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3212 debug("%s:%d\n", __func__, __LINE__);
3215 * Read in write latency.
3216 * WL for Hard PHY does not include additive latency.
3218 wlat = readl(&data_mgr->t_wl_add);
3219 wlat += readl(&data_mgr->mem_t_add);
3221 gbl->rw_wl_nop_cycles = wlat - 1;
3223 /* Read in readl latency. */
3224 rlat = readl(&data_mgr->t_rl_add);
3226 /* Set a pretty high read latency initially. */
3227 gbl->curr_read_lat = rlat + 16;
3228 if (gbl->curr_read_lat > max_latency)
3229 gbl->curr_read_lat = max_latency;
3231 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3233 /* Advertise write latency. */
3234 writel(wlat, &phy_mgr_cfg->afi_wlat);
3238 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3240 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3242 static void mem_skip_calibrate(void)
3244 uint32_t vfifo_offset;
3247 debug("%s:%d\n", __func__, __LINE__);
3248 /* Need to update every shadow register set used by the interface */
3249 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3250 r += NUM_RANKS_PER_SHADOW_REG) {
3252 * Set output phase alignment settings appropriate for
3255 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3256 scc_mgr_set_dqs_en_phase(i, 0);
3257 #if IO_DLL_CHAIN_LENGTH == 6
3258 scc_mgr_set_dqdqs_output_phase(i, 6);
3260 scc_mgr_set_dqdqs_output_phase(i, 7);
3265 * Write data arrives to the I/O two cycles before write
3266 * latency is reached (720 deg).
3267 * -> due to bit-slip in a/c bus
3268 * -> to allow board skew where dqs is longer than ck
3269 * -> how often can this happen!?
3270 * -> can claim back some ptaps for high freq
3271 * support if we can relax this, but i digress...
3273 * The write_clk leads mem_ck by 90 deg
3274 * The minimum ptap of the OPA is 180 deg
3275 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3276 * The write_clk is always delayed by 2 ptaps
3278 * Hence, to make DQS aligned to CK, we need to delay
3280 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3282 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3283 * gives us the number of ptaps, which simplies to:
3285 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3287 scc_mgr_set_dqdqs_output_phase(i,
3288 1.25 * IO_DLL_CHAIN_LENGTH - 2);
3290 writel(0xff, &sdr_scc_mgr->dqs_ena);
3291 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3293 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3294 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3295 SCC_MGR_GROUP_COUNTER_OFFSET);
3297 writel(0xff, &sdr_scc_mgr->dq_ena);
3298 writel(0xff, &sdr_scc_mgr->dm_ena);
3299 writel(0, &sdr_scc_mgr->update);
3302 /* Compensate for simulation model behaviour */
3303 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3304 scc_mgr_set_dqs_bus_in_delay(i, 10);
3305 scc_mgr_load_dqs(i);
3307 writel(0, &sdr_scc_mgr->update);
3310 * ArriaV has hard FIFOs that can only be initialized by incrementing
3313 vfifo_offset = CALIB_VFIFO_OFFSET;
3314 for (j = 0; j < vfifo_offset; j++)
3315 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3316 writel(0, &phy_mgr_cmd->fifo_reset);
3319 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3320 * setting from generation-time constant.
3322 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3323 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3327 * mem_calibrate() - Memory calibration entry point.
3329 * Perform memory calibration.
3331 static uint32_t mem_calibrate(void)
3334 uint32_t rank_bgn, sr;
3335 uint32_t write_group, write_test_bgn;
3336 uint32_t read_group, read_test_bgn;
3337 uint32_t run_groups, current_run;
3338 uint32_t failing_groups = 0;
3339 uint32_t group_failed = 0;
3341 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3342 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3344 debug("%s:%d\n", __func__, __LINE__);
3346 /* Initialize the data settings */
3347 gbl->error_substage = CAL_SUBSTAGE_NIL;
3348 gbl->error_stage = CAL_STAGE_NIL;
3349 gbl->error_group = 0xff;
3353 /* Initialize WLAT and RLAT. */
3356 /* Initialize bit slips. */
3357 mem_precharge_and_activate();
3359 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3360 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3361 SCC_MGR_GROUP_COUNTER_OFFSET);
3362 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3364 scc_mgr_set_hhp_extras();
3366 scc_set_bypass_mode(i);
3369 /* Calibration is skipped. */
3370 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3372 * Set VFIFO and LFIFO to instant-on settings in skip
3375 mem_skip_calibrate();
3378 * Do not remove this line as it makes sure all of our
3379 * decisions have been applied.
3381 writel(0, &sdr_scc_mgr->update);
3385 /* Calibration is not skipped. */
3386 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3388 * Zero all delay chain/phase settings for all
3389 * groups and all shadow register sets.
3393 run_groups = ~param->skip_groups;
3395 for (write_group = 0, write_test_bgn = 0; write_group
3396 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3397 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3399 /* Initialize the group failure */
3402 current_run = run_groups & ((1 <<
3403 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3404 run_groups = run_groups >>
3405 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3407 if (current_run == 0)
3410 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3411 SCC_MGR_GROUP_COUNTER_OFFSET);
3412 scc_mgr_zero_group(write_group, 0);
3414 for (read_group = write_group * rwdqs_ratio,
3416 read_group < (write_group + 1) * rwdqs_ratio;
3418 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3419 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3422 /* Calibrate the VFIFO */
3423 if (rw_mgr_mem_calibrate_vfifo(read_group,
3427 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3430 /* The group failed, we're done. */
3434 /* Calibrate the output side */
3435 for (rank_bgn = 0, sr = 0;
3436 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3437 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3438 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3441 /* Not needed in quick mode! */
3442 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3446 * Determine if this set of ranks
3447 * should be skipped entirely.
3449 if (param->skip_shadow_regs[sr])
3452 /* Calibrate WRITEs */
3453 if (!rw_mgr_mem_calibrate_writes(rank_bgn,
3454 write_group, write_test_bgn))
3458 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3462 /* Some group failed, we're done. */
3466 for (read_group = write_group * rwdqs_ratio,
3468 read_group < (write_group + 1) * rwdqs_ratio;
3470 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3471 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3474 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3478 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3481 /* The group failed, we're done. */
3485 /* No group failed, continue as usual. */
3488 grp_failed: /* A group failed, increment the counter. */
3493 * USER If there are any failing groups then report
3496 if (failing_groups != 0)
3499 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3503 * If we're skipping groups as part of debug,
3504 * don't calibrate LFIFO.
3506 if (param->skip_groups != 0)
3509 /* Calibrate the LFIFO */
3510 if (!rw_mgr_mem_calibrate_lfifo())
3515 * Do not remove this line as it makes sure all of our decisions
3516 * have been applied.
3518 writel(0, &sdr_scc_mgr->update);
3523 * run_mem_calibrate() - Perform memory calibration
3525 * This function triggers the entire memory calibration procedure.
3527 static int run_mem_calibrate(void)
3531 debug("%s:%d\n", __func__, __LINE__);
3533 /* Reset pass/fail status shown on afi_cal_success/fail */
3534 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3536 /* Stop tracking manager. */
3537 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3539 phy_mgr_initialize();
3540 rw_mgr_mem_initialize();
3542 /* Perform the actual memory calibration. */
3543 pass = mem_calibrate();
3545 mem_precharge_and_activate();
3546 writel(0, &phy_mgr_cmd->fifo_reset);
3549 rw_mgr_mem_handoff();
3551 * In Hard PHY this is a 2-bit control:
3553 * 1: DDIO Mux Select
3555 writel(0x2, &phy_mgr_cfg->mux_sel);
3557 /* Start tracking manager. */
3558 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3564 * debug_mem_calibrate() - Report result of memory calibration
3565 * @pass: Value indicating whether calibration passed or failed
3567 * This function reports the results of the memory calibration
3568 * and writes debug information into the register file.
3570 static void debug_mem_calibrate(int pass)
3572 uint32_t debug_info;
3575 printf("%s: CALIBRATION PASSED\n", __FILE__);
3580 if (gbl->fom_in > 0xff)
3583 if (gbl->fom_out > 0xff)
3584 gbl->fom_out = 0xff;
3586 /* Update the FOM in the register file */
3587 debug_info = gbl->fom_in;
3588 debug_info |= gbl->fom_out << 8;
3589 writel(debug_info, &sdr_reg_file->fom);
3591 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3592 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3594 printf("%s: CALIBRATION FAILED\n", __FILE__);
3596 debug_info = gbl->error_stage;
3597 debug_info |= gbl->error_substage << 8;
3598 debug_info |= gbl->error_group << 16;
3600 writel(debug_info, &sdr_reg_file->failing_stage);
3601 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3602 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3604 /* Update the failing group/stage in the register file */
3605 debug_info = gbl->error_stage;
3606 debug_info |= gbl->error_substage << 8;
3607 debug_info |= gbl->error_group << 16;
3608 writel(debug_info, &sdr_reg_file->failing_stage);
3611 printf("%s: Calibration complete\n", __FILE__);
3615 * hc_initialize_rom_data() - Initialize ROM data
3617 * Initialize ROM data.
3619 static void hc_initialize_rom_data(void)
3623 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3624 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3625 writel(inst_rom_init[i], addr + (i << 2));
3627 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3628 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3629 writel(ac_rom_init[i], addr + (i << 2));
3633 * initialize_reg_file() - Initialize SDR register file
3635 * Initialize SDR register file.
3637 static void initialize_reg_file(void)
3639 /* Initialize the register file with the correct data */
3640 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3641 writel(0, &sdr_reg_file->debug_data_addr);
3642 writel(0, &sdr_reg_file->cur_stage);
3643 writel(0, &sdr_reg_file->fom);
3644 writel(0, &sdr_reg_file->failing_stage);
3645 writel(0, &sdr_reg_file->debug1);
3646 writel(0, &sdr_reg_file->debug2);
3650 * initialize_hps_phy() - Initialize HPS PHY
3652 * Initialize HPS PHY.
3654 static void initialize_hps_phy(void)
3658 * Tracking also gets configured here because it's in the
3661 uint32_t trk_sample_count = 7500;
3662 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3664 * Format is number of outer loops in the 16 MSB, sample
3669 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3670 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3671 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3672 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3673 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3674 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3676 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3677 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3679 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3680 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3682 writel(reg, &sdr_ctrl->phy_ctrl0);
3685 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3687 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3688 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3689 trk_long_idle_sample_count);
3690 writel(reg, &sdr_ctrl->phy_ctrl1);
3693 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3694 trk_long_idle_sample_count >>
3695 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3696 writel(reg, &sdr_ctrl->phy_ctrl2);
3700 * initialize_tracking() - Initialize tracking
3702 * Initialize the register file with usable initial data.
3704 static void initialize_tracking(void)
3707 * Initialize the register file with the correct data.
3708 * Compute usable version of value in case we skip full
3709 * computation later.
3711 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3712 &sdr_reg_file->dtaps_per_ptap);
3714 /* trk_sample_count */
3715 writel(7500, &sdr_reg_file->trk_sample_count);
3717 /* longidle outer loop [15:0] */
3718 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3721 * longidle sample count [31:24]
3722 * trfc, worst case of 933Mhz 4Gb [23:16]
3723 * trcd, worst case [15:8]
3726 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3727 &sdr_reg_file->delays);
3730 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3731 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3732 &sdr_reg_file->trk_rw_mgr_addr);
3734 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3735 &sdr_reg_file->trk_read_dqs_width);
3738 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3739 &sdr_reg_file->trk_rfsh);
3742 int sdram_calibration_full(void)
3744 struct param_type my_param;
3745 struct gbl_type my_gbl;
3748 memset(&my_param, 0, sizeof(my_param));
3749 memset(&my_gbl, 0, sizeof(my_gbl));
3754 /* Set the calibration enabled by default */
3755 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3757 * Only sweep all groups (regardless of fail state) by default
3758 * Set enabled read test by default.
3760 #if DISABLE_GUARANTEED_READ
3761 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3763 /* Initialize the register file */
3764 initialize_reg_file();
3766 /* Initialize any PHY CSR */
3767 initialize_hps_phy();
3769 scc_mgr_initialize();
3771 initialize_tracking();
3773 printf("%s: Preparing to start memory calibration\n", __FILE__);
3775 debug("%s:%d\n", __func__, __LINE__);
3776 debug_cond(DLEVEL == 1,
3777 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3778 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3779 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3780 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3781 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3782 debug_cond(DLEVEL == 1,
3783 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3784 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3785 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3786 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3787 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3788 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3789 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3790 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3791 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3792 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3793 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3794 IO_IO_OUT2_DELAY_MAX);
3795 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3796 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3798 hc_initialize_rom_data();
3800 /* update info for sims */
3801 reg_file_set_stage(CAL_STAGE_NIL);
3802 reg_file_set_group(0);
3805 * Load global needed for those actions that require
3806 * some dynamic calibration support.
3808 dyn_calib_steps = STATIC_CALIB_STEPS;
3810 * Load global to allow dynamic selection of delay loop settings
3811 * based on calibration mode.
3813 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3814 skip_delay_mask = 0xff;
3816 skip_delay_mask = 0x0;
3818 pass = run_mem_calibrate();
3819 debug_mem_calibrate(pass);