2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
10 #include "sequencer.h"
11 #include "sequencer_auto.h"
12 #include "sequencer_auto_ac_init.h"
13 #include "sequencer_auto_inst_init.h"
14 #include "sequencer_defines.h"
16 static void scc_mgr_load_dqs_for_write_group(uint32_t write_group);
18 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
19 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
21 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
22 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
24 static struct socfpga_sdr_reg_file *sdr_reg_file =
25 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
27 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
28 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
30 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
31 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
33 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
34 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
36 static struct socfpga_data_mgr *data_mgr =
37 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
39 static struct socfpga_sdr_ctrl *sdr_ctrl =
40 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
45 * In order to reduce ROM size, most of the selectable calibration steps are
46 * decided at compile time based on the user's calibration mode selection,
47 * as captured by the STATIC_CALIB_STEPS selection below.
49 * However, to support simulation-time selection of fast simulation mode, where
50 * we skip everything except the bare minimum, we need a few of the steps to
51 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
52 * check, which is based on the rtl-supplied value, or we dynamically compute
53 * the value to use based on the dynamically-chosen calibration mode
57 #define STATIC_IN_RTL_SIM 0
58 #define STATIC_SKIP_DELAY_LOOPS 0
60 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
61 STATIC_SKIP_DELAY_LOOPS)
63 /* calibration steps requested by the rtl */
64 uint16_t dyn_calib_steps;
67 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
68 * instead of static, we use boolean logic to select between
69 * non-skip and skip values
71 * The mask is set to include all bits when not-skipping, but is
75 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
77 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
78 ((non_skip_value) & skip_delay_mask)
81 struct param_type *param;
82 uint32_t curr_shadow_reg;
84 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
85 uint32_t write_group, uint32_t use_dm,
86 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
88 static void set_failing_group_stage(uint32_t group, uint32_t stage,
92 * Only set the global stage if there was not been any other
95 if (gbl->error_stage == CAL_STAGE_NIL) {
96 gbl->error_substage = substage;
97 gbl->error_stage = stage;
98 gbl->error_group = group;
102 static void reg_file_set_group(uint32_t set_group)
104 /* Read the current group and stage */
105 uint32_t cur_stage_group = readl(&sdr_reg_file->cur_stage);
107 /* Clear the group */
108 cur_stage_group &= 0x0000FFFF;
111 cur_stage_group |= (set_group << 16);
113 /* Write the data back */
114 writel(cur_stage_group, &sdr_reg_file->cur_stage);
117 static void reg_file_set_stage(uint32_t set_stage)
119 /* Read the current group and stage */
120 uint32_t cur_stage_group = readl(&sdr_reg_file->cur_stage);
122 /* Clear the stage and substage */
123 cur_stage_group &= 0xFFFF0000;
126 cur_stage_group |= (set_stage & 0x000000FF);
128 /* Write the data back */
129 writel(cur_stage_group, &sdr_reg_file->cur_stage);
132 static void reg_file_set_sub_stage(uint32_t set_sub_stage)
134 /* Read the current group and stage */
135 uint32_t cur_stage_group = readl(&sdr_reg_file->cur_stage);
137 /* Clear the substage */
138 cur_stage_group &= 0xFFFF00FF;
140 /* Set the sub stage */
141 cur_stage_group |= ((set_sub_stage << 8) & 0x0000FF00);
143 /* Write the data back */
144 writel(cur_stage_group, &sdr_reg_file->cur_stage);
147 static void initialize(void)
149 debug("%s:%d\n", __func__, __LINE__);
150 /* USER calibration has control over path to memory */
152 * In Hard PHY this is a 2-bit control:
156 writel(0x3, &phy_mgr_cfg->mux_sel);
158 /* USER memory clock is not stable we begin initialization */
159 writel(0, &phy_mgr_cfg->reset_mem_stbl);
161 /* USER calibration status all set to zero */
162 writel(0, &phy_mgr_cfg->cal_status);
164 writel(0, &phy_mgr_cfg->cal_debug_info);
166 if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
167 param->read_correct_mask_vg = ((uint32_t)1 <<
168 (RW_MGR_MEM_DQ_PER_READ_DQS /
169 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
170 param->write_correct_mask_vg = ((uint32_t)1 <<
171 (RW_MGR_MEM_DQ_PER_READ_DQS /
172 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
173 param->read_correct_mask = ((uint32_t)1 <<
174 RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
175 param->write_correct_mask = ((uint32_t)1 <<
176 RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
177 param->dm_correct_mask = ((uint32_t)1 <<
178 (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH))
183 static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
185 uint32_t odt_mask_0 = 0;
186 uint32_t odt_mask_1 = 0;
187 uint32_t cs_and_odt_mask;
189 if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
190 if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
198 } else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
200 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
201 /* - Dual-Slot , Single-Rank
202 * (1 chip-select per DIMM)
204 * - RDIMM, 4 total CS (2 CS per DIMM)
206 * Since MEM_NUMBER_OF_RANKS is 2 they are
208 * with 2 CS each (special for RDIMM)
209 * Read: Turn on ODT on the opposite rank
210 * Write: Turn on ODT on all ranks
212 odt_mask_0 = 0x3 & ~(1 << rank);
216 * USER - Single-Slot , Dual-rank DIMMs
217 * (2 chip-selects per DIMM)
218 * USER Read: Turn on ODT off on all ranks
219 * USER Write: Turn on ODT on active rank
222 odt_mask_1 = 0x3 & (1 << rank);
227 * ----------+-----------------------+
230 * Read From +-----------------------+
231 * Rank | 3 | 2 | 1 | 0 |
232 * ----------+-----+-----+-----+-----+
233 * 0 | 0 | 1 | 0 | 0 |
234 * 1 | 1 | 0 | 0 | 0 |
235 * 2 | 0 | 0 | 0 | 1 |
236 * 3 | 0 | 0 | 1 | 0 |
237 * ----------+-----+-----+-----+-----+
240 * ----------+-----------------------+
243 * Write To +-----------------------+
244 * Rank | 3 | 2 | 1 | 0 |
245 * ----------+-----+-----+-----+-----+
246 * 0 | 0 | 1 | 0 | 1 |
247 * 1 | 1 | 0 | 1 | 0 |
248 * 2 | 0 | 1 | 0 | 1 |
249 * 3 | 1 | 0 | 1 | 0 |
250 * ----------+-----+-----+-----+-----+
277 (0xFF & ~(1 << rank)) |
278 ((0xFF & odt_mask_0) << 8) |
279 ((0xFF & odt_mask_1) << 16);
280 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
281 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
284 static void scc_mgr_initialize(void)
286 u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_RFILE_OFFSET;
289 * Clear register file for HPS
290 * 16 (2^4) is the size of the full register file in the scc mgr:
291 * RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
292 * MEM_IF_READ_DQS_WIDTH - 1) + 1;
295 for (i = 0; i < 16; i++) {
296 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
297 __func__, __LINE__, i);
298 writel(0, addr + (i << 2));
302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,
305 u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
307 /* Load the setting in the SCC manager */
308 writel(delay, addr + (read_group << 2));
311 static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group,
314 u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
316 writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
319 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
321 u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_PHASE_OFFSET;
323 /* Load the setting in the SCC manager */
324 writel(phase, addr + (read_group << 2));
327 static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
331 uint32_t update_scan_chains;
333 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
334 r += NUM_RANKS_PER_SHADOW_REG) {
336 * USER although the h/w doesn't support different phases per
337 * shadow register, for simplicity our scc manager modeling
338 * keeps different phase settings per shadow reg, and it's
339 * important for us to keep them in sync to match h/w.
340 * for efficiency, the scan chain update should occur only
343 update_scan_chains = (r == 0) ? 1 : 0;
345 scc_mgr_set_dqs_en_phase(read_group, phase);
347 if (update_scan_chains) {
348 writel(read_group, &sdr_scc_mgr->dqs_ena);
349 writel(0, &sdr_scc_mgr->update);
354 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group,
357 u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQDQS_OUT_PHASE_OFFSET;
359 /* Load the setting in the SCC manager */
360 writel(phase, addr + (write_group << 2));
363 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
367 uint32_t update_scan_chains;
369 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
370 r += NUM_RANKS_PER_SHADOW_REG) {
372 * USER although the h/w doesn't support different phases per
373 * shadow register, for simplicity our scc manager modeling
374 * keeps different phase settings per shadow reg, and it's
375 * important for us to keep them in sync to match h/w.
376 * for efficiency, the scan chain update should occur only
379 update_scan_chains = (r == 0) ? 1 : 0;
381 scc_mgr_set_dqdqs_output_phase(write_group, phase);
383 if (update_scan_chains) {
384 writel(write_group, &sdr_scc_mgr->dqs_ena);
385 writel(0, &sdr_scc_mgr->update);
390 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
392 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_DELAY_OFFSET;
394 /* Load the setting in the SCC manager */
395 writel(delay + IO_DQS_EN_DELAY_OFFSET, addr +
399 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
404 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
405 r += NUM_RANKS_PER_SHADOW_REG) {
406 scc_mgr_set_dqs_en_delay(read_group, delay);
408 writel(read_group, &sdr_scc_mgr->dqs_ena);
410 * In shadow register mode, the T11 settings are stored in
411 * registers in the core, which are updated by the DQS_ENA
412 * signals. Not issuing the SCC_MGR_UPD command allows us to
413 * save lots of rank switching overhead, by calling
414 * select_shadow_regs_for_update with update_scan_chains
417 writel(0, &sdr_scc_mgr->update);
420 * In shadow register mode, the T11 settings are stored in
421 * registers in the core, which are updated by the DQS_ENA
422 * signals. Not issuing the SCC_MGR_UPD command allows us to
423 * save lots of rank switching overhead, by calling
424 * select_shadow_regs_for_update with update_scan_chains
427 writel(0, &sdr_scc_mgr->update);
430 static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
433 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_OCT_OUT1_DELAY_OFFSET;
436 * Load the setting in the SCC manager
437 * Although OCT affects only write data, the OCT delay is controlled
438 * by the DQS logic block which is instantiated once per read group.
439 * For protocols where a write group consists of multiple read groups,
440 * the setting must be set multiple times.
442 for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
443 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
444 read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
445 RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
446 writel(delay, addr + (read_group << 2));
449 static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
450 uint32_t dq_in_group, uint32_t delay)
452 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
454 /* Load the setting in the SCC manager */
455 writel(delay, addr + (dq_in_group << 2));
458 static void scc_mgr_set_dq_in_delay(uint32_t write_group,
459 uint32_t dq_in_group, uint32_t delay)
461 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
463 /* Load the setting in the SCC manager */
464 writel(delay, addr + (dq_in_group << 2));
467 static void scc_mgr_set_hhp_extras(void)
470 * Load the fixed setting in the SCC manager
471 * bits: 0:0 = 1'b1 - dqs bypass
472 * bits: 1:1 = 1'b1 - dq bypass
473 * bits: 4:2 = 3'b001 - rfifo_mode
474 * bits: 6:5 = 2'b01 - rfifo clock_select
475 * bits: 7:7 = 1'b0 - separate gating from ungating setting
476 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
478 uint32_t value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0);
479 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_GLOBALS_OFFSET;
481 writel(value, addr + SCC_MGR_HHP_EXTRAS_OFFSET);
484 static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
487 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
489 /* Load the setting in the SCC manager */
490 writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
493 static void scc_mgr_set_dm_out1_delay(uint32_t write_group,
494 uint32_t dm, uint32_t delay)
496 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
498 /* Load the setting in the SCC manager */
500 ((RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm) << 2));
504 * USER Zero all DQS config
505 * TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
507 static void scc_mgr_zero_all(void)
512 * USER Zero all DQS config settings, across all groups and all
515 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
516 NUM_RANKS_PER_SHADOW_REG) {
517 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
519 * The phases actually don't exist on a per-rank basis,
520 * but there's no harm updating them several times, so
521 * let's keep the code simple.
523 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
524 scc_mgr_set_dqs_en_phase(i, 0);
525 scc_mgr_set_dqs_en_delay(i, 0);
528 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
529 scc_mgr_set_dqdqs_output_phase(i, 0);
530 /* av/cv don't have out2 */
531 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
535 /* multicast to all DQS group enables */
536 writel(0xff, &sdr_scc_mgr->dqs_ena);
537 writel(0, &sdr_scc_mgr->update);
540 static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
542 /* mode = 0 : Do NOT bypass - Half Rate Mode */
543 /* mode = 1 : Bypass - Full Rate Mode */
545 /* only need to set once for all groups, pins, dq, dqs, dm */
546 if (write_group == 0) {
547 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", __func__,
549 scc_mgr_set_hhp_extras();
550 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
553 /* multicast to all DQ enables */
554 writel(0xff, &sdr_scc_mgr->dq_ena);
555 writel(0xff, &sdr_scc_mgr->dm_ena);
557 /* update current DQS IO enable */
558 writel(0, &sdr_scc_mgr->dqs_io_ena);
560 /* update the DQS logic */
561 writel(write_group, &sdr_scc_mgr->dqs_ena);
564 writel(0, &sdr_scc_mgr->update);
567 static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
572 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
573 NUM_RANKS_PER_SHADOW_REG) {
574 /* Zero all DQ config settings */
575 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
576 scc_mgr_set_dq_out1_delay(write_group, i, 0);
578 scc_mgr_set_dq_in_delay(write_group, i, 0);
581 /* multicast to all DQ enables */
582 writel(0xff, &sdr_scc_mgr->dq_ena);
584 /* Zero all DM config settings */
585 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
586 scc_mgr_set_dm_out1_delay(write_group, i, 0);
589 /* multicast to all DM enables */
590 writel(0xff, &sdr_scc_mgr->dm_ena);
592 /* zero all DQS io settings */
594 scc_mgr_set_dqs_io_in_delay(write_group, 0);
595 /* av/cv don't have out2 */
596 scc_mgr_set_dqs_out1_delay(write_group, IO_DQS_OUT_RESERVE);
597 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
598 scc_mgr_load_dqs_for_write_group(write_group);
600 /* multicast to all DQS IO enables (only 1) */
601 writel(0, &sdr_scc_mgr->dqs_io_ena);
603 /* hit update to zero everything */
604 writel(0, &sdr_scc_mgr->update);
608 /* load up dqs config settings */
609 static void scc_mgr_load_dqs(uint32_t dqs)
611 writel(dqs, &sdr_scc_mgr->dqs_ena);
614 static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
617 uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
619 * Although OCT affects only write data, the OCT delay is controlled
620 * by the DQS logic block which is instantiated once per read group.
621 * For protocols where a write group consists of multiple read groups,
622 * the setting must be scanned multiple times.
624 for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
625 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
626 read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
627 RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
628 writel(read_group, addr);
631 /* load up dqs io config settings */
632 static void scc_mgr_load_dqs_io(void)
634 writel(0, &sdr_scc_mgr->dqs_io_ena);
637 /* load up dq config settings */
638 static void scc_mgr_load_dq(uint32_t dq_in_group)
640 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
643 /* load up dm config settings */
644 static void scc_mgr_load_dm(uint32_t dm)
646 writel(dm, &sdr_scc_mgr->dm_ena);
650 * apply and load a particular input delay for the DQ pins in a group
651 * group_bgn is the index of the first dq pin (in the write group)
653 static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group,
654 uint32_t group_bgn, uint32_t delay)
658 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
659 scc_mgr_set_dq_in_delay(write_group, p, delay);
664 /* apply and load a particular output delay for the DQ pins in a group */
665 static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group,
671 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
672 scc_mgr_set_dq_out1_delay(write_group, i, delay1);
677 /* apply and load a particular output delay for the DM pins in a group */
678 static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group,
683 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
684 scc_mgr_set_dm_out1_delay(write_group, i, delay1);
690 /* apply and load delay on both DQS and OCT out1 */
691 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
694 scc_mgr_set_dqs_out1_delay(write_group, delay);
695 scc_mgr_load_dqs_io();
697 scc_mgr_set_oct_out1_delay(write_group, delay);
698 scc_mgr_load_dqs_for_write_group(write_group);
701 /* apply a delay to the entire output side: DQ, DM, DQS, OCT */
702 static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group,
706 uint32_t i, p, new_delay;
709 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
710 new_delay = READ_SCC_DQ_OUT2_DELAY;
713 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
714 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQ[%u,%u]:\
715 %u > %lu => %lu", __func__, __LINE__,
716 write_group, group_bgn, delay, i, p, new_delay,
717 (long unsigned int)IO_IO_OUT2_DELAY_MAX,
718 (long unsigned int)IO_IO_OUT2_DELAY_MAX);
719 new_delay = IO_IO_OUT2_DELAY_MAX;
726 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
727 new_delay = READ_SCC_DM_IO_OUT2_DELAY;
730 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
731 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DM[%u]:\
732 %u > %lu => %lu\n", __func__, __LINE__,
733 write_group, group_bgn, delay, i, new_delay,
734 (long unsigned int)IO_IO_OUT2_DELAY_MAX,
735 (long unsigned int)IO_IO_OUT2_DELAY_MAX);
736 new_delay = IO_IO_OUT2_DELAY_MAX;
743 new_delay = READ_SCC_DQS_IO_OUT2_DELAY;
746 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
747 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
748 " adding %u to OUT1\n", __func__, __LINE__,
749 write_group, group_bgn, delay, new_delay,
750 IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
751 new_delay - IO_IO_OUT2_DELAY_MAX);
752 scc_mgr_set_dqs_out1_delay(write_group, new_delay -
753 IO_IO_OUT2_DELAY_MAX);
754 new_delay = IO_IO_OUT2_DELAY_MAX;
757 scc_mgr_load_dqs_io();
760 new_delay = READ_SCC_OCT_OUT2_DELAY;
763 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
764 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
765 " adding %u to OUT1\n", __func__, __LINE__,
766 write_group, group_bgn, delay, new_delay,
767 IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
768 new_delay - IO_IO_OUT2_DELAY_MAX);
769 scc_mgr_set_oct_out1_delay(write_group, new_delay -
770 IO_IO_OUT2_DELAY_MAX);
771 new_delay = IO_IO_OUT2_DELAY_MAX;
774 scc_mgr_load_dqs_for_write_group(write_group);
778 * USER apply a delay to the entire output side (DQ, DM, DQS, OCT)
781 static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
782 uint32_t write_group, uint32_t group_bgn, uint32_t delay)
786 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
787 r += NUM_RANKS_PER_SHADOW_REG) {
788 scc_mgr_apply_group_all_out_delay_add(write_group,
790 writel(0, &sdr_scc_mgr->update);
794 /* optimization used to recover some slots in ddr3 inst_rom */
795 /* could be applied to other protocols if we wanted to */
796 static void set_jump_as_return(void)
799 * to save space, we replace return with jump to special shared
800 * RETURN instruction so we set the counter to large value so that
803 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
804 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
808 * should always use constants as argument to ensure all computations are
809 * performed at compile time
811 static void delay_for_n_mem_clocks(const uint32_t clocks)
818 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
821 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
822 /* scale (rounding up) to get afi clocks */
825 * Note, we don't bother accounting for being off a little bit
826 * because of a few extra instructions in outer loops
827 * Note, the loops have a test at the end, and do the test before
828 * the decrement, and so always perform the loop
829 * 1 time more than the counter value
831 if (afi_clocks == 0) {
833 } else if (afi_clocks <= 0x100) {
834 inner = afi_clocks-1;
837 } else if (afi_clocks <= 0x10000) {
839 outer = (afi_clocks-1) >> 8;
844 c_loop = (afi_clocks-1) >> 16;
848 * rom instructions are structured as follows:
850 * IDLE_LOOP2: jnz cntr0, TARGET_A
851 * IDLE_LOOP1: jnz cntr1, TARGET_B
854 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
855 * TARGET_B is set to IDLE_LOOP2 as well
857 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
858 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
860 * a little confusing, but it helps save precious space in the inst_rom
861 * and sequencer rom and keeps the delays more accurate and reduces
864 if (afi_clocks <= 0x100) {
865 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
866 &sdr_rw_load_mgr_regs->load_cntr1);
868 writel(RW_MGR_IDLE_LOOP1,
869 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
871 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
872 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
874 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
875 &sdr_rw_load_mgr_regs->load_cntr0);
877 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
878 &sdr_rw_load_mgr_regs->load_cntr1);
880 writel(RW_MGR_IDLE_LOOP2,
881 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
883 writel(RW_MGR_IDLE_LOOP2,
884 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
886 /* hack to get around compiler not being smart enough */
887 if (afi_clocks <= 0x10000) {
888 /* only need to run once */
889 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
890 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
893 writel(RW_MGR_IDLE_LOOP2,
894 SDR_PHYGRP_RWMGRGRP_ADDRESS |
895 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
896 } while (c_loop-- != 0);
899 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
902 static void rw_mgr_mem_initialize(void)
905 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
906 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
908 debug("%s:%d\n", __func__, __LINE__);
910 /* The reset / cke part of initialization is broadcasted to all ranks */
911 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
912 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
915 * Here's how you load register for a loop
916 * Counters are located @ 0x800
917 * Jump address are located @ 0xC00
918 * For both, registers 0 to 3 are selected using bits 3 and 2, like
919 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
920 * I know this ain't pretty, but Avalon bus throws away the 2 least
924 /* start with memory RESET activated */
929 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
930 * If a and b are the number of iteration in 2 nested loops
931 * it takes the following number of cycles to complete the operation:
932 * number_of_cycles = ((2 + n) * a + 2) * b
933 * where n is the number of instruction in the inner loop
934 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
939 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
940 &sdr_rw_load_mgr_regs->load_cntr0);
941 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
942 &sdr_rw_load_mgr_regs->load_cntr1);
943 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
944 &sdr_rw_load_mgr_regs->load_cntr2);
946 /* Load jump address */
947 writel(RW_MGR_INIT_RESET_0_CKE_0,
948 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
949 writel(RW_MGR_INIT_RESET_0_CKE_0,
950 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
951 writel(RW_MGR_INIT_RESET_0_CKE_0,
952 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
954 /* Execute count instruction */
955 writel(RW_MGR_INIT_RESET_0_CKE_0, grpaddr);
957 /* indicate that memory is stable */
958 writel(1, &phy_mgr_cfg->reset_mem_stbl);
961 * transition the RESET to high
966 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
967 * If a and b are the number of iteration in 2 nested loops
968 * it takes the following number of cycles to complete the operation
969 * number_of_cycles = ((2 + n) * a + 2) * b
970 * where n is the number of instruction in the inner loop
971 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
976 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
977 &sdr_rw_load_mgr_regs->load_cntr0);
978 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
979 &sdr_rw_load_mgr_regs->load_cntr1);
980 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
981 &sdr_rw_load_mgr_regs->load_cntr2);
983 /* Load jump address */
984 writel(RW_MGR_INIT_RESET_1_CKE_0,
985 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
986 writel(RW_MGR_INIT_RESET_1_CKE_0,
987 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
988 writel(RW_MGR_INIT_RESET_1_CKE_0,
989 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
991 writel(RW_MGR_INIT_RESET_1_CKE_0, grpaddr);
993 /* bring up clock enable */
995 /* tXRP < 250 ck cycles */
996 delay_for_n_mem_clocks(250);
998 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
999 if (param->skip_ranks[r]) {
1000 /* request to skip the rank */
1005 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
1008 * USER Use Mirror-ed commands for odd ranks if address
1011 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
1012 set_jump_as_return();
1013 writel(RW_MGR_MRS2_MIRR, grpaddr);
1014 delay_for_n_mem_clocks(4);
1015 set_jump_as_return();
1016 writel(RW_MGR_MRS3_MIRR, grpaddr);
1017 delay_for_n_mem_clocks(4);
1018 set_jump_as_return();
1019 writel(RW_MGR_MRS1_MIRR, grpaddr);
1020 delay_for_n_mem_clocks(4);
1021 set_jump_as_return();
1022 writel(RW_MGR_MRS0_DLL_RESET_MIRR, grpaddr);
1024 set_jump_as_return();
1025 writel(RW_MGR_MRS2, grpaddr);
1026 delay_for_n_mem_clocks(4);
1027 set_jump_as_return();
1028 writel(RW_MGR_MRS3, grpaddr);
1029 delay_for_n_mem_clocks(4);
1030 set_jump_as_return();
1031 writel(RW_MGR_MRS1, grpaddr);
1032 set_jump_as_return();
1033 writel(RW_MGR_MRS0_DLL_RESET, grpaddr);
1035 set_jump_as_return();
1036 writel(RW_MGR_ZQCL, grpaddr);
1038 /* tZQinit = tDLLK = 512 ck cycles */
1039 delay_for_n_mem_clocks(512);
1044 * At the end of calibration we have to program the user settings in, and
1045 * USER hand off the memory to the user.
1047 static void rw_mgr_mem_handoff(void)
1050 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1051 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1053 debug("%s:%d\n", __func__, __LINE__);
1054 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
1055 if (param->skip_ranks[r])
1056 /* request to skip the rank */
1059 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
1061 /* precharge all banks ... */
1062 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
1064 /* load up MR settings specified by user */
1067 * Use Mirror-ed commands for odd ranks if address
1070 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
1071 set_jump_as_return();
1072 writel(RW_MGR_MRS2_MIRR, grpaddr);
1073 delay_for_n_mem_clocks(4);
1074 set_jump_as_return();
1075 writel(RW_MGR_MRS3_MIRR, grpaddr);
1076 delay_for_n_mem_clocks(4);
1077 set_jump_as_return();
1078 writel(RW_MGR_MRS1_MIRR, grpaddr);
1079 delay_for_n_mem_clocks(4);
1080 set_jump_as_return();
1081 writel(RW_MGR_MRS0_USER_MIRR, grpaddr);
1083 set_jump_as_return();
1084 writel(RW_MGR_MRS2, grpaddr);
1085 delay_for_n_mem_clocks(4);
1086 set_jump_as_return();
1087 writel(RW_MGR_MRS3, grpaddr);
1088 delay_for_n_mem_clocks(4);
1089 set_jump_as_return();
1090 writel(RW_MGR_MRS1, grpaddr);
1091 delay_for_n_mem_clocks(4);
1092 set_jump_as_return();
1093 writel(RW_MGR_MRS0_USER, grpaddr);
1096 * USER need to wait tMOD (12CK or 15ns) time before issuing
1097 * other commands, but we will have plenty of NIOS cycles before
1098 * actual handoff so its okay.
1104 * performs a guaranteed read on the patterns we are going to use during a
1105 * read test to ensure memory works
1107 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1108 uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1112 uint32_t correct_mask_vg;
1113 uint32_t tmp_bit_chk;
1114 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1115 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1117 uint32_t base_rw_mgr;
1119 *bit_chk = param->read_correct_mask;
1120 correct_mask_vg = param->read_correct_mask_vg;
1122 for (r = rank_bgn; r < rank_end; r++) {
1123 if (param->skip_ranks[r])
1124 /* request to skip the rank */
1128 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1130 /* Load up a constant bursts of read commands */
1131 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1132 writel(RW_MGR_GUARANTEED_READ,
1133 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1135 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1136 writel(RW_MGR_GUARANTEED_READ_CONT,
1137 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1140 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1141 /* reset the fifos to get pointers to known state */
1143 writel(0, &phy_mgr_cmd->fifo_reset);
1144 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1145 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1147 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1148 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1150 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1151 writel(RW_MGR_GUARANTEED_READ, addr +
1152 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1155 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1156 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1161 *bit_chk &= tmp_bit_chk;
1164 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1165 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1167 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1168 debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1169 %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1170 (long unsigned int)(*bit_chk == param->read_correct_mask));
1171 return *bit_chk == param->read_correct_mask;
1174 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1175 (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1177 return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1178 num_tries, bit_chk, 1);
1181 /* load up the patterns we are going to use during a read test */
1182 static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
1186 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1187 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1189 debug("%s:%d\n", __func__, __LINE__);
1190 for (r = rank_bgn; r < rank_end; r++) {
1191 if (param->skip_ranks[r])
1192 /* request to skip the rank */
1196 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1198 /* Load up a constant bursts */
1199 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1201 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1202 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1204 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1206 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1207 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1209 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1211 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1212 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1214 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1216 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1217 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1219 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1220 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1223 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1227 * try a read and see if it returns correct data back. has dummy reads
1228 * inserted into the mix used to align dqs enable. has more thorough checks
1229 * than the regular read test.
1231 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1232 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1233 uint32_t all_groups, uint32_t all_ranks)
1236 uint32_t correct_mask_vg;
1237 uint32_t tmp_bit_chk;
1238 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1239 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1241 uint32_t base_rw_mgr;
1243 *bit_chk = param->read_correct_mask;
1244 correct_mask_vg = param->read_correct_mask_vg;
1246 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1247 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1249 for (r = rank_bgn; r < rank_end; r++) {
1250 if (param->skip_ranks[r])
1251 /* request to skip the rank */
1255 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1257 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1259 writel(RW_MGR_READ_B2B_WAIT1,
1260 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1262 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1263 writel(RW_MGR_READ_B2B_WAIT2,
1264 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1266 if (quick_read_mode)
1267 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1268 /* need at least two (1+1) reads to capture failures */
1269 else if (all_groups)
1270 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1272 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1274 writel(RW_MGR_READ_B2B,
1275 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1277 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1278 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1279 &sdr_rw_load_mgr_regs->load_cntr3);
1281 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1283 writel(RW_MGR_READ_B2B,
1284 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1287 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1288 /* reset the fifos to get pointers to known state */
1289 writel(0, &phy_mgr_cmd->fifo_reset);
1290 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1291 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1293 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1294 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1297 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1299 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1301 writel(RW_MGR_READ_B2B, addr +
1302 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1305 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1306 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1311 *bit_chk &= tmp_bit_chk;
1314 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1315 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1318 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1319 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1320 (%u == %u) => %lu", __func__, __LINE__, group,
1321 all_groups, *bit_chk, param->read_correct_mask,
1322 (long unsigned int)(*bit_chk ==
1323 param->read_correct_mask));
1324 return *bit_chk == param->read_correct_mask;
1326 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1327 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1328 (%u != %lu) => %lu\n", __func__, __LINE__,
1329 group, all_groups, *bit_chk, (long unsigned int)0,
1330 (long unsigned int)(*bit_chk != 0x00));
1331 return *bit_chk != 0x00;
1335 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1336 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1337 uint32_t all_groups)
1339 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1340 bit_chk, all_groups, 1);
1343 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1345 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1349 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1353 for (i = 0; i < VFIFO_SIZE-1; i++)
1354 rw_mgr_incr_vfifo(grp, v);
1357 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1360 uint32_t fail_cnt = 0;
1361 uint32_t test_status;
1363 for (v = 0; v < VFIFO_SIZE; ) {
1364 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1365 __func__, __LINE__, v);
1366 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1367 (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1375 /* fiddle with FIFO */
1376 rw_mgr_incr_vfifo(grp, &v);
1379 if (v >= VFIFO_SIZE) {
1380 /* no failing read found!! Something must have gone wrong */
1381 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1382 __func__, __LINE__);
1389 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1390 uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1391 uint32_t *v, uint32_t *d, uint32_t *p,
1392 uint32_t *i, uint32_t *max_working_cnt)
1394 uint32_t found_begin = 0;
1395 uint32_t tmp_delay = 0;
1396 uint32_t test_status;
1398 for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1399 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1400 *work_bgn = tmp_delay;
1401 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1403 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1404 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1405 IO_DELAY_PER_OPA_TAP) {
1406 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1409 rw_mgr_mem_calibrate_read_test_all_ranks
1410 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1413 *max_working_cnt = 1;
1422 if (*p > IO_DQS_EN_PHASE_MAX)
1423 /* fiddle with FIFO */
1424 rw_mgr_incr_vfifo(*grp, v);
1431 if (*i >= VFIFO_SIZE) {
1432 /* cannot find working solution */
1433 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1434 ptap/dtap\n", __func__, __LINE__);
1441 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1442 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1443 uint32_t *p, uint32_t *max_working_cnt)
1445 uint32_t found_begin = 0;
1448 /* Special case code for backing up a phase */
1450 *p = IO_DQS_EN_PHASE_MAX;
1451 rw_mgr_decr_vfifo(*grp, v);
1455 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1456 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1458 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1459 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1460 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1462 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1466 *work_bgn = tmp_delay;
1471 /* We have found a working dtap before the ptap found above */
1472 if (found_begin == 1)
1473 (*max_working_cnt)++;
1476 * Restore VFIFO to old state before we decremented it
1480 if (*p > IO_DQS_EN_PHASE_MAX) {
1482 rw_mgr_incr_vfifo(*grp, v);
1485 scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1488 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1489 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1490 uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1493 uint32_t found_end = 0;
1496 *work_end += IO_DELAY_PER_OPA_TAP;
1497 if (*p > IO_DQS_EN_PHASE_MAX) {
1498 /* fiddle with FIFO */
1500 rw_mgr_incr_vfifo(*grp, v);
1503 for (; *i < VFIFO_SIZE + 1; (*i)++) {
1504 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1505 += IO_DELAY_PER_OPA_TAP) {
1506 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1508 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1509 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1513 (*max_working_cnt)++;
1520 if (*p > IO_DQS_EN_PHASE_MAX) {
1521 /* fiddle with FIFO */
1522 rw_mgr_incr_vfifo(*grp, v);
1527 if (*i >= VFIFO_SIZE + 1) {
1528 /* cannot see edge of failing read */
1529 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1530 failed\n", __func__, __LINE__);
1537 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1538 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1539 uint32_t *p, uint32_t *work_mid,
1545 *work_mid = (*work_bgn + *work_end) / 2;
1547 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1548 *work_bgn, *work_end, *work_mid);
1549 /* Get the middle delay to be less than a VFIFO delay */
1550 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1551 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1553 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1554 while (*work_mid > tmp_delay)
1555 *work_mid -= tmp_delay;
1556 debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1559 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1560 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1562 tmp_delay -= IO_DELAY_PER_OPA_TAP;
1563 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1564 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1565 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1567 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1569 scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1570 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1573 * push vfifo until we can successfully calibrate. We can do this
1574 * because the largest possible margin in 1 VFIFO cycle.
1576 for (i = 0; i < VFIFO_SIZE; i++) {
1577 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1579 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1585 /* fiddle with FIFO */
1586 rw_mgr_incr_vfifo(*grp, v);
1589 if (i >= VFIFO_SIZE) {
1590 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1591 failed\n", __func__, __LINE__);
1598 /* find a good dqs enable to use */
1599 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1601 uint32_t v, d, p, i;
1602 uint32_t max_working_cnt;
1604 uint32_t dtaps_per_ptap;
1605 uint32_t work_bgn, work_mid, work_end;
1606 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1608 debug("%s:%d %u\n", __func__, __LINE__, grp);
1610 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1612 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1613 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1615 /* ************************************************************** */
1616 /* * Step 0 : Determine number of delay taps for each phase tap * */
1617 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1619 /* ********************************************************* */
1620 /* * Step 1 : First push vfifo until we get a failing read * */
1621 v = find_vfifo_read(grp, &bit_chk);
1623 max_working_cnt = 0;
1625 /* ******************************************************** */
1626 /* * step 2: find first working phase, increment in ptaps * */
1628 if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1629 &p, &i, &max_working_cnt) == 0)
1632 work_end = work_bgn;
1635 * If d is 0 then the working window covers a phase tap and
1636 * we can follow the old procedure otherwise, we've found the beginning,
1637 * and we need to increment the dtaps until we find the end.
1640 /* ********************************************************* */
1641 /* * step 3a: if we have room, back off by one and
1642 increment in dtaps * */
1644 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1647 /* ********************************************************* */
1648 /* * step 4a: go forward from working phase to non working
1649 phase, increment in ptaps * */
1650 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1651 &i, &max_working_cnt, &work_end) == 0)
1654 /* ********************************************************* */
1655 /* * step 5a: back off one from last, increment in dtaps * */
1657 /* Special case code for backing up a phase */
1659 p = IO_DQS_EN_PHASE_MAX;
1660 rw_mgr_decr_vfifo(grp, &v);
1665 work_end -= IO_DELAY_PER_OPA_TAP;
1666 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1668 /* * The actual increment of dtaps is done outside of
1669 the if/else loop to share code */
1672 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1673 vfifo=%u ptap=%u\n", __func__, __LINE__,
1676 /* ******************************************************* */
1677 /* * step 3-5b: Find the right edge of the window using
1679 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1680 ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1683 work_end = work_bgn;
1685 /* * The actual increment of dtaps is done outside of the
1686 if/else loop to share code */
1688 /* Only here to counterbalance a subtract later on which is
1689 not needed if this branch of the algorithm is taken */
1693 /* The dtap increment to find the failing edge is done here */
1694 for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1695 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1696 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1697 end-2: dtap=%u\n", __func__, __LINE__, d);
1698 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1700 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1707 /* Go back to working dtap */
1709 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1711 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1712 ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1713 v, p, d-1, work_end);
1715 if (work_end < work_bgn) {
1717 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1718 failed\n", __func__, __LINE__);
1722 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1723 __func__, __LINE__, work_bgn, work_end);
1725 /* *************************************************************** */
1727 * * We need to calculate the number of dtaps that equal a ptap
1728 * * To do that we'll back up a ptap and re-find the edge of the
1729 * * window using dtaps
1732 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1733 for tracking\n", __func__, __LINE__);
1735 /* Special case code for backing up a phase */
1737 p = IO_DQS_EN_PHASE_MAX;
1738 rw_mgr_decr_vfifo(grp, &v);
1739 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1740 cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1744 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1745 phase only: v=%u p=%u", __func__, __LINE__,
1749 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1752 * Increase dtap until we first see a passing read (in case the
1753 * window is smaller than a ptap),
1754 * and then a failing read to mark the edge of the window again
1757 /* Find a passing read */
1758 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1759 __func__, __LINE__);
1760 found_passing_read = 0;
1761 found_failing_read = 0;
1762 initial_failing_dtap = d;
1763 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1764 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1765 read d=%u\n", __func__, __LINE__, d);
1766 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1768 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1771 found_passing_read = 1;
1776 if (found_passing_read) {
1777 /* Find a failing read */
1778 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1779 read\n", __func__, __LINE__);
1780 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1781 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1782 testing read d=%u\n", __func__, __LINE__, d);
1783 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1785 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1786 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1787 found_failing_read = 1;
1792 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1793 calculate dtaps", __func__, __LINE__);
1794 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1798 * The dynamically calculated dtaps_per_ptap is only valid if we
1799 * found a passing/failing read. If we didn't, it means d hit the max
1800 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1801 * statically calculated value.
1803 if (found_passing_read && found_failing_read)
1804 dtaps_per_ptap = d - initial_failing_dtap;
1806 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1807 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1808 - %u = %u", __func__, __LINE__, d,
1809 initial_failing_dtap, dtaps_per_ptap);
1811 /* ******************************************** */
1812 /* * step 6: Find the centre of the window * */
1813 if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1814 &work_mid, &work_end) == 0)
1817 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1818 vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1824 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1825 * dq_in_delay values
1828 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1829 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1837 const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1838 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1839 /* we start at zero, so have one less dq to devide among */
1841 debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1844 /* try different dq_in_delays since the dq path is shorter than dqs */
1846 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1847 r += NUM_RANKS_PER_SHADOW_REG) {
1848 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1849 i++, p++, d += delay_step) {
1850 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1851 vfifo_find_dqs_", __func__, __LINE__);
1852 debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1853 write_group, read_group);
1854 debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
1855 scc_mgr_set_dq_in_delay(write_group, p, d);
1858 writel(0, &sdr_scc_mgr->update);
1861 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1863 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1864 en_phase_sweep_dq", __func__, __LINE__);
1865 debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1866 chain to zero\n", write_group, read_group, found);
1868 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1869 r += NUM_RANKS_PER_SHADOW_REG) {
1870 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1872 scc_mgr_set_dq_in_delay(write_group, p, 0);
1875 writel(0, &sdr_scc_mgr->update);
1881 /* per-bit deskew DQ and center */
1882 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1883 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1884 uint32_t use_read_test, uint32_t update_fom)
1886 uint32_t i, p, d, min_index;
1888 * Store these as signed since there are comparisons with
1892 uint32_t sticky_bit_chk;
1893 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1894 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1895 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1897 int32_t orig_mid_min, mid_min;
1898 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1900 int32_t dq_margin, dqs_margin;
1902 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1905 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1907 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1908 start_dqs = readl(addr + (read_group << 2));
1909 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1910 start_dqs_en = readl(addr + ((read_group << 2)
1911 - IO_DQS_EN_DELAY_OFFSET));
1913 /* set the left and right edge of each bit to an illegal value */
1914 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1916 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1917 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1918 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1921 /* Search for the left edge of the window for each bit */
1922 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1923 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1925 writel(0, &sdr_scc_mgr->update);
1928 * Stop searching when the read test doesn't pass AND when
1929 * we've seen a passing read on every bit.
1931 if (use_read_test) {
1932 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1933 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1936 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1939 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1940 (read_group - (write_group *
1941 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1942 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1943 stop = (bit_chk == 0);
1945 sticky_bit_chk = sticky_bit_chk | bit_chk;
1946 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1947 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1948 && %u", __func__, __LINE__, d,
1950 param->read_correct_mask, stop);
1955 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1957 /* Remember a passing test as the
1961 /* If a left edge has not been seen yet,
1962 then a future passing test will mark
1963 this edge as the right edge */
1965 IO_IO_IN_DELAY_MAX + 1) {
1966 right_edge[i] = -(d + 1);
1969 bit_chk = bit_chk >> 1;
1974 /* Reset DQ delay chains to 0 */
1975 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, 0);
1977 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1978 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1979 %d right_edge[%u]: %d\n", __func__, __LINE__,
1980 i, left_edge[i], i, right_edge[i]);
1983 * Check for cases where we haven't found the left edge,
1984 * which makes our assignment of the the right edge invalid.
1985 * Reset it to the illegal value.
1987 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1988 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1989 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1990 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1991 right_edge[%u]: %d\n", __func__, __LINE__,
1996 * Reset sticky bit (except for bits where we have seen
1997 * both the left and right edge).
1999 sticky_bit_chk = sticky_bit_chk << 1;
2000 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
2001 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
2002 sticky_bit_chk = sticky_bit_chk | 1;
2009 /* Search for the right edge of the window for each bit */
2010 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
2011 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
2012 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2013 uint32_t delay = d + start_dqs_en;
2014 if (delay > IO_DQS_EN_DELAY_MAX)
2015 delay = IO_DQS_EN_DELAY_MAX;
2016 scc_mgr_set_dqs_en_delay(read_group, delay);
2018 scc_mgr_load_dqs(read_group);
2020 writel(0, &sdr_scc_mgr->update);
2023 * Stop searching when the read test doesn't pass AND when
2024 * we've seen a passing read on every bit.
2026 if (use_read_test) {
2027 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
2028 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
2031 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2034 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
2035 (read_group - (write_group *
2036 RW_MGR_MEM_IF_READ_DQS_WIDTH /
2037 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
2038 stop = (bit_chk == 0);
2040 sticky_bit_chk = sticky_bit_chk | bit_chk;
2041 stop = stop && (sticky_bit_chk == param->read_correct_mask);
2043 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
2044 %u && %u", __func__, __LINE__, d,
2045 sticky_bit_chk, param->read_correct_mask, stop);
2050 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2052 /* Remember a passing test as
2057 /* If a right edge has not been
2058 seen yet, then a future passing
2059 test will mark this edge as the
2061 if (right_edge[i] ==
2062 IO_IO_IN_DELAY_MAX + 1) {
2063 left_edge[i] = -(d + 1);
2066 /* d = 0 failed, but it passed
2067 when testing the left edge,
2068 so it must be marginal,
2070 if (right_edge[i] ==
2071 IO_IO_IN_DELAY_MAX + 1 &&
2077 /* If a right edge has not been
2078 seen yet, then a future passing
2079 test will mark this edge as the
2081 else if (right_edge[i] ==
2082 IO_IO_IN_DELAY_MAX +
2084 left_edge[i] = -(d + 1);
2089 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2090 d=%u]: ", __func__, __LINE__, d);
2091 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2092 (int)(bit_chk & 1), i, left_edge[i]);
2093 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2095 bit_chk = bit_chk >> 1;
2100 /* Check that all bits have a window */
2101 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2102 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2103 %d right_edge[%u]: %d", __func__, __LINE__,
2104 i, left_edge[i], i, right_edge[i]);
2105 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2106 == IO_IO_IN_DELAY_MAX + 1)) {
2108 * Restore delay chain settings before letting the loop
2109 * in rw_mgr_mem_calibrate_vfifo to retry different
2110 * dqs/ck relationships.
2112 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2113 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2114 scc_mgr_set_dqs_en_delay(read_group,
2117 scc_mgr_load_dqs(read_group);
2118 writel(0, &sdr_scc_mgr->update);
2120 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2121 find edge [%u]: %d %d", __func__, __LINE__,
2122 i, left_edge[i], right_edge[i]);
2123 if (use_read_test) {
2124 set_failing_group_stage(read_group *
2125 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2127 CAL_SUBSTAGE_VFIFO_CENTER);
2129 set_failing_group_stage(read_group *
2130 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2131 CAL_STAGE_VFIFO_AFTER_WRITES,
2132 CAL_SUBSTAGE_VFIFO_CENTER);
2138 /* Find middle of window for each DQ bit */
2139 mid_min = left_edge[0] - right_edge[0];
2141 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2142 mid = left_edge[i] - right_edge[i];
2143 if (mid < mid_min) {
2150 * -mid_min/2 represents the amount that we need to move DQS.
2151 * If mid_min is odd and positive we'll need to add one to
2152 * make sure the rounding in further calculations is correct
2153 * (always bias to the right), so just add 1 for all positive values.
2158 mid_min = mid_min / 2;
2160 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2161 __func__, __LINE__, mid_min, min_index);
2163 /* Determine the amount we can change DQS (which is -mid_min) */
2164 orig_mid_min = mid_min;
2165 new_dqs = start_dqs - mid_min;
2166 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2167 new_dqs = IO_DQS_IN_DELAY_MAX;
2168 else if (new_dqs < 0)
2171 mid_min = start_dqs - new_dqs;
2172 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2175 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2176 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2177 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2178 else if (start_dqs_en - mid_min < 0)
2179 mid_min += start_dqs_en - mid_min;
2181 new_dqs = start_dqs - mid_min;
2183 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2184 new_dqs=%d mid_min=%d\n", start_dqs,
2185 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2188 /* Initialize data for export structures */
2189 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2190 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2192 /* add delay to bring centre of all DQ windows to the same "level" */
2193 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2194 /* Use values before divide by 2 to reduce round off error */
2195 shift_dq = (left_edge[i] - right_edge[i] -
2196 (left_edge[min_index] - right_edge[min_index]))/2 +
2197 (orig_mid_min - mid_min);
2199 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2200 shift_dq[%u]=%d\n", i, shift_dq);
2202 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2203 temp_dq_in_delay1 = readl(addr + (p << 2));
2204 temp_dq_in_delay2 = readl(addr + (i << 2));
2206 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2207 (int32_t)IO_IO_IN_DELAY_MAX) {
2208 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2209 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2210 shift_dq = -(int32_t)temp_dq_in_delay1;
2212 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2213 shift_dq[%u]=%d\n", i, shift_dq);
2214 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2215 scc_mgr_set_dq_in_delay(write_group, p, final_dq[i]);
2218 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2219 left_edge[i] - shift_dq + (-mid_min),
2220 right_edge[i] + shift_dq - (-mid_min));
2221 /* To determine values for export structures */
2222 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2223 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2225 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2226 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2229 final_dqs = new_dqs;
2230 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2231 final_dqs_en = start_dqs_en - mid_min;
2234 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2235 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2236 scc_mgr_load_dqs(read_group);
2240 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2241 scc_mgr_load_dqs(read_group);
2242 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2243 dqs_margin=%d", __func__, __LINE__,
2244 dq_margin, dqs_margin);
2247 * Do not remove this line as it makes sure all of our decisions
2248 * have been applied. Apply the update bit.
2250 writel(0, &sdr_scc_mgr->update);
2252 return (dq_margin >= 0) && (dqs_margin >= 0);
2256 * calibrate the read valid prediction FIFO.
2258 * - read valid prediction will consist of finding a good DQS enable phase,
2259 * DQS enable delay, DQS input phase, and DQS input delay.
2260 * - we also do a per-bit deskew on the DQ lines.
2262 static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
2265 uint32_t p, d, rank_bgn, sr;
2266 uint32_t dtaps_per_ptap;
2269 uint32_t grp_calibrated;
2270 uint32_t write_group, write_test_bgn;
2271 uint32_t failed_substage;
2273 debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
2275 /* update info for sims */
2276 reg_file_set_stage(CAL_STAGE_VFIFO);
2278 write_group = read_group;
2279 write_test_bgn = test_bgn;
2281 /* USER Determine number of delay taps for each phase tap */
2284 while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
2286 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
2291 /* update info for sims */
2292 reg_file_set_group(read_group);
2296 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2297 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2299 for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
2301 * In RLDRAMX we may be messing the delay of pins in
2302 * the same write group but outside of the current read
2303 * the group, but that's ok because we haven't
2304 * calibrated output side yet.
2307 scc_mgr_apply_group_all_out_delay_add_all_ranks
2308 (write_group, write_test_bgn, d);
2311 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
2313 /* set a particular dqdqs phase */
2314 scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
2316 debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
2317 p=%u d=%u\n", __func__, __LINE__,
2321 * Load up the patterns used by read calibration
2322 * using current DQDQS phase.
2324 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2325 if (!(gbl->phy_debug_mode_flags &
2326 PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
2327 if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
2328 (read_group, 1, &bit_chk)) {
2329 debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
2330 __func__, __LINE__);
2331 debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
2339 if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
2340 (write_group, read_group, test_bgn)) {
2342 * USER Read per-bit deskew can be done on a
2343 * per shadow register basis.
2345 for (rank_bgn = 0, sr = 0;
2346 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2347 rank_bgn += NUM_RANKS_PER_SHADOW_REG,
2350 * Determine if this set of ranks
2351 * should be skipped entirely.
2353 if (!param->skip_shadow_regs[sr]) {
2355 * If doing read after write
2356 * calibration, do not update
2357 * FOM, now - do it then.
2359 if (!rw_mgr_mem_calibrate_vfifo_center
2360 (rank_bgn, write_group,
2361 read_group, test_bgn, 1, 0)) {
2364 CAL_SUBSTAGE_VFIFO_CENTER;
2370 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2375 if (grp_calibrated == 0) {
2376 set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
2382 * Reset the delay chains back to zero if they have moved > 1
2383 * (check for > 1 because loop will increase d even when pass in
2387 scc_mgr_zero_group(write_group, write_test_bgn, 1);
2392 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2393 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2396 uint32_t rank_bgn, sr;
2397 uint32_t grp_calibrated;
2398 uint32_t write_group;
2400 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2402 /* update info for sims */
2404 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2405 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2407 write_group = read_group;
2409 /* update info for sims */
2410 reg_file_set_group(read_group);
2413 /* Read per-bit deskew can be done on a per shadow register basis */
2414 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2415 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2416 /* Determine if this set of ranks should be skipped entirely */
2417 if (!param->skip_shadow_regs[sr]) {
2418 /* This is the last calibration round, update FOM here */
2419 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2430 if (grp_calibrated == 0) {
2431 set_failing_group_stage(write_group,
2432 CAL_STAGE_VFIFO_AFTER_WRITES,
2433 CAL_SUBSTAGE_VFIFO_CENTER);
2440 /* Calibrate LFIFO to find smallest read latency */
2441 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2446 debug("%s:%d\n", __func__, __LINE__);
2448 /* update info for sims */
2449 reg_file_set_stage(CAL_STAGE_LFIFO);
2450 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2452 /* Load up the patterns used by read calibration for all ranks */
2453 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2457 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2458 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2459 __func__, __LINE__, gbl->curr_read_lat);
2461 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2469 /* reduce read latency and see if things are working */
2471 gbl->curr_read_lat--;
2472 } while (gbl->curr_read_lat > 0);
2474 /* reset the fifos to get pointers to known state */
2476 writel(0, &phy_mgr_cmd->fifo_reset);
2479 /* add a fudge factor to the read latency that was determined */
2480 gbl->curr_read_lat += 2;
2481 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2482 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2483 read_lat=%u\n", __func__, __LINE__,
2484 gbl->curr_read_lat);
2487 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2488 CAL_SUBSTAGE_READ_LATENCY);
2490 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2491 read_lat=%u\n", __func__, __LINE__,
2492 gbl->curr_read_lat);
2498 * issue write test command.
2499 * two variants are provided. one that just tests a write pattern and
2500 * another that tests datamask functionality.
2502 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2505 uint32_t mcc_instruction;
2506 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2507 ENABLE_SUPER_QUICK_CALIBRATION);
2508 uint32_t rw_wl_nop_cycles;
2512 * Set counter and jump addresses for the right
2513 * number of NOP cycles.
2514 * The number of supported NOP cycles can range from -1 to infinity
2515 * Three different cases are handled:
2517 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2518 * mechanism will be used to insert the right number of NOPs
2520 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2521 * issuing the write command will jump straight to the
2522 * micro-instruction that turns on DQS (for DDRx), or outputs write
2523 * data (for RLD), skipping
2524 * the NOP micro-instruction all together
2526 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2527 * turned on in the same micro-instruction that issues the write
2528 * command. Then we need
2529 * to directly jump to the micro-instruction that sends out the data
2531 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2532 * (2 and 3). One jump-counter (0) is used to perform multiple
2533 * write-read operations.
2534 * one counter left to issue this command in "multiple-group" mode
2537 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2539 if (rw_wl_nop_cycles == -1) {
2541 * CNTR 2 - We want to execute the special write operation that
2542 * turns on DQS right away and then skip directly to the
2543 * instruction that sends out the data. We set the counter to a
2544 * large number so that the jump is always taken.
2546 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2548 /* CNTR 3 - Not used */
2550 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2551 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2552 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2553 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2554 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2556 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2557 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2558 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2559 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2560 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2562 } else if (rw_wl_nop_cycles == 0) {
2564 * CNTR 2 - We want to skip the NOP operation and go straight
2565 * to the DQS enable instruction. We set the counter to a large
2566 * number so that the jump is always taken.
2568 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2570 /* CNTR 3 - Not used */
2572 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2573 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2574 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2576 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2577 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2578 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2582 * CNTR 2 - In this case we want to execute the next instruction
2583 * and NOT take the jump. So we set the counter to 0. The jump
2584 * address doesn't count.
2586 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2587 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2590 * CNTR 3 - Set the nop counter to the number of cycles we
2591 * need to loop for, minus 1.
2593 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2595 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2596 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2597 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2599 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2600 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2601 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2605 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2606 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2608 if (quick_write_mode)
2609 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2611 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2613 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2616 * CNTR 1 - This is used to ensure enough time elapses
2617 * for read data to come back.
2619 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2622 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2623 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2625 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2626 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2629 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2630 writel(mcc_instruction, addr + (group << 2));
2633 /* Test writes, can check for a single bit pass or multiple bit pass */
2634 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2635 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2636 uint32_t *bit_chk, uint32_t all_ranks)
2639 uint32_t correct_mask_vg;
2640 uint32_t tmp_bit_chk;
2642 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2643 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2644 uint32_t addr_rw_mgr;
2645 uint32_t base_rw_mgr;
2647 *bit_chk = param->write_correct_mask;
2648 correct_mask_vg = param->write_correct_mask_vg;
2650 for (r = rank_bgn; r < rank_end; r++) {
2651 if (param->skip_ranks[r]) {
2652 /* request to skip the rank */
2657 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2660 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2661 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2662 /* reset the fifos to get pointers to known state */
2663 writel(0, &phy_mgr_cmd->fifo_reset);
2665 tmp_bit_chk = tmp_bit_chk <<
2666 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2667 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2668 rw_mgr_mem_calibrate_write_test_issue(write_group *
2669 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2672 base_rw_mgr = readl(addr_rw_mgr);
2673 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2677 *bit_chk &= tmp_bit_chk;
2681 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2682 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2683 %u => %lu", write_group, use_dm,
2684 *bit_chk, param->write_correct_mask,
2685 (long unsigned int)(*bit_chk ==
2686 param->write_correct_mask));
2687 return *bit_chk == param->write_correct_mask;
2689 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2690 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2691 write_group, use_dm, *bit_chk);
2692 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2693 (long unsigned int)(*bit_chk != 0));
2694 return *bit_chk != 0x00;
2699 * center all windows. do per-bit-deskew to possibly increase size of
2702 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2703 uint32_t write_group, uint32_t test_bgn)
2705 uint32_t i, p, min_index;
2708 * Store these as signed since there are comparisons with
2712 uint32_t sticky_bit_chk;
2713 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2714 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2716 int32_t mid_min, orig_mid_min;
2717 int32_t new_dqs, start_dqs, shift_dq;
2718 int32_t dq_margin, dqs_margin, dm_margin;
2720 uint32_t temp_dq_out1_delay;
2723 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2727 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2728 start_dqs = readl(addr +
2729 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2731 /* per-bit deskew */
2734 * set the left and right edge of each bit to an illegal value
2735 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2738 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2739 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2740 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2743 /* Search for the left edge of the window for each bit */
2744 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2745 scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
2747 writel(0, &sdr_scc_mgr->update);
2750 * Stop searching when the read test doesn't pass AND when
2751 * we've seen a passing read on every bit.
2753 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2754 0, PASS_ONE_BIT, &bit_chk, 0);
2755 sticky_bit_chk = sticky_bit_chk | bit_chk;
2756 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2757 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2758 == %u && %u [bit_chk= %u ]\n",
2759 d, sticky_bit_chk, param->write_correct_mask,
2765 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2768 * Remember a passing test as the
2774 * If a left edge has not been seen
2775 * yet, then a future passing test will
2776 * mark this edge as the right edge.
2779 IO_IO_OUT1_DELAY_MAX + 1) {
2780 right_edge[i] = -(d + 1);
2783 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2784 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2785 (int)(bit_chk & 1), i, left_edge[i]);
2786 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2788 bit_chk = bit_chk >> 1;
2793 /* Reset DQ delay chains to 0 */
2794 scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, 0);
2796 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2797 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2798 %d right_edge[%u]: %d\n", __func__, __LINE__,
2799 i, left_edge[i], i, right_edge[i]);
2802 * Check for cases where we haven't found the left edge,
2803 * which makes our assignment of the the right edge invalid.
2804 * Reset it to the illegal value.
2806 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2807 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2808 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2809 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2810 right_edge[%u]: %d\n", __func__, __LINE__,
2815 * Reset sticky bit (except for bits where we have
2816 * seen the left edge).
2818 sticky_bit_chk = sticky_bit_chk << 1;
2819 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2820 sticky_bit_chk = sticky_bit_chk | 1;
2826 /* Search for the right edge of the window for each bit */
2827 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2828 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2831 writel(0, &sdr_scc_mgr->update);
2834 * Stop searching when the read test doesn't pass AND when
2835 * we've seen a passing read on every bit.
2837 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2838 0, PASS_ONE_BIT, &bit_chk, 0);
2840 sticky_bit_chk = sticky_bit_chk | bit_chk;
2841 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2843 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2844 %u && %u\n", d, sticky_bit_chk,
2845 param->write_correct_mask, stop);
2849 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2851 /* d = 0 failed, but it passed when
2852 testing the left edge, so it must be
2853 marginal, set it to -1 */
2854 if (right_edge[i] ==
2855 IO_IO_OUT1_DELAY_MAX + 1 &&
2857 IO_IO_OUT1_DELAY_MAX + 1) {
2864 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2867 * Remember a passing test as
2874 * If a right edge has not
2875 * been seen yet, then a future
2876 * passing test will mark this
2877 * edge as the left edge.
2879 if (right_edge[i] ==
2880 IO_IO_OUT1_DELAY_MAX + 1)
2881 left_edge[i] = -(d + 1);
2884 * d = 0 failed, but it passed
2885 * when testing the left edge,
2886 * so it must be marginal, set
2889 if (right_edge[i] ==
2890 IO_IO_OUT1_DELAY_MAX + 1 &&
2892 IO_IO_OUT1_DELAY_MAX + 1)
2895 * If a right edge has not been
2896 * seen yet, then a future
2897 * passing test will mark this
2898 * edge as the left edge.
2900 else if (right_edge[i] ==
2901 IO_IO_OUT1_DELAY_MAX +
2903 left_edge[i] = -(d + 1);
2906 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2907 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2908 (int)(bit_chk & 1), i, left_edge[i]);
2909 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2911 bit_chk = bit_chk >> 1;
2916 /* Check that all bits have a window */
2917 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2918 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2919 %d right_edge[%u]: %d", __func__, __LINE__,
2920 i, left_edge[i], i, right_edge[i]);
2921 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2922 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2923 set_failing_group_stage(test_bgn + i,
2925 CAL_SUBSTAGE_WRITES_CENTER);
2930 /* Find middle of window for each DQ bit */
2931 mid_min = left_edge[0] - right_edge[0];
2933 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2934 mid = left_edge[i] - right_edge[i];
2935 if (mid < mid_min) {
2942 * -mid_min/2 represents the amount that we need to move DQS.
2943 * If mid_min is odd and positive we'll need to add one to
2944 * make sure the rounding in further calculations is correct
2945 * (always bias to the right), so just add 1 for all positive values.
2949 mid_min = mid_min / 2;
2950 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2953 /* Determine the amount we can change DQS (which is -mid_min) */
2954 orig_mid_min = mid_min;
2955 new_dqs = start_dqs;
2957 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2958 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2959 /* Initialize data for export structures */
2960 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2961 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2963 /* add delay to bring centre of all DQ windows to the same "level" */
2964 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2965 /* Use values before divide by 2 to reduce round off error */
2966 shift_dq = (left_edge[i] - right_edge[i] -
2967 (left_edge[min_index] - right_edge[min_index]))/2 +
2968 (orig_mid_min - mid_min);
2970 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2971 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2973 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2974 temp_dq_out1_delay = readl(addr + (i << 2));
2975 if (shift_dq + (int32_t)temp_dq_out1_delay >
2976 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2977 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2978 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2979 shift_dq = -(int32_t)temp_dq_out1_delay;
2981 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2983 scc_mgr_set_dq_out1_delay(write_group, i, temp_dq_out1_delay +
2987 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2988 left_edge[i] - shift_dq + (-mid_min),
2989 right_edge[i] + shift_dq - (-mid_min));
2990 /* To determine values for export structures */
2991 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2992 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2994 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2995 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2999 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3000 writel(0, &sdr_scc_mgr->update);
3003 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3006 * set the left and right edge of each bit to an illegal value,
3007 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3009 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3010 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3011 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3012 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3013 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
3014 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
3015 int32_t win_best = 0;
3017 /* Search for the/part of the window with DM shift */
3018 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3019 scc_mgr_apply_group_dm_out1_delay(write_group, d);
3020 writel(0, &sdr_scc_mgr->update);
3022 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3023 PASS_ALL_BITS, &bit_chk,
3025 /* USE Set current end of the window */
3028 * If a starting edge of our window has not been seen
3029 * this is our current start of the DM window.
3031 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3035 * If current window is bigger than best seen.
3036 * Set best seen to be current window.
3038 if ((end_curr-bgn_curr+1) > win_best) {
3039 win_best = end_curr-bgn_curr+1;
3040 bgn_best = bgn_curr;
3041 end_best = end_curr;
3044 /* We just saw a failing test. Reset temp edge */
3045 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3046 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3051 /* Reset DM delay chains to 0 */
3052 scc_mgr_apply_group_dm_out1_delay(write_group, 0);
3055 * Check to see if the current window nudges up aganist 0 delay.
3056 * If so we need to continue the search by shifting DQS otherwise DQS
3057 * search begins as a new search. */
3058 if (end_curr != 0) {
3059 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3060 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3063 /* Search for the/part of the window with DQS shifts */
3064 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3066 * Note: This only shifts DQS, so are we limiting ourselve to
3067 * width of DQ unnecessarily.
3069 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3072 writel(0, &sdr_scc_mgr->update);
3073 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3074 PASS_ALL_BITS, &bit_chk,
3076 /* USE Set current end of the window */
3079 * If a beginning edge of our window has not been seen
3080 * this is our current begin of the DM window.
3082 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3086 * If current window is bigger than best seen. Set best
3087 * seen to be current window.
3089 if ((end_curr-bgn_curr+1) > win_best) {
3090 win_best = end_curr-bgn_curr+1;
3091 bgn_best = bgn_curr;
3092 end_best = end_curr;
3095 /* We just saw a failing test. Reset temp edge */
3096 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3097 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3099 /* Early exit optimization: if ther remaining delay
3100 chain space is less than already seen largest window
3103 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3109 /* assign left and right edge for cal and reporting; */
3110 left_edge[0] = -1*bgn_best;
3111 right_edge[0] = end_best;
3113 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3114 __LINE__, left_edge[0], right_edge[0]);
3116 /* Move DQS (back to orig) */
3117 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3121 /* Find middle of window for the DM bit */
3122 mid = (left_edge[0] - right_edge[0]) / 2;
3124 /* only move right, since we are not moving DQS/DQ */
3128 /* dm_marign should fail if we never find a window */
3132 dm_margin = left_edge[0] - mid;
3134 scc_mgr_apply_group_dm_out1_delay(write_group, mid);
3135 writel(0, &sdr_scc_mgr->update);
3137 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3138 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3139 right_edge[0], mid, dm_margin);
3141 gbl->fom_out += dq_margin + dqs_margin;
3143 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3144 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3145 dq_margin, dqs_margin, dm_margin);
3148 * Do not remove this line as it makes sure all of our
3149 * decisions have been applied.
3151 writel(0, &sdr_scc_mgr->update);
3152 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3155 /* calibrate the write operations */
3156 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3159 /* update info for sims */
3160 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3162 reg_file_set_stage(CAL_STAGE_WRITES);
3163 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3165 reg_file_set_group(g);
3167 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3168 set_failing_group_stage(g, CAL_STAGE_WRITES,
3169 CAL_SUBSTAGE_WRITES_CENTER);
3176 /* precharge all banks and activate row 0 in bank "000..." and bank "111..." */
3177 static void mem_precharge_and_activate(void)
3181 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3182 if (param->skip_ranks[r]) {
3183 /* request to skip the rank */
3188 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3190 /* precharge all banks ... */
3191 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3192 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3194 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3195 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3196 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3198 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3199 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3200 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3203 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3204 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3208 /* Configure various memory related parameters. */
3209 static void mem_config(void)
3211 uint32_t rlat, wlat;
3212 uint32_t rw_wl_nop_cycles;
3213 uint32_t max_latency;
3215 debug("%s:%d\n", __func__, __LINE__);
3216 /* read in write and read latency */
3217 wlat = readl(&data_mgr->t_wl_add);
3218 wlat += readl(&data_mgr->mem_t_add);
3220 /* WL for hard phy does not include additive latency */
3223 * add addtional write latency to offset the address/command extra
3224 * clock cycle. We change the AC mux setting causing AC to be delayed
3225 * by one mem clock cycle. Only do this for DDR3
3229 rlat = readl(&data_mgr->t_rl_add);
3231 rw_wl_nop_cycles = wlat - 2;
3232 gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
3235 * For AV/CV, lfifo is hardened and always runs at full rate so
3236 * max latency in AFI clocks, used here, is correspondingly smaller.
3238 max_latency = (1<<MAX_LATENCY_COUNT_WIDTH)/1 - 1;
3239 /* configure for a burst length of 8 */
3242 /* Adjust Write Latency for Hard PHY */
3245 /* set a pretty high read latency initially */
3246 gbl->curr_read_lat = rlat + 16;
3248 if (gbl->curr_read_lat > max_latency)
3249 gbl->curr_read_lat = max_latency;
3251 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3253 /* advertise write latency */
3254 gbl->curr_write_lat = wlat;
3255 writel(wlat - 2, &phy_mgr_cfg->afi_wlat);
3257 /* initialize bit slips */
3258 mem_precharge_and_activate();
3261 /* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
3262 static void mem_skip_calibrate(void)
3264 uint32_t vfifo_offset;
3267 debug("%s:%d\n", __func__, __LINE__);
3268 /* Need to update every shadow register set used by the interface */
3269 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3270 r += NUM_RANKS_PER_SHADOW_REG) {
3272 * Set output phase alignment settings appropriate for
3275 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3276 scc_mgr_set_dqs_en_phase(i, 0);
3277 #if IO_DLL_CHAIN_LENGTH == 6
3278 scc_mgr_set_dqdqs_output_phase(i, 6);
3280 scc_mgr_set_dqdqs_output_phase(i, 7);
3285 * Write data arrives to the I/O two cycles before write
3286 * latency is reached (720 deg).
3287 * -> due to bit-slip in a/c bus
3288 * -> to allow board skew where dqs is longer than ck
3289 * -> how often can this happen!?
3290 * -> can claim back some ptaps for high freq
3291 * support if we can relax this, but i digress...
3293 * The write_clk leads mem_ck by 90 deg
3294 * The minimum ptap of the OPA is 180 deg
3295 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3296 * The write_clk is always delayed by 2 ptaps
3298 * Hence, to make DQS aligned to CK, we need to delay
3300 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3302 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3303 * gives us the number of ptaps, which simplies to:
3305 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3307 scc_mgr_set_dqdqs_output_phase(i, (1.25 *
3308 IO_DLL_CHAIN_LENGTH - 2));
3310 writel(0xff, &sdr_scc_mgr->dqs_ena);
3311 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3313 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3314 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3315 SCC_MGR_GROUP_COUNTER_OFFSET);
3317 writel(0xff, &sdr_scc_mgr->dq_ena);
3318 writel(0xff, &sdr_scc_mgr->dm_ena);
3319 writel(0, &sdr_scc_mgr->update);
3322 /* Compensate for simulation model behaviour */
3323 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3324 scc_mgr_set_dqs_bus_in_delay(i, 10);
3325 scc_mgr_load_dqs(i);
3327 writel(0, &sdr_scc_mgr->update);
3330 * ArriaV has hard FIFOs that can only be initialized by incrementing
3333 vfifo_offset = CALIB_VFIFO_OFFSET;
3334 for (j = 0; j < vfifo_offset; j++) {
3335 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3337 writel(0, &phy_mgr_cmd->fifo_reset);
3340 * For ACV with hard lfifo, we get the skip-cal setting from
3341 * generation-time constant.
3343 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3344 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3347 /* Memory calibration entry point */
3348 static uint32_t mem_calibrate(void)
3351 uint32_t rank_bgn, sr;
3352 uint32_t write_group, write_test_bgn;
3353 uint32_t read_group, read_test_bgn;
3354 uint32_t run_groups, current_run;
3355 uint32_t failing_groups = 0;
3356 uint32_t group_failed = 0;
3357 uint32_t sr_failed = 0;
3359 debug("%s:%d\n", __func__, __LINE__);
3360 /* Initialize the data settings */
3362 gbl->error_substage = CAL_SUBSTAGE_NIL;
3363 gbl->error_stage = CAL_STAGE_NIL;
3364 gbl->error_group = 0xff;
3370 uint32_t bypass_mode = 0x1;
3371 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3372 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3373 SCC_MGR_GROUP_COUNTER_OFFSET);
3374 scc_set_bypass_mode(i, bypass_mode);
3377 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3379 * Set VFIFO and LFIFO to instant-on settings in skip
3382 mem_skip_calibrate();
3384 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3386 * Zero all delay chain/phase settings for all
3387 * groups and all shadow register sets.
3391 run_groups = ~param->skip_groups;
3393 for (write_group = 0, write_test_bgn = 0; write_group
3394 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3395 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3396 /* Initialized the group failure */
3399 current_run = run_groups & ((1 <<
3400 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3401 run_groups = run_groups >>
3402 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3404 if (current_run == 0)
3407 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3408 SCC_MGR_GROUP_COUNTER_OFFSET);
3409 scc_mgr_zero_group(write_group, write_test_bgn,
3412 for (read_group = write_group *
3413 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3414 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3416 read_group < (write_group + 1) *
3417 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3418 RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3420 read_group++, read_test_bgn +=
3421 RW_MGR_MEM_DQ_PER_READ_DQS) {
3422 /* Calibrate the VFIFO */
3423 if (!((STATIC_CALIB_STEPS) &
3424 CALIB_SKIP_VFIFO)) {
3425 if (!rw_mgr_mem_calibrate_vfifo
3431 phy_debug_mode_flags &
3432 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3439 /* Calibrate the output side */
3440 if (group_failed == 0) {
3441 for (rank_bgn = 0, sr = 0; rank_bgn
3442 < RW_MGR_MEM_NUMBER_OF_RANKS;
3444 NUM_RANKS_PER_SHADOW_REG,
3447 if (!((STATIC_CALIB_STEPS) &
3448 CALIB_SKIP_WRITES)) {
3449 if ((STATIC_CALIB_STEPS)
3450 & CALIB_SKIP_DELAY_SWEEPS) {
3451 /* not needed in quick mode! */
3454 * Determine if this set of
3455 * ranks should be skipped
3458 if (!param->skip_shadow_regs[sr]) {
3459 if (!rw_mgr_mem_calibrate_writes
3460 (rank_bgn, write_group,
3464 phy_debug_mode_flags &
3465 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3477 if (group_failed == 0) {
3478 for (read_group = write_group *
3479 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3480 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3482 read_group < (write_group + 1)
3483 * RW_MGR_MEM_IF_READ_DQS_WIDTH
3484 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3486 read_group++, read_test_bgn +=
3487 RW_MGR_MEM_DQ_PER_READ_DQS) {
3488 if (!((STATIC_CALIB_STEPS) &
3489 CALIB_SKIP_WRITES)) {
3490 if (!rw_mgr_mem_calibrate_vfifo_end
3491 (read_group, read_test_bgn)) {
3494 if (!(gbl->phy_debug_mode_flags
3495 & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3503 if (group_failed != 0)
3508 * USER If there are any failing groups then report
3511 if (failing_groups != 0)
3514 /* Calibrate the LFIFO */
3515 if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
3517 * If we're skipping groups as part of debug,
3518 * don't calibrate LFIFO.
3520 if (param->skip_groups == 0) {
3521 if (!rw_mgr_mem_calibrate_lfifo())
3529 * Do not remove this line as it makes sure all of our decisions
3530 * have been applied.
3532 writel(0, &sdr_scc_mgr->update);
3536 static uint32_t run_mem_calibrate(void)
3539 uint32_t debug_info;
3541 debug("%s:%d\n", __func__, __LINE__);
3543 /* Reset pass/fail status shown on afi_cal_success/fail */
3544 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3546 /* stop tracking manger */
3547 uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg);
3549 writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
3552 rw_mgr_mem_initialize();
3554 pass = mem_calibrate();
3556 mem_precharge_and_activate();
3557 writel(0, &phy_mgr_cmd->fifo_reset);
3561 * Don't return control of the PHY back to AFI when in debug mode.
3563 if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) {
3564 rw_mgr_mem_handoff();
3566 * In Hard PHY this is a 2-bit control:
3568 * 1: DDIO Mux Select
3570 writel(0x2, &phy_mgr_cfg->mux_sel);
3573 writel(ctrlcfg, &sdr_ctrl->ctrl_cfg);
3576 printf("%s: CALIBRATION PASSED\n", __FILE__);
3581 if (gbl->fom_in > 0xff)
3584 if (gbl->fom_out > 0xff)
3585 gbl->fom_out = 0xff;
3587 /* Update the FOM in the register file */
3588 debug_info = gbl->fom_in;
3589 debug_info |= gbl->fom_out << 8;
3590 writel(debug_info, &sdr_reg_file->fom);
3592 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3593 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3595 printf("%s: CALIBRATION FAILED\n", __FILE__);
3597 debug_info = gbl->error_stage;
3598 debug_info |= gbl->error_substage << 8;
3599 debug_info |= gbl->error_group << 16;
3601 writel(debug_info, &sdr_reg_file->failing_stage);
3602 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3603 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3605 /* Update the failing group/stage in the register file */
3606 debug_info = gbl->error_stage;
3607 debug_info |= gbl->error_substage << 8;
3608 debug_info |= gbl->error_group << 16;
3609 writel(debug_info, &sdr_reg_file->failing_stage);
3616 * hc_initialize_rom_data() - Initialize ROM data
3618 * Initialize ROM data.
3620 static void hc_initialize_rom_data(void)
3624 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3625 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3626 writel(inst_rom_init[i], addr + (i << 2));
3628 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3629 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3630 writel(ac_rom_init[i], addr + (i << 2));
3633 static void initialize_reg_file(void)
3635 /* Initialize the register file with the correct data */
3636 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3637 writel(0, &sdr_reg_file->debug_data_addr);
3638 writel(0, &sdr_reg_file->cur_stage);
3639 writel(0, &sdr_reg_file->fom);
3640 writel(0, &sdr_reg_file->failing_stage);
3641 writel(0, &sdr_reg_file->debug1);
3642 writel(0, &sdr_reg_file->debug2);
3645 static void initialize_hps_phy(void)
3649 * Tracking also gets configured here because it's in the
3652 uint32_t trk_sample_count = 7500;
3653 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3655 * Format is number of outer loops in the 16 MSB, sample
3660 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3661 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3662 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3663 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3664 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3665 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3667 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3668 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3670 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3671 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3673 writel(reg, &sdr_ctrl->phy_ctrl0);
3676 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3678 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3679 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3680 trk_long_idle_sample_count);
3681 writel(reg, &sdr_ctrl->phy_ctrl1);
3684 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3685 trk_long_idle_sample_count >>
3686 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3687 writel(reg, &sdr_ctrl->phy_ctrl2);
3690 static void initialize_tracking(void)
3692 uint32_t concatenated_longidle = 0x0;
3693 uint32_t concatenated_delays = 0x0;
3694 uint32_t concatenated_rw_addr = 0x0;
3695 uint32_t concatenated_refresh = 0x0;
3696 uint32_t trk_sample_count = 7500;
3697 uint32_t dtaps_per_ptap;
3701 * compute usable version of value in case we skip full
3706 while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
3708 tmp_delay += IO_DELAY_PER_DCHAIN_TAP;
3712 concatenated_longidle = concatenated_longidle ^ 10;
3713 /*longidle outer loop */
3714 concatenated_longidle = concatenated_longidle << 16;
3715 concatenated_longidle = concatenated_longidle ^ 100;
3716 /*longidle sample count */
3717 concatenated_delays = concatenated_delays ^ 243;
3718 /* trfc, worst case of 933Mhz 4Gb */
3719 concatenated_delays = concatenated_delays << 8;
3720 concatenated_delays = concatenated_delays ^ 14;
3721 /* trcd, worst case */
3722 concatenated_delays = concatenated_delays << 8;
3723 concatenated_delays = concatenated_delays ^ 10;
3725 concatenated_delays = concatenated_delays << 8;
3726 concatenated_delays = concatenated_delays ^ 4;
3729 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_IDLE;
3730 concatenated_rw_addr = concatenated_rw_addr << 8;
3731 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_ACTIVATE_1;
3732 concatenated_rw_addr = concatenated_rw_addr << 8;
3733 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_SGLE_READ;
3734 concatenated_rw_addr = concatenated_rw_addr << 8;
3735 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_PRECHARGE_ALL;
3737 concatenated_refresh = concatenated_refresh ^ RW_MGR_REFRESH_ALL;
3738 concatenated_refresh = concatenated_refresh << 24;
3739 concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
3741 /* Initialize the register file with the correct data */
3742 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
3743 writel(trk_sample_count, &sdr_reg_file->trk_sample_count);
3744 writel(concatenated_longidle, &sdr_reg_file->trk_longidle);
3745 writel(concatenated_delays, &sdr_reg_file->delays);
3746 writel(concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr);
3747 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, &sdr_reg_file->trk_read_dqs_width);
3748 writel(concatenated_refresh, &sdr_reg_file->trk_rfsh);
3751 int sdram_calibration_full(void)
3753 struct param_type my_param;
3754 struct gbl_type my_gbl;
3761 /* Initialize the debug mode flags */
3762 gbl->phy_debug_mode_flags = 0;
3763 /* Set the calibration enabled by default */
3764 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3766 * Only sweep all groups (regardless of fail state) by default
3767 * Set enabled read test by default.
3769 #if DISABLE_GUARANTEED_READ
3770 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3772 /* Initialize the register file */
3773 initialize_reg_file();
3775 /* Initialize any PHY CSR */
3776 initialize_hps_phy();
3778 scc_mgr_initialize();
3780 initialize_tracking();
3782 /* USER Enable all ranks, groups */
3783 for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++)
3784 param->skip_ranks[i] = 0;
3785 for (i = 0; i < NUM_SHADOW_REGS; ++i)
3786 param->skip_shadow_regs[i] = 0;
3787 param->skip_groups = 0;
3789 printf("%s: Preparing to start memory calibration\n", __FILE__);
3791 debug("%s:%d\n", __func__, __LINE__);
3792 debug_cond(DLEVEL == 1,
3793 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3794 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3795 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3796 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3797 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3798 debug_cond(DLEVEL == 1,
3799 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3800 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3801 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3802 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3803 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3804 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3805 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3806 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3807 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3808 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3809 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3810 IO_IO_OUT2_DELAY_MAX);
3811 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3812 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3814 hc_initialize_rom_data();
3816 /* update info for sims */
3817 reg_file_set_stage(CAL_STAGE_NIL);
3818 reg_file_set_group(0);
3821 * Load global needed for those actions that require
3822 * some dynamic calibration support.
3824 dyn_calib_steps = STATIC_CALIB_STEPS;
3826 * Load global to allow dynamic selection of delay loop settings
3827 * based on calibration mode.
3829 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3830 skip_delay_mask = 0xff;
3832 skip_delay_mask = 0x0;
3834 pass = run_mem_calibrate();
3836 printf("%s: Calibration complete\n", __FILE__);