2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
10 #include "sequencer.h"
11 #include "sequencer_auto.h"
12 #include "sequencer_auto_ac_init.h"
13 #include "sequencer_auto_inst_init.h"
14 #include "sequencer_defines.h"
16 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
17 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
19 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
20 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
22 static struct socfpga_sdr_reg_file *sdr_reg_file =
23 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
25 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
26 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
28 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
29 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
31 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
32 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
34 static struct socfpga_data_mgr *data_mgr =
35 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
37 static struct socfpga_sdr_ctrl *sdr_ctrl =
38 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
43 * In order to reduce ROM size, most of the selectable calibration steps are
44 * decided at compile time based on the user's calibration mode selection,
45 * as captured by the STATIC_CALIB_STEPS selection below.
47 * However, to support simulation-time selection of fast simulation mode, where
48 * we skip everything except the bare minimum, we need a few of the steps to
49 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
50 * check, which is based on the rtl-supplied value, or we dynamically compute
51 * the value to use based on the dynamically-chosen calibration mode
55 #define STATIC_IN_RTL_SIM 0
56 #define STATIC_SKIP_DELAY_LOOPS 0
58 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
59 STATIC_SKIP_DELAY_LOOPS)
61 /* calibration steps requested by the rtl */
62 uint16_t dyn_calib_steps;
65 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
66 * instead of static, we use boolean logic to select between
67 * non-skip and skip values
69 * The mask is set to include all bits when not-skipping, but is
73 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
75 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
76 ((non_skip_value) & skip_delay_mask)
79 struct param_type *param;
80 uint32_t curr_shadow_reg;
82 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
83 uint32_t write_group, uint32_t use_dm,
84 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
86 static void set_failing_group_stage(uint32_t group, uint32_t stage,
90 * Only set the global stage if there was not been any other
93 if (gbl->error_stage == CAL_STAGE_NIL) {
94 gbl->error_substage = substage;
95 gbl->error_stage = stage;
96 gbl->error_group = group;
100 static void reg_file_set_group(u16 set_group)
102 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
105 static void reg_file_set_stage(u8 set_stage)
107 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
110 static void reg_file_set_sub_stage(u8 set_sub_stage)
112 set_sub_stage &= 0xff;
113 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
117 * phy_mgr_initialize() - Initialize PHY Manager
119 * Initialize PHY Manager.
121 static void phy_mgr_initialize(void)
125 debug("%s:%d\n", __func__, __LINE__);
126 /* Calibration has control over path to memory */
128 * In Hard PHY this is a 2-bit control:
132 writel(0x3, &phy_mgr_cfg->mux_sel);
134 /* USER memory clock is not stable we begin initialization */
135 writel(0, &phy_mgr_cfg->reset_mem_stbl);
137 /* USER calibration status all set to zero */
138 writel(0, &phy_mgr_cfg->cal_status);
140 writel(0, &phy_mgr_cfg->cal_debug_info);
142 /* Init params only if we do NOT skip calibration. */
143 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
146 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
147 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
148 param->read_correct_mask_vg = (1 << ratio) - 1;
149 param->write_correct_mask_vg = (1 << ratio) - 1;
150 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
151 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
152 ratio = RW_MGR_MEM_DATA_WIDTH /
153 RW_MGR_MEM_DATA_MASK_WIDTH;
154 param->dm_correct_mask = (1 << ratio) - 1;
157 static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
159 uint32_t odt_mask_0 = 0;
160 uint32_t odt_mask_1 = 0;
161 uint32_t cs_and_odt_mask;
163 if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
164 if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
172 } else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
174 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
175 /* - Dual-Slot , Single-Rank
176 * (1 chip-select per DIMM)
178 * - RDIMM, 4 total CS (2 CS per DIMM)
180 * Since MEM_NUMBER_OF_RANKS is 2 they are
182 * with 2 CS each (special for RDIMM)
183 * Read: Turn on ODT on the opposite rank
184 * Write: Turn on ODT on all ranks
186 odt_mask_0 = 0x3 & ~(1 << rank);
190 * USER - Single-Slot , Dual-rank DIMMs
191 * (2 chip-selects per DIMM)
192 * USER Read: Turn on ODT off on all ranks
193 * USER Write: Turn on ODT on active rank
196 odt_mask_1 = 0x3 & (1 << rank);
201 * ----------+-----------------------+
204 * Read From +-----------------------+
205 * Rank | 3 | 2 | 1 | 0 |
206 * ----------+-----+-----+-----+-----+
207 * 0 | 0 | 1 | 0 | 0 |
208 * 1 | 1 | 0 | 0 | 0 |
209 * 2 | 0 | 0 | 0 | 1 |
210 * 3 | 0 | 0 | 1 | 0 |
211 * ----------+-----+-----+-----+-----+
214 * ----------+-----------------------+
217 * Write To +-----------------------+
218 * Rank | 3 | 2 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
220 * 0 | 0 | 1 | 0 | 1 |
221 * 1 | 1 | 0 | 1 | 0 |
222 * 2 | 0 | 1 | 0 | 1 |
223 * 3 | 1 | 0 | 1 | 0 |
224 * ----------+-----+-----+-----+-----+
251 (0xFF & ~(1 << rank)) |
252 ((0xFF & odt_mask_0) << 8) |
253 ((0xFF & odt_mask_1) << 16);
254 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
255 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
259 * scc_mgr_set() - Set SCC Manager register
260 * @off: Base offset in SCC Manager space
261 * @grp: Read/Write group
262 * @val: Value to be set
264 * This function sets the SCC Manager (Scan Chain Control Manager) register.
266 static void scc_mgr_set(u32 off, u32 grp, u32 val)
268 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
272 * scc_mgr_initialize() - Initialize SCC Manager registers
274 * Initialize SCC Manager registers.
276 static void scc_mgr_initialize(void)
279 * Clear register file for HPS. 16 (2^4) is the size of the
280 * full register file in the scc mgr:
281 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
282 * MEM_IF_READ_DQS_WIDTH - 1);
286 for (i = 0; i < 16; i++) {
287 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
288 __func__, __LINE__, i);
289 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
293 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
295 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
298 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
300 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
303 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
305 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
308 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
310 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
313 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
315 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
319 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
321 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
324 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
326 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
329 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
331 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
335 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
337 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
338 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
342 /* load up dqs config settings */
343 static void scc_mgr_load_dqs(uint32_t dqs)
345 writel(dqs, &sdr_scc_mgr->dqs_ena);
348 /* load up dqs io config settings */
349 static void scc_mgr_load_dqs_io(void)
351 writel(0, &sdr_scc_mgr->dqs_io_ena);
354 /* load up dq config settings */
355 static void scc_mgr_load_dq(uint32_t dq_in_group)
357 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
360 /* load up dm config settings */
361 static void scc_mgr_load_dm(uint32_t dm)
363 writel(dm, &sdr_scc_mgr->dm_ena);
367 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
368 * @off: Base offset in SCC Manager space
369 * @grp: Read/Write group
370 * @val: Value to be set
371 * @update: If non-zero, trigger SCC Manager update for all ranks
373 * This function sets the SCC Manager (Scan Chain Control Manager) register
374 * and optionally triggers the SCC update for all ranks.
376 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
381 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
382 r += NUM_RANKS_PER_SHADOW_REG) {
383 scc_mgr_set(off, grp, val);
385 if (update || (r == 0)) {
386 writel(grp, &sdr_scc_mgr->dqs_ena);
387 writel(0, &sdr_scc_mgr->update);
392 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
395 * USER although the h/w doesn't support different phases per
396 * shadow register, for simplicity our scc manager modeling
397 * keeps different phase settings per shadow reg, and it's
398 * important for us to keep them in sync to match h/w.
399 * for efficiency, the scan chain update should occur only
402 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
403 read_group, phase, 0);
406 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
410 * USER although the h/w doesn't support different phases per
411 * shadow register, for simplicity our scc manager modeling
412 * keeps different phase settings per shadow reg, and it's
413 * important for us to keep them in sync to match h/w.
414 * for efficiency, the scan chain update should occur only
417 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
418 write_group, phase, 0);
421 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
425 * In shadow register mode, the T11 settings are stored in
426 * registers in the core, which are updated by the DQS_ENA
427 * signals. Not issuing the SCC_MGR_UPD command allows us to
428 * save lots of rank switching overhead, by calling
429 * select_shadow_regs_for_update with update_scan_chains
432 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
433 read_group, delay, 1);
434 writel(0, &sdr_scc_mgr->update);
438 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
439 * @write_group: Write group
440 * @delay: Delay value
442 * This function sets the OCT output delay in SCC manager.
444 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
446 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
447 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
448 const int base = write_group * ratio;
451 * Load the setting in the SCC manager
452 * Although OCT affects only write data, the OCT delay is controlled
453 * by the DQS logic block which is instantiated once per read group.
454 * For protocols where a write group consists of multiple read groups,
455 * the setting must be set multiple times.
457 for (i = 0; i < ratio; i++)
458 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
462 * scc_mgr_set_hhp_extras() - Set HHP extras.
464 * Load the fixed setting in the SCC manager HHP extras.
466 static void scc_mgr_set_hhp_extras(void)
469 * Load the fixed setting in the SCC manager
470 * bits: 0:0 = 1'b1 - DQS bypass
471 * bits: 1:1 = 1'b1 - DQ bypass
472 * bits: 4:2 = 3'b001 - rfifo_mode
473 * bits: 6:5 = 2'b01 - rfifo clock_select
474 * bits: 7:7 = 1'b0 - separate gating from ungating setting
475 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
477 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
478 (1 << 2) | (1 << 1) | (1 << 0);
479 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
480 SCC_MGR_HHP_GLOBALS_OFFSET |
481 SCC_MGR_HHP_EXTRAS_OFFSET;
483 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
486 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
491 * scc_mgr_zero_all() - Zero all DQS config
493 * Zero all DQS config.
495 static void scc_mgr_zero_all(void)
500 * USER Zero all DQS config settings, across all groups and all
503 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
504 r += NUM_RANKS_PER_SHADOW_REG) {
505 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
507 * The phases actually don't exist on a per-rank basis,
508 * but there's no harm updating them several times, so
509 * let's keep the code simple.
511 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
512 scc_mgr_set_dqs_en_phase(i, 0);
513 scc_mgr_set_dqs_en_delay(i, 0);
516 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
517 scc_mgr_set_dqdqs_output_phase(i, 0);
518 /* Arria V/Cyclone V don't have out2. */
519 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
523 /* Multicast to all DQS group enables. */
524 writel(0xff, &sdr_scc_mgr->dqs_ena);
525 writel(0, &sdr_scc_mgr->update);
529 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
530 * @write_group: Write group
532 * Set bypass mode and trigger SCC update.
534 static void scc_set_bypass_mode(const u32 write_group)
536 /* Multicast to all DQ enables. */
537 writel(0xff, &sdr_scc_mgr->dq_ena);
538 writel(0xff, &sdr_scc_mgr->dm_ena);
540 /* Update current DQS IO enable. */
541 writel(0, &sdr_scc_mgr->dqs_io_ena);
543 /* Update the DQS logic. */
544 writel(write_group, &sdr_scc_mgr->dqs_ena);
547 writel(0, &sdr_scc_mgr->update);
551 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
552 * @write_group: Write group
554 * Load DQS settings for Write Group, do not trigger SCC update.
556 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
558 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
559 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
560 const int base = write_group * ratio;
563 * Load the setting in the SCC manager
564 * Although OCT affects only write data, the OCT delay is controlled
565 * by the DQS logic block which is instantiated once per read group.
566 * For protocols where a write group consists of multiple read groups,
567 * the setting must be set multiple times.
569 for (i = 0; i < ratio; i++)
570 writel(base + i, &sdr_scc_mgr->dqs_ena);
574 * scc_mgr_zero_group() - Zero all configs for a group
576 * Zero DQ, DM, DQS and OCT configs for a group.
578 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
582 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
583 r += NUM_RANKS_PER_SHADOW_REG) {
584 /* Zero all DQ config settings. */
585 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
586 scc_mgr_set_dq_out1_delay(i, 0);
588 scc_mgr_set_dq_in_delay(i, 0);
591 /* Multicast to all DQ enables. */
592 writel(0xff, &sdr_scc_mgr->dq_ena);
594 /* Zero all DM config settings. */
595 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
596 scc_mgr_set_dm_out1_delay(i, 0);
598 /* Multicast to all DM enables. */
599 writel(0xff, &sdr_scc_mgr->dm_ena);
601 /* Zero all DQS IO settings. */
603 scc_mgr_set_dqs_io_in_delay(0);
605 /* Arria V/Cyclone V don't have out2. */
606 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
607 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
608 scc_mgr_load_dqs_for_write_group(write_group);
610 /* Multicast to all DQS IO enables (only 1 in total). */
611 writel(0, &sdr_scc_mgr->dqs_io_ena);
613 /* Hit update to zero everything. */
614 writel(0, &sdr_scc_mgr->update);
619 * apply and load a particular input delay for the DQ pins in a group
620 * group_bgn is the index of the first dq pin (in the write group)
622 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
626 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
627 scc_mgr_set_dq_in_delay(p, delay);
633 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
634 * @delay: Delay value
636 * Apply and load a particular output delay for the DQ pins in a group.
638 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
642 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
643 scc_mgr_set_dq_out1_delay(i, delay);
648 /* apply and load a particular output delay for the DM pins in a group */
649 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
653 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
654 scc_mgr_set_dm_out1_delay(i, delay1);
660 /* apply and load delay on both DQS and OCT out1 */
661 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
664 scc_mgr_set_dqs_out1_delay(delay);
665 scc_mgr_load_dqs_io();
667 scc_mgr_set_oct_out1_delay(write_group, delay);
668 scc_mgr_load_dqs_for_write_group(write_group);
672 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
673 * @write_group: Write group
674 * @delay: Delay value
676 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
678 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
684 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
688 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
692 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
693 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
694 debug_cond(DLEVEL == 1,
695 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
696 __func__, __LINE__, write_group, delay, new_delay,
697 IO_IO_OUT2_DELAY_MAX,
698 new_delay - IO_IO_OUT2_DELAY_MAX);
699 new_delay -= IO_IO_OUT2_DELAY_MAX;
700 scc_mgr_set_dqs_out1_delay(new_delay);
703 scc_mgr_load_dqs_io();
706 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
707 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
708 debug_cond(DLEVEL == 1,
709 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
710 __func__, __LINE__, write_group, delay,
711 new_delay, IO_IO_OUT2_DELAY_MAX,
712 new_delay - IO_IO_OUT2_DELAY_MAX);
713 new_delay -= IO_IO_OUT2_DELAY_MAX;
714 scc_mgr_set_oct_out1_delay(write_group, new_delay);
717 scc_mgr_load_dqs_for_write_group(write_group);
721 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
722 * @write_group: Write group
723 * @delay: Delay value
725 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
728 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
733 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
734 r += NUM_RANKS_PER_SHADOW_REG) {
735 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
736 writel(0, &sdr_scc_mgr->update);
741 * set_jump_as_return() - Return instruction optimization
743 * Optimization used to recover some slots in ddr3 inst_rom could be
744 * applied to other protocols if we wanted to
746 static void set_jump_as_return(void)
749 * To save space, we replace return with jump to special shared
750 * RETURN instruction so we set the counter to large value so that
753 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
754 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
758 * should always use constants as argument to ensure all computations are
759 * performed at compile time
761 static void delay_for_n_mem_clocks(const uint32_t clocks)
768 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
771 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
772 /* scale (rounding up) to get afi clocks */
775 * Note, we don't bother accounting for being off a little bit
776 * because of a few extra instructions in outer loops
777 * Note, the loops have a test at the end, and do the test before
778 * the decrement, and so always perform the loop
779 * 1 time more than the counter value
781 if (afi_clocks == 0) {
783 } else if (afi_clocks <= 0x100) {
784 inner = afi_clocks-1;
787 } else if (afi_clocks <= 0x10000) {
789 outer = (afi_clocks-1) >> 8;
794 c_loop = (afi_clocks-1) >> 16;
798 * rom instructions are structured as follows:
800 * IDLE_LOOP2: jnz cntr0, TARGET_A
801 * IDLE_LOOP1: jnz cntr1, TARGET_B
804 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
805 * TARGET_B is set to IDLE_LOOP2 as well
807 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
808 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
810 * a little confusing, but it helps save precious space in the inst_rom
811 * and sequencer rom and keeps the delays more accurate and reduces
814 if (afi_clocks <= 0x100) {
815 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
816 &sdr_rw_load_mgr_regs->load_cntr1);
818 writel(RW_MGR_IDLE_LOOP1,
819 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
821 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
822 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
824 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
825 &sdr_rw_load_mgr_regs->load_cntr0);
827 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
828 &sdr_rw_load_mgr_regs->load_cntr1);
830 writel(RW_MGR_IDLE_LOOP2,
831 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
833 writel(RW_MGR_IDLE_LOOP2,
834 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
836 /* hack to get around compiler not being smart enough */
837 if (afi_clocks <= 0x10000) {
838 /* only need to run once */
839 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
840 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
843 writel(RW_MGR_IDLE_LOOP2,
844 SDR_PHYGRP_RWMGRGRP_ADDRESS |
845 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
846 } while (c_loop-- != 0);
849 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
853 * rw_mgr_mem_init_load_regs() - Load instruction registers
854 * @cntr0: Counter 0 value
855 * @cntr1: Counter 1 value
856 * @cntr2: Counter 2 value
857 * @jump: Jump instruction value
859 * Load instruction registers.
861 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
863 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
864 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
867 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
868 &sdr_rw_load_mgr_regs->load_cntr0);
869 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
870 &sdr_rw_load_mgr_regs->load_cntr1);
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
872 &sdr_rw_load_mgr_regs->load_cntr2);
874 /* Load jump address */
875 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
876 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
877 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
879 /* Execute count instruction */
880 writel(jump, grpaddr);
884 * rw_mgr_mem_load_user() - Load user calibration values
885 * @fin1: Final instruction 1
886 * @fin2: Final instruction 2
887 * @precharge: If 1, precharge the banks at the end
889 * Load user calibration values and optionally precharge the banks.
891 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
894 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
895 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
898 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
899 if (param->skip_ranks[r]) {
900 /* request to skip the rank */
905 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
907 /* precharge all banks ... */
909 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
912 * USER Use Mirror-ed commands for odd ranks if address
915 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
916 set_jump_as_return();
917 writel(RW_MGR_MRS2_MIRR, grpaddr);
918 delay_for_n_mem_clocks(4);
919 set_jump_as_return();
920 writel(RW_MGR_MRS3_MIRR, grpaddr);
921 delay_for_n_mem_clocks(4);
922 set_jump_as_return();
923 writel(RW_MGR_MRS1_MIRR, grpaddr);
924 delay_for_n_mem_clocks(4);
925 set_jump_as_return();
926 writel(fin1, grpaddr);
928 set_jump_as_return();
929 writel(RW_MGR_MRS2, grpaddr);
930 delay_for_n_mem_clocks(4);
931 set_jump_as_return();
932 writel(RW_MGR_MRS3, grpaddr);
933 delay_for_n_mem_clocks(4);
934 set_jump_as_return();
935 writel(RW_MGR_MRS1, grpaddr);
936 set_jump_as_return();
937 writel(fin2, grpaddr);
943 set_jump_as_return();
944 writel(RW_MGR_ZQCL, grpaddr);
946 /* tZQinit = tDLLK = 512 ck cycles */
947 delay_for_n_mem_clocks(512);
951 static void rw_mgr_mem_initialize(void)
953 debug("%s:%d\n", __func__, __LINE__);
955 /* The reset / cke part of initialization is broadcasted to all ranks */
956 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
957 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
960 * Here's how you load register for a loop
961 * Counters are located @ 0x800
962 * Jump address are located @ 0xC00
963 * For both, registers 0 to 3 are selected using bits 3 and 2, like
964 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
965 * I know this ain't pretty, but Avalon bus throws away the 2 least
969 /* start with memory RESET activated */
974 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
975 * If a and b are the number of iteration in 2 nested loops
976 * it takes the following number of cycles to complete the operation:
977 * number_of_cycles = ((2 + n) * a + 2) * b
978 * where n is the number of instruction in the inner loop
979 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
982 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
984 RW_MGR_INIT_RESET_0_CKE_0);
986 /* indicate that memory is stable */
987 writel(1, &phy_mgr_cfg->reset_mem_stbl);
990 * transition the RESET to high
995 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
996 * If a and b are the number of iteration in 2 nested loops
997 * it takes the following number of cycles to complete the operation
998 * number_of_cycles = ((2 + n) * a + 2) * b
999 * where n is the number of instruction in the inner loop
1000 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1003 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1004 SEQ_TRESET_CNTR2_VAL,
1005 RW_MGR_INIT_RESET_1_CKE_0);
1007 /* bring up clock enable */
1009 /* tXRP < 250 ck cycles */
1010 delay_for_n_mem_clocks(250);
1012 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1017 * At the end of calibration we have to program the user settings in, and
1018 * USER hand off the memory to the user.
1020 static void rw_mgr_mem_handoff(void)
1022 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1024 * USER need to wait tMOD (12CK or 15ns) time before issuing
1025 * other commands, but we will have plenty of NIOS cycles before
1026 * actual handoff so its okay.
1031 * performs a guaranteed read on the patterns we are going to use during a
1032 * read test to ensure memory works
1034 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1035 uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1039 uint32_t correct_mask_vg;
1040 uint32_t tmp_bit_chk;
1041 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1042 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1044 uint32_t base_rw_mgr;
1046 *bit_chk = param->read_correct_mask;
1047 correct_mask_vg = param->read_correct_mask_vg;
1049 for (r = rank_bgn; r < rank_end; r++) {
1050 if (param->skip_ranks[r])
1051 /* request to skip the rank */
1055 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1057 /* Load up a constant bursts of read commands */
1058 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1059 writel(RW_MGR_GUARANTEED_READ,
1060 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1062 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1063 writel(RW_MGR_GUARANTEED_READ_CONT,
1064 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1067 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1068 /* reset the fifos to get pointers to known state */
1070 writel(0, &phy_mgr_cmd->fifo_reset);
1071 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1072 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1074 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1075 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1077 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1078 writel(RW_MGR_GUARANTEED_READ, addr +
1079 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1082 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1083 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1088 *bit_chk &= tmp_bit_chk;
1091 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1092 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1094 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1095 debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1096 %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1097 (long unsigned int)(*bit_chk == param->read_correct_mask));
1098 return *bit_chk == param->read_correct_mask;
1101 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1102 (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1104 return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1105 num_tries, bit_chk, 1);
1108 /* load up the patterns we are going to use during a read test */
1109 static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
1113 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1114 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1116 debug("%s:%d\n", __func__, __LINE__);
1117 for (r = rank_bgn; r < rank_end; r++) {
1118 if (param->skip_ranks[r])
1119 /* request to skip the rank */
1123 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1125 /* Load up a constant bursts */
1126 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1128 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1129 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1131 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1133 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1134 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1136 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1138 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1139 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1141 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1143 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1144 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1146 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1147 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1150 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1154 * try a read and see if it returns correct data back. has dummy reads
1155 * inserted into the mix used to align dqs enable. has more thorough checks
1156 * than the regular read test.
1158 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1159 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1160 uint32_t all_groups, uint32_t all_ranks)
1163 uint32_t correct_mask_vg;
1164 uint32_t tmp_bit_chk;
1165 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1166 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1168 uint32_t base_rw_mgr;
1170 *bit_chk = param->read_correct_mask;
1171 correct_mask_vg = param->read_correct_mask_vg;
1173 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1174 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1176 for (r = rank_bgn; r < rank_end; r++) {
1177 if (param->skip_ranks[r])
1178 /* request to skip the rank */
1182 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1184 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1186 writel(RW_MGR_READ_B2B_WAIT1,
1187 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1189 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1190 writel(RW_MGR_READ_B2B_WAIT2,
1191 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1193 if (quick_read_mode)
1194 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1195 /* need at least two (1+1) reads to capture failures */
1196 else if (all_groups)
1197 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1199 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1201 writel(RW_MGR_READ_B2B,
1202 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1204 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1205 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1206 &sdr_rw_load_mgr_regs->load_cntr3);
1208 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1210 writel(RW_MGR_READ_B2B,
1211 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1214 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1215 /* reset the fifos to get pointers to known state */
1216 writel(0, &phy_mgr_cmd->fifo_reset);
1217 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1218 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1220 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1221 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1224 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1226 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1228 writel(RW_MGR_READ_B2B, addr +
1229 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1232 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1233 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1238 *bit_chk &= tmp_bit_chk;
1241 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1242 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1245 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1246 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1247 (%u == %u) => %lu", __func__, __LINE__, group,
1248 all_groups, *bit_chk, param->read_correct_mask,
1249 (long unsigned int)(*bit_chk ==
1250 param->read_correct_mask));
1251 return *bit_chk == param->read_correct_mask;
1253 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1254 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1255 (%u != %lu) => %lu\n", __func__, __LINE__,
1256 group, all_groups, *bit_chk, (long unsigned int)0,
1257 (long unsigned int)(*bit_chk != 0x00));
1258 return *bit_chk != 0x00;
1262 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1263 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1264 uint32_t all_groups)
1266 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1267 bit_chk, all_groups, 1);
1270 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1272 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1276 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1280 for (i = 0; i < VFIFO_SIZE-1; i++)
1281 rw_mgr_incr_vfifo(grp, v);
1284 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1287 uint32_t fail_cnt = 0;
1288 uint32_t test_status;
1290 for (v = 0; v < VFIFO_SIZE; ) {
1291 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1292 __func__, __LINE__, v);
1293 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1294 (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1302 /* fiddle with FIFO */
1303 rw_mgr_incr_vfifo(grp, &v);
1306 if (v >= VFIFO_SIZE) {
1307 /* no failing read found!! Something must have gone wrong */
1308 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1309 __func__, __LINE__);
1316 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1317 uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1318 uint32_t *v, uint32_t *d, uint32_t *p,
1319 uint32_t *i, uint32_t *max_working_cnt)
1321 uint32_t found_begin = 0;
1322 uint32_t tmp_delay = 0;
1323 uint32_t test_status;
1325 for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1326 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1327 *work_bgn = tmp_delay;
1328 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1330 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1331 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1332 IO_DELAY_PER_OPA_TAP) {
1333 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1336 rw_mgr_mem_calibrate_read_test_all_ranks
1337 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1340 *max_working_cnt = 1;
1349 if (*p > IO_DQS_EN_PHASE_MAX)
1350 /* fiddle with FIFO */
1351 rw_mgr_incr_vfifo(*grp, v);
1358 if (*i >= VFIFO_SIZE) {
1359 /* cannot find working solution */
1360 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1361 ptap/dtap\n", __func__, __LINE__);
1368 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1369 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1370 uint32_t *p, uint32_t *max_working_cnt)
1372 uint32_t found_begin = 0;
1375 /* Special case code for backing up a phase */
1377 *p = IO_DQS_EN_PHASE_MAX;
1378 rw_mgr_decr_vfifo(*grp, v);
1382 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1383 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1385 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1386 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1387 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1389 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1393 *work_bgn = tmp_delay;
1398 /* We have found a working dtap before the ptap found above */
1399 if (found_begin == 1)
1400 (*max_working_cnt)++;
1403 * Restore VFIFO to old state before we decremented it
1407 if (*p > IO_DQS_EN_PHASE_MAX) {
1409 rw_mgr_incr_vfifo(*grp, v);
1412 scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1415 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1416 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1417 uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1420 uint32_t found_end = 0;
1423 *work_end += IO_DELAY_PER_OPA_TAP;
1424 if (*p > IO_DQS_EN_PHASE_MAX) {
1425 /* fiddle with FIFO */
1427 rw_mgr_incr_vfifo(*grp, v);
1430 for (; *i < VFIFO_SIZE + 1; (*i)++) {
1431 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1432 += IO_DELAY_PER_OPA_TAP) {
1433 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1435 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1436 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1440 (*max_working_cnt)++;
1447 if (*p > IO_DQS_EN_PHASE_MAX) {
1448 /* fiddle with FIFO */
1449 rw_mgr_incr_vfifo(*grp, v);
1454 if (*i >= VFIFO_SIZE + 1) {
1455 /* cannot see edge of failing read */
1456 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1457 failed\n", __func__, __LINE__);
1464 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1465 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1466 uint32_t *p, uint32_t *work_mid,
1472 *work_mid = (*work_bgn + *work_end) / 2;
1474 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1475 *work_bgn, *work_end, *work_mid);
1476 /* Get the middle delay to be less than a VFIFO delay */
1477 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1478 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1480 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1481 while (*work_mid > tmp_delay)
1482 *work_mid -= tmp_delay;
1483 debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1486 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1487 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1489 tmp_delay -= IO_DELAY_PER_OPA_TAP;
1490 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1491 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1492 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1494 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1496 scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1497 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1500 * push vfifo until we can successfully calibrate. We can do this
1501 * because the largest possible margin in 1 VFIFO cycle.
1503 for (i = 0; i < VFIFO_SIZE; i++) {
1504 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1506 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1512 /* fiddle with FIFO */
1513 rw_mgr_incr_vfifo(*grp, v);
1516 if (i >= VFIFO_SIZE) {
1517 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1518 failed\n", __func__, __LINE__);
1525 /* find a good dqs enable to use */
1526 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1528 uint32_t v, d, p, i;
1529 uint32_t max_working_cnt;
1531 uint32_t dtaps_per_ptap;
1532 uint32_t work_bgn, work_mid, work_end;
1533 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1535 debug("%s:%d %u\n", __func__, __LINE__, grp);
1537 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1539 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1540 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1542 /* ************************************************************** */
1543 /* * Step 0 : Determine number of delay taps for each phase tap * */
1544 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1546 /* ********************************************************* */
1547 /* * Step 1 : First push vfifo until we get a failing read * */
1548 v = find_vfifo_read(grp, &bit_chk);
1550 max_working_cnt = 0;
1552 /* ******************************************************** */
1553 /* * step 2: find first working phase, increment in ptaps * */
1555 if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1556 &p, &i, &max_working_cnt) == 0)
1559 work_end = work_bgn;
1562 * If d is 0 then the working window covers a phase tap and
1563 * we can follow the old procedure otherwise, we've found the beginning,
1564 * and we need to increment the dtaps until we find the end.
1567 /* ********************************************************* */
1568 /* * step 3a: if we have room, back off by one and
1569 increment in dtaps * */
1571 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1574 /* ********************************************************* */
1575 /* * step 4a: go forward from working phase to non working
1576 phase, increment in ptaps * */
1577 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1578 &i, &max_working_cnt, &work_end) == 0)
1581 /* ********************************************************* */
1582 /* * step 5a: back off one from last, increment in dtaps * */
1584 /* Special case code for backing up a phase */
1586 p = IO_DQS_EN_PHASE_MAX;
1587 rw_mgr_decr_vfifo(grp, &v);
1592 work_end -= IO_DELAY_PER_OPA_TAP;
1593 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1595 /* * The actual increment of dtaps is done outside of
1596 the if/else loop to share code */
1599 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1600 vfifo=%u ptap=%u\n", __func__, __LINE__,
1603 /* ******************************************************* */
1604 /* * step 3-5b: Find the right edge of the window using
1606 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1607 ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1610 work_end = work_bgn;
1612 /* * The actual increment of dtaps is done outside of the
1613 if/else loop to share code */
1615 /* Only here to counterbalance a subtract later on which is
1616 not needed if this branch of the algorithm is taken */
1620 /* The dtap increment to find the failing edge is done here */
1621 for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1622 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1623 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1624 end-2: dtap=%u\n", __func__, __LINE__, d);
1625 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1627 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1634 /* Go back to working dtap */
1636 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1638 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1639 ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1640 v, p, d-1, work_end);
1642 if (work_end < work_bgn) {
1644 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1645 failed\n", __func__, __LINE__);
1649 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1650 __func__, __LINE__, work_bgn, work_end);
1652 /* *************************************************************** */
1654 * * We need to calculate the number of dtaps that equal a ptap
1655 * * To do that we'll back up a ptap and re-find the edge of the
1656 * * window using dtaps
1659 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1660 for tracking\n", __func__, __LINE__);
1662 /* Special case code for backing up a phase */
1664 p = IO_DQS_EN_PHASE_MAX;
1665 rw_mgr_decr_vfifo(grp, &v);
1666 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1667 cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1671 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1672 phase only: v=%u p=%u", __func__, __LINE__,
1676 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1679 * Increase dtap until we first see a passing read (in case the
1680 * window is smaller than a ptap),
1681 * and then a failing read to mark the edge of the window again
1684 /* Find a passing read */
1685 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1686 __func__, __LINE__);
1687 found_passing_read = 0;
1688 found_failing_read = 0;
1689 initial_failing_dtap = d;
1690 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1691 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1692 read d=%u\n", __func__, __LINE__, d);
1693 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1695 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1698 found_passing_read = 1;
1703 if (found_passing_read) {
1704 /* Find a failing read */
1705 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1706 read\n", __func__, __LINE__);
1707 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1708 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1709 testing read d=%u\n", __func__, __LINE__, d);
1710 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1712 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1713 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1714 found_failing_read = 1;
1719 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1720 calculate dtaps", __func__, __LINE__);
1721 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1725 * The dynamically calculated dtaps_per_ptap is only valid if we
1726 * found a passing/failing read. If we didn't, it means d hit the max
1727 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1728 * statically calculated value.
1730 if (found_passing_read && found_failing_read)
1731 dtaps_per_ptap = d - initial_failing_dtap;
1733 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1734 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1735 - %u = %u", __func__, __LINE__, d,
1736 initial_failing_dtap, dtaps_per_ptap);
1738 /* ******************************************** */
1739 /* * step 6: Find the centre of the window * */
1740 if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1741 &work_mid, &work_end) == 0)
1744 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1745 vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1751 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1752 * dq_in_delay values
1755 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1756 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1764 const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1765 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1766 /* we start at zero, so have one less dq to devide among */
1768 debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1771 /* try different dq_in_delays since the dq path is shorter than dqs */
1773 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1774 r += NUM_RANKS_PER_SHADOW_REG) {
1775 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
1776 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1777 vfifo_find_dqs_", __func__, __LINE__);
1778 debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1779 write_group, read_group);
1780 debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
1781 scc_mgr_set_dq_in_delay(p, d);
1784 writel(0, &sdr_scc_mgr->update);
1787 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1789 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1790 en_phase_sweep_dq", __func__, __LINE__);
1791 debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1792 chain to zero\n", write_group, read_group, found);
1794 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1795 r += NUM_RANKS_PER_SHADOW_REG) {
1796 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1798 scc_mgr_set_dq_in_delay(p, 0);
1801 writel(0, &sdr_scc_mgr->update);
1807 /* per-bit deskew DQ and center */
1808 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1809 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1810 uint32_t use_read_test, uint32_t update_fom)
1812 uint32_t i, p, d, min_index;
1814 * Store these as signed since there are comparisons with
1818 uint32_t sticky_bit_chk;
1819 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1820 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1821 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1823 int32_t orig_mid_min, mid_min;
1824 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1826 int32_t dq_margin, dqs_margin;
1828 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1831 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1833 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1834 start_dqs = readl(addr + (read_group << 2));
1835 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1836 start_dqs_en = readl(addr + ((read_group << 2)
1837 - IO_DQS_EN_DELAY_OFFSET));
1839 /* set the left and right edge of each bit to an illegal value */
1840 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1842 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1843 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1844 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1847 /* Search for the left edge of the window for each bit */
1848 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1849 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1851 writel(0, &sdr_scc_mgr->update);
1854 * Stop searching when the read test doesn't pass AND when
1855 * we've seen a passing read on every bit.
1857 if (use_read_test) {
1858 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1859 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1862 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1865 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1866 (read_group - (write_group *
1867 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1868 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1869 stop = (bit_chk == 0);
1871 sticky_bit_chk = sticky_bit_chk | bit_chk;
1872 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1873 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1874 && %u", __func__, __LINE__, d,
1876 param->read_correct_mask, stop);
1881 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1883 /* Remember a passing test as the
1887 /* If a left edge has not been seen yet,
1888 then a future passing test will mark
1889 this edge as the right edge */
1891 IO_IO_IN_DELAY_MAX + 1) {
1892 right_edge[i] = -(d + 1);
1895 bit_chk = bit_chk >> 1;
1900 /* Reset DQ delay chains to 0 */
1901 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1903 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1904 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1905 %d right_edge[%u]: %d\n", __func__, __LINE__,
1906 i, left_edge[i], i, right_edge[i]);
1909 * Check for cases where we haven't found the left edge,
1910 * which makes our assignment of the the right edge invalid.
1911 * Reset it to the illegal value.
1913 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1914 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1915 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1916 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1917 right_edge[%u]: %d\n", __func__, __LINE__,
1922 * Reset sticky bit (except for bits where we have seen
1923 * both the left and right edge).
1925 sticky_bit_chk = sticky_bit_chk << 1;
1926 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1927 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1928 sticky_bit_chk = sticky_bit_chk | 1;
1935 /* Search for the right edge of the window for each bit */
1936 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1937 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1938 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1939 uint32_t delay = d + start_dqs_en;
1940 if (delay > IO_DQS_EN_DELAY_MAX)
1941 delay = IO_DQS_EN_DELAY_MAX;
1942 scc_mgr_set_dqs_en_delay(read_group, delay);
1944 scc_mgr_load_dqs(read_group);
1946 writel(0, &sdr_scc_mgr->update);
1949 * Stop searching when the read test doesn't pass AND when
1950 * we've seen a passing read on every bit.
1952 if (use_read_test) {
1953 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1954 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1957 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1960 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1961 (read_group - (write_group *
1962 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1963 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1964 stop = (bit_chk == 0);
1966 sticky_bit_chk = sticky_bit_chk | bit_chk;
1967 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1969 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1970 %u && %u", __func__, __LINE__, d,
1971 sticky_bit_chk, param->read_correct_mask, stop);
1976 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1978 /* Remember a passing test as
1983 /* If a right edge has not been
1984 seen yet, then a future passing
1985 test will mark this edge as the
1987 if (right_edge[i] ==
1988 IO_IO_IN_DELAY_MAX + 1) {
1989 left_edge[i] = -(d + 1);
1992 /* d = 0 failed, but it passed
1993 when testing the left edge,
1994 so it must be marginal,
1996 if (right_edge[i] ==
1997 IO_IO_IN_DELAY_MAX + 1 &&
2003 /* If a right edge has not been
2004 seen yet, then a future passing
2005 test will mark this edge as the
2007 else if (right_edge[i] ==
2008 IO_IO_IN_DELAY_MAX +
2010 left_edge[i] = -(d + 1);
2015 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2016 d=%u]: ", __func__, __LINE__, d);
2017 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2018 (int)(bit_chk & 1), i, left_edge[i]);
2019 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2021 bit_chk = bit_chk >> 1;
2026 /* Check that all bits have a window */
2027 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2028 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2029 %d right_edge[%u]: %d", __func__, __LINE__,
2030 i, left_edge[i], i, right_edge[i]);
2031 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2032 == IO_IO_IN_DELAY_MAX + 1)) {
2034 * Restore delay chain settings before letting the loop
2035 * in rw_mgr_mem_calibrate_vfifo to retry different
2036 * dqs/ck relationships.
2038 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2039 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2040 scc_mgr_set_dqs_en_delay(read_group,
2043 scc_mgr_load_dqs(read_group);
2044 writel(0, &sdr_scc_mgr->update);
2046 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2047 find edge [%u]: %d %d", __func__, __LINE__,
2048 i, left_edge[i], right_edge[i]);
2049 if (use_read_test) {
2050 set_failing_group_stage(read_group *
2051 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2053 CAL_SUBSTAGE_VFIFO_CENTER);
2055 set_failing_group_stage(read_group *
2056 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2057 CAL_STAGE_VFIFO_AFTER_WRITES,
2058 CAL_SUBSTAGE_VFIFO_CENTER);
2064 /* Find middle of window for each DQ bit */
2065 mid_min = left_edge[0] - right_edge[0];
2067 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2068 mid = left_edge[i] - right_edge[i];
2069 if (mid < mid_min) {
2076 * -mid_min/2 represents the amount that we need to move DQS.
2077 * If mid_min is odd and positive we'll need to add one to
2078 * make sure the rounding in further calculations is correct
2079 * (always bias to the right), so just add 1 for all positive values.
2084 mid_min = mid_min / 2;
2086 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2087 __func__, __LINE__, mid_min, min_index);
2089 /* Determine the amount we can change DQS (which is -mid_min) */
2090 orig_mid_min = mid_min;
2091 new_dqs = start_dqs - mid_min;
2092 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2093 new_dqs = IO_DQS_IN_DELAY_MAX;
2094 else if (new_dqs < 0)
2097 mid_min = start_dqs - new_dqs;
2098 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2101 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2102 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2103 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2104 else if (start_dqs_en - mid_min < 0)
2105 mid_min += start_dqs_en - mid_min;
2107 new_dqs = start_dqs - mid_min;
2109 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2110 new_dqs=%d mid_min=%d\n", start_dqs,
2111 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2114 /* Initialize data for export structures */
2115 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2116 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2118 /* add delay to bring centre of all DQ windows to the same "level" */
2119 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2120 /* Use values before divide by 2 to reduce round off error */
2121 shift_dq = (left_edge[i] - right_edge[i] -
2122 (left_edge[min_index] - right_edge[min_index]))/2 +
2123 (orig_mid_min - mid_min);
2125 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2126 shift_dq[%u]=%d\n", i, shift_dq);
2128 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2129 temp_dq_in_delay1 = readl(addr + (p << 2));
2130 temp_dq_in_delay2 = readl(addr + (i << 2));
2132 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2133 (int32_t)IO_IO_IN_DELAY_MAX) {
2134 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2135 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2136 shift_dq = -(int32_t)temp_dq_in_delay1;
2138 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2139 shift_dq[%u]=%d\n", i, shift_dq);
2140 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2141 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2144 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2145 left_edge[i] - shift_dq + (-mid_min),
2146 right_edge[i] + shift_dq - (-mid_min));
2147 /* To determine values for export structures */
2148 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2149 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2151 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2152 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2155 final_dqs = new_dqs;
2156 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2157 final_dqs_en = start_dqs_en - mid_min;
2160 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2161 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2162 scc_mgr_load_dqs(read_group);
2166 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2167 scc_mgr_load_dqs(read_group);
2168 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2169 dqs_margin=%d", __func__, __LINE__,
2170 dq_margin, dqs_margin);
2173 * Do not remove this line as it makes sure all of our decisions
2174 * have been applied. Apply the update bit.
2176 writel(0, &sdr_scc_mgr->update);
2178 return (dq_margin >= 0) && (dqs_margin >= 0);
2182 * calibrate the read valid prediction FIFO.
2184 * - read valid prediction will consist of finding a good DQS enable phase,
2185 * DQS enable delay, DQS input phase, and DQS input delay.
2186 * - we also do a per-bit deskew on the DQ lines.
2188 static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
2191 uint32_t p, d, rank_bgn, sr;
2192 uint32_t dtaps_per_ptap;
2194 uint32_t grp_calibrated;
2195 uint32_t write_group, write_test_bgn;
2196 uint32_t failed_substage;
2198 debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
2200 /* update info for sims */
2201 reg_file_set_stage(CAL_STAGE_VFIFO);
2203 write_group = read_group;
2204 write_test_bgn = test_bgn;
2206 /* USER Determine number of delay taps for each phase tap */
2207 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2208 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2210 /* update info for sims */
2211 reg_file_set_group(read_group);
2215 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2216 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2218 for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
2220 * In RLDRAMX we may be messing the delay of pins in
2221 * the same write group but outside of the current read
2222 * the group, but that's ok because we haven't
2223 * calibrated output side yet.
2226 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2230 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
2232 /* set a particular dqdqs phase */
2233 scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
2235 debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
2236 p=%u d=%u\n", __func__, __LINE__,
2240 * Load up the patterns used by read calibration
2241 * using current DQDQS phase.
2243 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2244 if (!(gbl->phy_debug_mode_flags &
2245 PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
2246 if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
2247 (read_group, 1, &bit_chk)) {
2248 debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
2249 __func__, __LINE__);
2250 debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
2258 if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
2259 (write_group, read_group, test_bgn)) {
2261 * USER Read per-bit deskew can be done on a
2262 * per shadow register basis.
2264 for (rank_bgn = 0, sr = 0;
2265 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2266 rank_bgn += NUM_RANKS_PER_SHADOW_REG,
2269 * Determine if this set of ranks
2270 * should be skipped entirely.
2272 if (!param->skip_shadow_regs[sr]) {
2274 * If doing read after write
2275 * calibration, do not update
2276 * FOM, now - do it then.
2278 if (!rw_mgr_mem_calibrate_vfifo_center
2279 (rank_bgn, write_group,
2280 read_group, test_bgn, 1, 0)) {
2283 CAL_SUBSTAGE_VFIFO_CENTER;
2289 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2294 if (grp_calibrated == 0) {
2295 set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
2301 * Reset the delay chains back to zero if they have moved > 1
2302 * (check for > 1 because loop will increase d even when pass in
2306 scc_mgr_zero_group(write_group, 1);
2311 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2312 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2315 uint32_t rank_bgn, sr;
2316 uint32_t grp_calibrated;
2317 uint32_t write_group;
2319 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2321 /* update info for sims */
2323 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2324 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2326 write_group = read_group;
2328 /* update info for sims */
2329 reg_file_set_group(read_group);
2332 /* Read per-bit deskew can be done on a per shadow register basis */
2333 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2334 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2335 /* Determine if this set of ranks should be skipped entirely */
2336 if (!param->skip_shadow_regs[sr]) {
2337 /* This is the last calibration round, update FOM here */
2338 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2349 if (grp_calibrated == 0) {
2350 set_failing_group_stage(write_group,
2351 CAL_STAGE_VFIFO_AFTER_WRITES,
2352 CAL_SUBSTAGE_VFIFO_CENTER);
2359 /* Calibrate LFIFO to find smallest read latency */
2360 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2365 debug("%s:%d\n", __func__, __LINE__);
2367 /* update info for sims */
2368 reg_file_set_stage(CAL_STAGE_LFIFO);
2369 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2371 /* Load up the patterns used by read calibration for all ranks */
2372 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2376 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2377 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2378 __func__, __LINE__, gbl->curr_read_lat);
2380 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2388 /* reduce read latency and see if things are working */
2390 gbl->curr_read_lat--;
2391 } while (gbl->curr_read_lat > 0);
2393 /* reset the fifos to get pointers to known state */
2395 writel(0, &phy_mgr_cmd->fifo_reset);
2398 /* add a fudge factor to the read latency that was determined */
2399 gbl->curr_read_lat += 2;
2400 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2401 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2402 read_lat=%u\n", __func__, __LINE__,
2403 gbl->curr_read_lat);
2406 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2407 CAL_SUBSTAGE_READ_LATENCY);
2409 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2410 read_lat=%u\n", __func__, __LINE__,
2411 gbl->curr_read_lat);
2417 * issue write test command.
2418 * two variants are provided. one that just tests a write pattern and
2419 * another that tests datamask functionality.
2421 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2424 uint32_t mcc_instruction;
2425 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2426 ENABLE_SUPER_QUICK_CALIBRATION);
2427 uint32_t rw_wl_nop_cycles;
2431 * Set counter and jump addresses for the right
2432 * number of NOP cycles.
2433 * The number of supported NOP cycles can range from -1 to infinity
2434 * Three different cases are handled:
2436 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2437 * mechanism will be used to insert the right number of NOPs
2439 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2440 * issuing the write command will jump straight to the
2441 * micro-instruction that turns on DQS (for DDRx), or outputs write
2442 * data (for RLD), skipping
2443 * the NOP micro-instruction all together
2445 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2446 * turned on in the same micro-instruction that issues the write
2447 * command. Then we need
2448 * to directly jump to the micro-instruction that sends out the data
2450 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2451 * (2 and 3). One jump-counter (0) is used to perform multiple
2452 * write-read operations.
2453 * one counter left to issue this command in "multiple-group" mode
2456 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2458 if (rw_wl_nop_cycles == -1) {
2460 * CNTR 2 - We want to execute the special write operation that
2461 * turns on DQS right away and then skip directly to the
2462 * instruction that sends out the data. We set the counter to a
2463 * large number so that the jump is always taken.
2465 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2467 /* CNTR 3 - Not used */
2469 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2470 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2471 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2472 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2473 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2475 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2476 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2477 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2478 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2479 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2481 } else if (rw_wl_nop_cycles == 0) {
2483 * CNTR 2 - We want to skip the NOP operation and go straight
2484 * to the DQS enable instruction. We set the counter to a large
2485 * number so that the jump is always taken.
2487 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2489 /* CNTR 3 - Not used */
2491 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2492 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2493 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2495 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2496 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2497 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2501 * CNTR 2 - In this case we want to execute the next instruction
2502 * and NOT take the jump. So we set the counter to 0. The jump
2503 * address doesn't count.
2505 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2506 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2509 * CNTR 3 - Set the nop counter to the number of cycles we
2510 * need to loop for, minus 1.
2512 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2514 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2515 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2516 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2518 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2519 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2520 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2524 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2525 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2527 if (quick_write_mode)
2528 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2530 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2532 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2535 * CNTR 1 - This is used to ensure enough time elapses
2536 * for read data to come back.
2538 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2541 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2542 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2544 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2545 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2548 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2549 writel(mcc_instruction, addr + (group << 2));
2552 /* Test writes, can check for a single bit pass or multiple bit pass */
2553 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2554 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2555 uint32_t *bit_chk, uint32_t all_ranks)
2558 uint32_t correct_mask_vg;
2559 uint32_t tmp_bit_chk;
2561 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2562 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2563 uint32_t addr_rw_mgr;
2564 uint32_t base_rw_mgr;
2566 *bit_chk = param->write_correct_mask;
2567 correct_mask_vg = param->write_correct_mask_vg;
2569 for (r = rank_bgn; r < rank_end; r++) {
2570 if (param->skip_ranks[r]) {
2571 /* request to skip the rank */
2576 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2579 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2580 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2581 /* reset the fifos to get pointers to known state */
2582 writel(0, &phy_mgr_cmd->fifo_reset);
2584 tmp_bit_chk = tmp_bit_chk <<
2585 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2586 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2587 rw_mgr_mem_calibrate_write_test_issue(write_group *
2588 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2591 base_rw_mgr = readl(addr_rw_mgr);
2592 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2596 *bit_chk &= tmp_bit_chk;
2600 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2601 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2602 %u => %lu", write_group, use_dm,
2603 *bit_chk, param->write_correct_mask,
2604 (long unsigned int)(*bit_chk ==
2605 param->write_correct_mask));
2606 return *bit_chk == param->write_correct_mask;
2608 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2609 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2610 write_group, use_dm, *bit_chk);
2611 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2612 (long unsigned int)(*bit_chk != 0));
2613 return *bit_chk != 0x00;
2618 * center all windows. do per-bit-deskew to possibly increase size of
2621 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2622 uint32_t write_group, uint32_t test_bgn)
2624 uint32_t i, p, min_index;
2627 * Store these as signed since there are comparisons with
2631 uint32_t sticky_bit_chk;
2632 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2633 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2635 int32_t mid_min, orig_mid_min;
2636 int32_t new_dqs, start_dqs, shift_dq;
2637 int32_t dq_margin, dqs_margin, dm_margin;
2639 uint32_t temp_dq_out1_delay;
2642 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2646 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2647 start_dqs = readl(addr +
2648 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2650 /* per-bit deskew */
2653 * set the left and right edge of each bit to an illegal value
2654 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2657 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2658 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2659 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2662 /* Search for the left edge of the window for each bit */
2663 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2664 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2666 writel(0, &sdr_scc_mgr->update);
2669 * Stop searching when the read test doesn't pass AND when
2670 * we've seen a passing read on every bit.
2672 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2673 0, PASS_ONE_BIT, &bit_chk, 0);
2674 sticky_bit_chk = sticky_bit_chk | bit_chk;
2675 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2676 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2677 == %u && %u [bit_chk= %u ]\n",
2678 d, sticky_bit_chk, param->write_correct_mask,
2684 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2687 * Remember a passing test as the
2693 * If a left edge has not been seen
2694 * yet, then a future passing test will
2695 * mark this edge as the right edge.
2698 IO_IO_OUT1_DELAY_MAX + 1) {
2699 right_edge[i] = -(d + 1);
2702 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2703 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2704 (int)(bit_chk & 1), i, left_edge[i]);
2705 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2707 bit_chk = bit_chk >> 1;
2712 /* Reset DQ delay chains to 0 */
2713 scc_mgr_apply_group_dq_out1_delay(0);
2715 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2716 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2717 %d right_edge[%u]: %d\n", __func__, __LINE__,
2718 i, left_edge[i], i, right_edge[i]);
2721 * Check for cases where we haven't found the left edge,
2722 * which makes our assignment of the the right edge invalid.
2723 * Reset it to the illegal value.
2725 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2726 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2727 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2728 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2729 right_edge[%u]: %d\n", __func__, __LINE__,
2734 * Reset sticky bit (except for bits where we have
2735 * seen the left edge).
2737 sticky_bit_chk = sticky_bit_chk << 1;
2738 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2739 sticky_bit_chk = sticky_bit_chk | 1;
2745 /* Search for the right edge of the window for each bit */
2746 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2747 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2750 writel(0, &sdr_scc_mgr->update);
2753 * Stop searching when the read test doesn't pass AND when
2754 * we've seen a passing read on every bit.
2756 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2757 0, PASS_ONE_BIT, &bit_chk, 0);
2759 sticky_bit_chk = sticky_bit_chk | bit_chk;
2760 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2762 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2763 %u && %u\n", d, sticky_bit_chk,
2764 param->write_correct_mask, stop);
2768 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2770 /* d = 0 failed, but it passed when
2771 testing the left edge, so it must be
2772 marginal, set it to -1 */
2773 if (right_edge[i] ==
2774 IO_IO_OUT1_DELAY_MAX + 1 &&
2776 IO_IO_OUT1_DELAY_MAX + 1) {
2783 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2786 * Remember a passing test as
2793 * If a right edge has not
2794 * been seen yet, then a future
2795 * passing test will mark this
2796 * edge as the left edge.
2798 if (right_edge[i] ==
2799 IO_IO_OUT1_DELAY_MAX + 1)
2800 left_edge[i] = -(d + 1);
2803 * d = 0 failed, but it passed
2804 * when testing the left edge,
2805 * so it must be marginal, set
2808 if (right_edge[i] ==
2809 IO_IO_OUT1_DELAY_MAX + 1 &&
2811 IO_IO_OUT1_DELAY_MAX + 1)
2814 * If a right edge has not been
2815 * seen yet, then a future
2816 * passing test will mark this
2817 * edge as the left edge.
2819 else if (right_edge[i] ==
2820 IO_IO_OUT1_DELAY_MAX +
2822 left_edge[i] = -(d + 1);
2825 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2826 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2827 (int)(bit_chk & 1), i, left_edge[i]);
2828 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2830 bit_chk = bit_chk >> 1;
2835 /* Check that all bits have a window */
2836 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2837 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2838 %d right_edge[%u]: %d", __func__, __LINE__,
2839 i, left_edge[i], i, right_edge[i]);
2840 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2841 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2842 set_failing_group_stage(test_bgn + i,
2844 CAL_SUBSTAGE_WRITES_CENTER);
2849 /* Find middle of window for each DQ bit */
2850 mid_min = left_edge[0] - right_edge[0];
2852 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2853 mid = left_edge[i] - right_edge[i];
2854 if (mid < mid_min) {
2861 * -mid_min/2 represents the amount that we need to move DQS.
2862 * If mid_min is odd and positive we'll need to add one to
2863 * make sure the rounding in further calculations is correct
2864 * (always bias to the right), so just add 1 for all positive values.
2868 mid_min = mid_min / 2;
2869 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2872 /* Determine the amount we can change DQS (which is -mid_min) */
2873 orig_mid_min = mid_min;
2874 new_dqs = start_dqs;
2876 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2877 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2878 /* Initialize data for export structures */
2879 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2880 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2882 /* add delay to bring centre of all DQ windows to the same "level" */
2883 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2884 /* Use values before divide by 2 to reduce round off error */
2885 shift_dq = (left_edge[i] - right_edge[i] -
2886 (left_edge[min_index] - right_edge[min_index]))/2 +
2887 (orig_mid_min - mid_min);
2889 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2890 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2892 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2893 temp_dq_out1_delay = readl(addr + (i << 2));
2894 if (shift_dq + (int32_t)temp_dq_out1_delay >
2895 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2896 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2897 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2898 shift_dq = -(int32_t)temp_dq_out1_delay;
2900 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2902 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2905 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2906 left_edge[i] - shift_dq + (-mid_min),
2907 right_edge[i] + shift_dq - (-mid_min));
2908 /* To determine values for export structures */
2909 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2910 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2912 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2913 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2917 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2918 writel(0, &sdr_scc_mgr->update);
2921 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2924 * set the left and right edge of each bit to an illegal value,
2925 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2927 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2928 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2929 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2930 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2931 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2932 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2933 int32_t win_best = 0;
2935 /* Search for the/part of the window with DM shift */
2936 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
2937 scc_mgr_apply_group_dm_out1_delay(d);
2938 writel(0, &sdr_scc_mgr->update);
2940 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2941 PASS_ALL_BITS, &bit_chk,
2943 /* USE Set current end of the window */
2946 * If a starting edge of our window has not been seen
2947 * this is our current start of the DM window.
2949 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2953 * If current window is bigger than best seen.
2954 * Set best seen to be current window.
2956 if ((end_curr-bgn_curr+1) > win_best) {
2957 win_best = end_curr-bgn_curr+1;
2958 bgn_best = bgn_curr;
2959 end_best = end_curr;
2962 /* We just saw a failing test. Reset temp edge */
2963 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2964 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2969 /* Reset DM delay chains to 0 */
2970 scc_mgr_apply_group_dm_out1_delay(0);
2973 * Check to see if the current window nudges up aganist 0 delay.
2974 * If so we need to continue the search by shifting DQS otherwise DQS
2975 * search begins as a new search. */
2976 if (end_curr != 0) {
2977 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2978 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2981 /* Search for the/part of the window with DQS shifts */
2982 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
2984 * Note: This only shifts DQS, so are we limiting ourselve to
2985 * width of DQ unnecessarily.
2987 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2990 writel(0, &sdr_scc_mgr->update);
2991 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2992 PASS_ALL_BITS, &bit_chk,
2994 /* USE Set current end of the window */
2997 * If a beginning edge of our window has not been seen
2998 * this is our current begin of the DM window.
3000 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3004 * If current window is bigger than best seen. Set best
3005 * seen to be current window.
3007 if ((end_curr-bgn_curr+1) > win_best) {
3008 win_best = end_curr-bgn_curr+1;
3009 bgn_best = bgn_curr;
3010 end_best = end_curr;
3013 /* We just saw a failing test. Reset temp edge */
3014 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3015 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3017 /* Early exit optimization: if ther remaining delay
3018 chain space is less than already seen largest window
3021 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3027 /* assign left and right edge for cal and reporting; */
3028 left_edge[0] = -1*bgn_best;
3029 right_edge[0] = end_best;
3031 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3032 __LINE__, left_edge[0], right_edge[0]);
3034 /* Move DQS (back to orig) */
3035 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3039 /* Find middle of window for the DM bit */
3040 mid = (left_edge[0] - right_edge[0]) / 2;
3042 /* only move right, since we are not moving DQS/DQ */
3046 /* dm_marign should fail if we never find a window */
3050 dm_margin = left_edge[0] - mid;
3052 scc_mgr_apply_group_dm_out1_delay(mid);
3053 writel(0, &sdr_scc_mgr->update);
3055 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3056 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3057 right_edge[0], mid, dm_margin);
3059 gbl->fom_out += dq_margin + dqs_margin;
3061 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3062 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3063 dq_margin, dqs_margin, dm_margin);
3066 * Do not remove this line as it makes sure all of our
3067 * decisions have been applied.
3069 writel(0, &sdr_scc_mgr->update);
3070 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3073 /* calibrate the write operations */
3074 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3077 /* update info for sims */
3078 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3080 reg_file_set_stage(CAL_STAGE_WRITES);
3081 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3083 reg_file_set_group(g);
3085 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3086 set_failing_group_stage(g, CAL_STAGE_WRITES,
3087 CAL_SUBSTAGE_WRITES_CENTER);
3095 * mem_precharge_and_activate() - Precharge all banks and activate
3097 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3099 static void mem_precharge_and_activate(void)
3103 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3104 /* Test if the rank should be skipped. */
3105 if (param->skip_ranks[r])
3109 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3111 /* Precharge all banks. */
3112 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3113 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3115 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3116 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3117 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3119 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3120 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3121 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3123 /* Activate rows. */
3124 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3125 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3130 * mem_init_latency() - Configure memory RLAT and WLAT settings
3132 * Configure memory RLAT and WLAT parameters.
3134 static void mem_init_latency(void)
3137 * For AV/CV, LFIFO is hardened and always runs at full rate
3138 * so max latency in AFI clocks, used here, is correspondingly
3141 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3144 debug("%s:%d\n", __func__, __LINE__);
3147 * Read in write latency.
3148 * WL for Hard PHY does not include additive latency.
3150 wlat = readl(&data_mgr->t_wl_add);
3151 wlat += readl(&data_mgr->mem_t_add);
3153 gbl->rw_wl_nop_cycles = wlat - 1;
3155 /* Read in readl latency. */
3156 rlat = readl(&data_mgr->t_rl_add);
3158 /* Set a pretty high read latency initially. */
3159 gbl->curr_read_lat = rlat + 16;
3160 if (gbl->curr_read_lat > max_latency)
3161 gbl->curr_read_lat = max_latency;
3163 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3165 /* Advertise write latency. */
3166 writel(wlat, &phy_mgr_cfg->afi_wlat);
3169 /* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
3170 static void mem_skip_calibrate(void)
3172 uint32_t vfifo_offset;
3175 debug("%s:%d\n", __func__, __LINE__);
3176 /* Need to update every shadow register set used by the interface */
3177 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3178 r += NUM_RANKS_PER_SHADOW_REG) {
3180 * Set output phase alignment settings appropriate for
3183 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3184 scc_mgr_set_dqs_en_phase(i, 0);
3185 #if IO_DLL_CHAIN_LENGTH == 6
3186 scc_mgr_set_dqdqs_output_phase(i, 6);
3188 scc_mgr_set_dqdqs_output_phase(i, 7);
3193 * Write data arrives to the I/O two cycles before write
3194 * latency is reached (720 deg).
3195 * -> due to bit-slip in a/c bus
3196 * -> to allow board skew where dqs is longer than ck
3197 * -> how often can this happen!?
3198 * -> can claim back some ptaps for high freq
3199 * support if we can relax this, but i digress...
3201 * The write_clk leads mem_ck by 90 deg
3202 * The minimum ptap of the OPA is 180 deg
3203 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3204 * The write_clk is always delayed by 2 ptaps
3206 * Hence, to make DQS aligned to CK, we need to delay
3208 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3210 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3211 * gives us the number of ptaps, which simplies to:
3213 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3215 scc_mgr_set_dqdqs_output_phase(i, (1.25 *
3216 IO_DLL_CHAIN_LENGTH - 2));
3218 writel(0xff, &sdr_scc_mgr->dqs_ena);
3219 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3221 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3222 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3223 SCC_MGR_GROUP_COUNTER_OFFSET);
3225 writel(0xff, &sdr_scc_mgr->dq_ena);
3226 writel(0xff, &sdr_scc_mgr->dm_ena);
3227 writel(0, &sdr_scc_mgr->update);
3230 /* Compensate for simulation model behaviour */
3231 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3232 scc_mgr_set_dqs_bus_in_delay(i, 10);
3233 scc_mgr_load_dqs(i);
3235 writel(0, &sdr_scc_mgr->update);
3238 * ArriaV has hard FIFOs that can only be initialized by incrementing
3241 vfifo_offset = CALIB_VFIFO_OFFSET;
3242 for (j = 0; j < vfifo_offset; j++) {
3243 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3245 writel(0, &phy_mgr_cmd->fifo_reset);
3248 * For ACV with hard lfifo, we get the skip-cal setting from
3249 * generation-time constant.
3251 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3252 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3255 /* Memory calibration entry point */
3256 static uint32_t mem_calibrate(void)
3259 uint32_t rank_bgn, sr;
3260 uint32_t write_group, write_test_bgn;
3261 uint32_t read_group, read_test_bgn;
3262 uint32_t run_groups, current_run;
3263 uint32_t failing_groups = 0;
3264 uint32_t group_failed = 0;
3265 uint32_t sr_failed = 0;
3267 debug("%s:%d\n", __func__, __LINE__);
3269 /* Initialize the data settings */
3270 gbl->error_substage = CAL_SUBSTAGE_NIL;
3271 gbl->error_stage = CAL_STAGE_NIL;
3272 gbl->error_group = 0xff;
3276 /* Initialize WLAT and RLAT. */
3279 /* Initialize bit slips. */
3280 mem_precharge_and_activate();
3282 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3283 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3284 SCC_MGR_GROUP_COUNTER_OFFSET);
3285 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3287 scc_mgr_set_hhp_extras();
3289 scc_set_bypass_mode(i);
3292 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3294 * Set VFIFO and LFIFO to instant-on settings in skip
3297 mem_skip_calibrate();
3299 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3301 * Zero all delay chain/phase settings for all
3302 * groups and all shadow register sets.
3306 run_groups = ~param->skip_groups;
3308 for (write_group = 0, write_test_bgn = 0; write_group
3309 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3310 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3311 /* Initialized the group failure */
3314 current_run = run_groups & ((1 <<
3315 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3316 run_groups = run_groups >>
3317 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3319 if (current_run == 0)
3322 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3323 SCC_MGR_GROUP_COUNTER_OFFSET);
3324 scc_mgr_zero_group(write_group, 0);
3326 for (read_group = write_group *
3327 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3328 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3330 read_group < (write_group + 1) *
3331 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3332 RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3334 read_group++, read_test_bgn +=
3335 RW_MGR_MEM_DQ_PER_READ_DQS) {
3336 /* Calibrate the VFIFO */
3337 if (!((STATIC_CALIB_STEPS) &
3338 CALIB_SKIP_VFIFO)) {
3339 if (!rw_mgr_mem_calibrate_vfifo
3345 phy_debug_mode_flags &
3346 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3353 /* Calibrate the output side */
3354 if (group_failed == 0) {
3355 for (rank_bgn = 0, sr = 0; rank_bgn
3356 < RW_MGR_MEM_NUMBER_OF_RANKS;
3358 NUM_RANKS_PER_SHADOW_REG,
3361 if (!((STATIC_CALIB_STEPS) &
3362 CALIB_SKIP_WRITES)) {
3363 if ((STATIC_CALIB_STEPS)
3364 & CALIB_SKIP_DELAY_SWEEPS) {
3365 /* not needed in quick mode! */
3368 * Determine if this set of
3369 * ranks should be skipped
3372 if (!param->skip_shadow_regs[sr]) {
3373 if (!rw_mgr_mem_calibrate_writes
3374 (rank_bgn, write_group,
3378 phy_debug_mode_flags &
3379 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3391 if (group_failed == 0) {
3392 for (read_group = write_group *
3393 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3394 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3396 read_group < (write_group + 1)
3397 * RW_MGR_MEM_IF_READ_DQS_WIDTH
3398 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3400 read_group++, read_test_bgn +=
3401 RW_MGR_MEM_DQ_PER_READ_DQS) {
3402 if (!((STATIC_CALIB_STEPS) &
3403 CALIB_SKIP_WRITES)) {
3404 if (!rw_mgr_mem_calibrate_vfifo_end
3405 (read_group, read_test_bgn)) {
3408 if (!(gbl->phy_debug_mode_flags
3409 & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3417 if (group_failed != 0)
3422 * USER If there are any failing groups then report
3425 if (failing_groups != 0)
3428 /* Calibrate the LFIFO */
3429 if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
3431 * If we're skipping groups as part of debug,
3432 * don't calibrate LFIFO.
3434 if (param->skip_groups == 0) {
3435 if (!rw_mgr_mem_calibrate_lfifo())
3443 * Do not remove this line as it makes sure all of our decisions
3444 * have been applied.
3446 writel(0, &sdr_scc_mgr->update);
3451 * run_mem_calibrate() - Perform memory calibration
3453 * This function triggers the entire memory calibration procedure.
3455 static int run_mem_calibrate(void)
3459 debug("%s:%d\n", __func__, __LINE__);
3461 /* Reset pass/fail status shown on afi_cal_success/fail */
3462 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3464 /* Stop tracking manager. */
3465 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3467 phy_mgr_initialize();
3468 rw_mgr_mem_initialize();
3470 /* Perform the actual memory calibration. */
3471 pass = mem_calibrate();
3473 mem_precharge_and_activate();
3474 writel(0, &phy_mgr_cmd->fifo_reset);
3477 rw_mgr_mem_handoff();
3479 * In Hard PHY this is a 2-bit control:
3481 * 1: DDIO Mux Select
3483 writel(0x2, &phy_mgr_cfg->mux_sel);
3485 /* Start tracking manager. */
3486 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3492 * debug_mem_calibrate() - Report result of memory calibration
3493 * @pass: Value indicating whether calibration passed or failed
3495 * This function reports the results of the memory calibration
3496 * and writes debug information into the register file.
3498 static void debug_mem_calibrate(int pass)
3500 uint32_t debug_info;
3503 printf("%s: CALIBRATION PASSED\n", __FILE__);
3508 if (gbl->fom_in > 0xff)
3511 if (gbl->fom_out > 0xff)
3512 gbl->fom_out = 0xff;
3514 /* Update the FOM in the register file */
3515 debug_info = gbl->fom_in;
3516 debug_info |= gbl->fom_out << 8;
3517 writel(debug_info, &sdr_reg_file->fom);
3519 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3520 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3522 printf("%s: CALIBRATION FAILED\n", __FILE__);
3524 debug_info = gbl->error_stage;
3525 debug_info |= gbl->error_substage << 8;
3526 debug_info |= gbl->error_group << 16;
3528 writel(debug_info, &sdr_reg_file->failing_stage);
3529 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3530 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3532 /* Update the failing group/stage in the register file */
3533 debug_info = gbl->error_stage;
3534 debug_info |= gbl->error_substage << 8;
3535 debug_info |= gbl->error_group << 16;
3536 writel(debug_info, &sdr_reg_file->failing_stage);
3539 printf("%s: Calibration complete\n", __FILE__);
3543 * hc_initialize_rom_data() - Initialize ROM data
3545 * Initialize ROM data.
3547 static void hc_initialize_rom_data(void)
3551 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3552 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3553 writel(inst_rom_init[i], addr + (i << 2));
3555 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3556 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3557 writel(ac_rom_init[i], addr + (i << 2));
3561 * initialize_reg_file() - Initialize SDR register file
3563 * Initialize SDR register file.
3565 static void initialize_reg_file(void)
3567 /* Initialize the register file with the correct data */
3568 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3569 writel(0, &sdr_reg_file->debug_data_addr);
3570 writel(0, &sdr_reg_file->cur_stage);
3571 writel(0, &sdr_reg_file->fom);
3572 writel(0, &sdr_reg_file->failing_stage);
3573 writel(0, &sdr_reg_file->debug1);
3574 writel(0, &sdr_reg_file->debug2);
3578 * initialize_hps_phy() - Initialize HPS PHY
3580 * Initialize HPS PHY.
3582 static void initialize_hps_phy(void)
3586 * Tracking also gets configured here because it's in the
3589 uint32_t trk_sample_count = 7500;
3590 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3592 * Format is number of outer loops in the 16 MSB, sample
3597 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3598 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3599 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3600 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3601 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3602 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3604 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3605 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3607 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3608 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3610 writel(reg, &sdr_ctrl->phy_ctrl0);
3613 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3615 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3616 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3617 trk_long_idle_sample_count);
3618 writel(reg, &sdr_ctrl->phy_ctrl1);
3621 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3622 trk_long_idle_sample_count >>
3623 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3624 writel(reg, &sdr_ctrl->phy_ctrl2);
3628 * initialize_tracking() - Initialize tracking
3630 * Initialize the register file with usable initial data.
3632 static void initialize_tracking(void)
3635 * Initialize the register file with the correct data.
3636 * Compute usable version of value in case we skip full
3637 * computation later.
3639 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3640 &sdr_reg_file->dtaps_per_ptap);
3642 /* trk_sample_count */
3643 writel(7500, &sdr_reg_file->trk_sample_count);
3645 /* longidle outer loop [15:0] */
3646 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3649 * longidle sample count [31:24]
3650 * trfc, worst case of 933Mhz 4Gb [23:16]
3651 * trcd, worst case [15:8]
3654 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3655 &sdr_reg_file->delays);
3658 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3659 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3660 &sdr_reg_file->trk_rw_mgr_addr);
3662 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3663 &sdr_reg_file->trk_read_dqs_width);
3666 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3667 &sdr_reg_file->trk_rfsh);
3670 int sdram_calibration_full(void)
3672 struct param_type my_param;
3673 struct gbl_type my_gbl;
3676 memset(&my_param, 0, sizeof(my_param));
3677 memset(&my_gbl, 0, sizeof(my_gbl));
3682 /* Set the calibration enabled by default */
3683 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3685 * Only sweep all groups (regardless of fail state) by default
3686 * Set enabled read test by default.
3688 #if DISABLE_GUARANTEED_READ
3689 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3691 /* Initialize the register file */
3692 initialize_reg_file();
3694 /* Initialize any PHY CSR */
3695 initialize_hps_phy();
3697 scc_mgr_initialize();
3699 initialize_tracking();
3701 printf("%s: Preparing to start memory calibration\n", __FILE__);
3703 debug("%s:%d\n", __func__, __LINE__);
3704 debug_cond(DLEVEL == 1,
3705 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3706 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3707 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3708 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3709 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3710 debug_cond(DLEVEL == 1,
3711 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3712 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3713 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3714 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3715 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3716 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3717 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3718 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3719 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3720 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3721 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3722 IO_IO_OUT2_DELAY_MAX);
3723 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3724 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3726 hc_initialize_rom_data();
3728 /* update info for sims */
3729 reg_file_set_stage(CAL_STAGE_NIL);
3730 reg_file_set_group(0);
3733 * Load global needed for those actions that require
3734 * some dynamic calibration support.
3736 dyn_calib_steps = STATIC_CALIB_STEPS;
3738 * Load global to allow dynamic selection of delay loop settings
3739 * based on calibration mode.
3741 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3742 skip_delay_mask = 0xff;
3744 skip_delay_mask = 0x0;
3746 pass = run_mem_calibrate();
3747 debug_mem_calibrate(pass);