git.sur5r.net Git - u-boot/blob - drivers/ddr/altera/sequencer.c

   1 /*
   2  * Copyright Altera Corporation (C) 2012-2015
   3  *
   4  * SPDX-License-Identifier:    BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/sdram.h>
  10 #include <errno.h>
  11 #include "sequencer.h"
  12 #include "sequencer_auto.h"
  13 #include "sequencer_auto_ac_init.h"
  14 #include "sequencer_auto_inst_init.h"
  15 #include "sequencer_defines.h"
  16
  17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  18         (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  19
  20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  21         (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  22
  23 static struct socfpga_sdr_reg_file *sdr_reg_file =
  24         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  25
  26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  27         (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  28
  29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  30         (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  31
  32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  33         (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  34
  35 static struct socfpga_data_mgr *data_mgr =
  36         (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  37
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  40
  41 #define DELTA_D         1
  42
  43 /*
  44  * In order to reduce ROM size, most of the selectable calibration steps are
  45  * decided at compile time based on the user's calibration mode selection,
  46  * as captured by the STATIC_CALIB_STEPS selection below.
  47  *
  48  * However, to support simulation-time selection of fast simulation mode, where
  49  * we skip everything except the bare minimum, we need a few of the steps to
  50  * be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
  51  * check, which is based on the rtl-supplied value, or we dynamically compute
  52  * the value to use based on the dynamically-chosen calibration mode
  53  */
  54
  55 #define DLEVEL 0
  56 #define STATIC_IN_RTL_SIM 0
  57 #define STATIC_SKIP_DELAY_LOOPS 0
  58
  59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
  60         STATIC_SKIP_DELAY_LOOPS)
  61
  62 /* calibration steps requested by the rtl */
  63 uint16_t dyn_calib_steps;
  64
  65 /*
  66  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  67  * instead of static, we use boolean logic to select between
  68  * non-skip and skip values
  69  *
  70  * The mask is set to include all bits when not-skipping, but is
  71  * zero when skipping
  72  */
  73
  74 uint16_t skip_delay_mask;       /* mask off bits when skipping/not-skipping */
  75
  76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
  77         ((non_skip_value) & skip_delay_mask)
  78
  79 struct gbl_type *gbl;
  80 struct param_type *param;
  81 uint32_t curr_shadow_reg;
  82
  83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
  84         uint32_t write_group, uint32_t use_dm,
  85         uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
  86
  87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
  88         uint32_t substage)
  89 {
  90         /*
  91          * Only set the global stage if there was not been any other
  92          * failing group
  93          */
  94         if (gbl->error_stage == CAL_STAGE_NIL)  {
  95                 gbl->error_substage = substage;
  96                 gbl->error_stage = stage;
  97                 gbl->error_group = group;
  98         }
  99 }
 100
 101 static void reg_file_set_group(u16 set_group)
 102 {
 103         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
 104 }
 105
 106 static void reg_file_set_stage(u8 set_stage)
 107 {
 108         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
 109 }
 110
 111 static void reg_file_set_sub_stage(u8 set_sub_stage)
 112 {
 113         set_sub_stage &= 0xff;
 114         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
 115 }
 116
 117 /**
 118  * phy_mgr_initialize() - Initialize PHY Manager
 119  *
 120  * Initialize PHY Manager.
 121  */
 122 static void phy_mgr_initialize(void)
 123 {
 124         u32 ratio;
 125
 126         debug("%s:%d\n", __func__, __LINE__);
 127         /* Calibration has control over path to memory */
 128         /*
 129          * In Hard PHY this is a 2-bit control:
 130          * 0: AFI Mux Select
 131          * 1: DDIO Mux Select
 132          */
 133         writel(0x3, &phy_mgr_cfg->mux_sel);
 134
 135         /* USER memory clock is not stable we begin initialization  */
 136         writel(0, &phy_mgr_cfg->reset_mem_stbl);
 137
 138         /* USER calibration status all set to zero */
 139         writel(0, &phy_mgr_cfg->cal_status);
 140
 141         writel(0, &phy_mgr_cfg->cal_debug_info);
 142
 143         /* Init params only if we do NOT skip calibration. */
 144         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
 145                 return;
 146
 147         ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
 148                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
 149         param->read_correct_mask_vg = (1 << ratio) - 1;
 150         param->write_correct_mask_vg = (1 << ratio) - 1;
 151         param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
 152         param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
 153         ratio = RW_MGR_MEM_DATA_WIDTH /
 154                 RW_MGR_MEM_DATA_MASK_WIDTH;
 155         param->dm_correct_mask = (1 << ratio) - 1;
 156 }
 157
 158 /**
 159  * set_rank_and_odt_mask() - Set Rank and ODT mask
 160  * @rank:       Rank mask
 161  * @odt_mode:   ODT mode, OFF or READ_WRITE
 162  *
 163  * Set Rank and ODT mask (On-Die Termination).
 164  */
 165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
 166 {
 167         u32 odt_mask_0 = 0;
 168         u32 odt_mask_1 = 0;
 169         u32 cs_and_odt_mask;
 170
 171         if (odt_mode == RW_MGR_ODT_MODE_OFF) {
 172                 odt_mask_0 = 0x0;
 173                 odt_mask_1 = 0x0;
 174         } else {        /* RW_MGR_ODT_MODE_READ_WRITE */
 175                 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
 176                 case 1: /* 1 Rank */
 177                         /* Read: ODT = 0 ; Write: ODT = 1 */
 178                         odt_mask_0 = 0x0;
 179                         odt_mask_1 = 0x1;
 180                         break;
 181                 case 2: /* 2 Ranks */
 182                         if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
 183                                 /*
 184                                  * - Dual-Slot , Single-Rank (1 CS per DIMM)
 185                                  *   OR
 186                                  * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
 187                                  *
 188                                  * Since MEM_NUMBER_OF_RANKS is 2, they
 189                                  * are both single rank with 2 CS each
 190                                  * (special for RDIMM).
 191                                  *
 192                                  * Read: Turn on ODT on the opposite rank
 193                                  * Write: Turn on ODT on all ranks
 194                                  */
 195                                 odt_mask_0 = 0x3 & ~(1 << rank);
 196                                 odt_mask_1 = 0x3;
 197                         } else {
 198                                 /*
 199                                  * - Single-Slot , Dual-Rank (2 CS per DIMM)
 200                                  *
 201                                  * Read: Turn on ODT off on all ranks
 202                                  * Write: Turn on ODT on active rank
 203                                  */
 204                                 odt_mask_0 = 0x0;
 205                                 odt_mask_1 = 0x3 & (1 << rank);
 206                         }
 207                         break;
 208                 case 4: /* 4 Ranks */
 209                         /* Read:
 210                          * ----------+-----------------------+
 211                          *           |         ODT           |
 212                          * Read From +-----------------------+
 213                          *   Rank    |  3  |  2  |  1  |  0  |
 214                          * ----------+-----+-----+-----+-----+
 215                          *     0     |  0  |  1  |  0  |  0  |
 216                          *     1     |  1  |  0  |  0  |  0  |
 217                          *     2     |  0  |  0  |  0  |  1  |
 218                          *     3     |  0  |  0  |  1  |  0  |
 219                          * ----------+-----+-----+-----+-----+
 220                          *
 221                          * Write:
 222                          * ----------+-----------------------+
 223                          *           |         ODT           |
 224                          * Write To  +-----------------------+
 225                          *   Rank    |  3  |  2  |  1  |  0  |
 226                          * ----------+-----+-----+-----+-----+
 227                          *     0     |  0  |  1  |  0  |  1  |
 228                          *     1     |  1  |  0  |  1  |  0  |
 229                          *     2     |  0  |  1  |  0  |  1  |
 230                          *     3     |  1  |  0  |  1  |  0  |
 231                          * ----------+-----+-----+-----+-----+
 232                          */
 233                         switch (rank) {
 234                         case 0:
 235                                 odt_mask_0 = 0x4;
 236                                 odt_mask_1 = 0x5;
 237                                 break;
 238                         case 1:
 239                                 odt_mask_0 = 0x8;
 240                                 odt_mask_1 = 0xA;
 241                                 break;
 242                         case 2:
 243                                 odt_mask_0 = 0x1;
 244                                 odt_mask_1 = 0x5;
 245                                 break;
 246                         case 3:
 247                                 odt_mask_0 = 0x2;
 248                                 odt_mask_1 = 0xA;
 249                                 break;
 250                         }
 251                         break;
 252                 }
 253         }
 254
 255         cs_and_odt_mask = (0xFF & ~(1 << rank)) |
 256                           ((0xFF & odt_mask_0) << 8) |
 257                           ((0xFF & odt_mask_1) << 16);
 258         writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 259                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 260 }
 261
 262 /**
 263  * scc_mgr_set() - Set SCC Manager register
 264  * @off:        Base offset in SCC Manager space
 265  * @grp:        Read/Write group
 266  * @val:        Value to be set
 267  *
 268  * This function sets the SCC Manager (Scan Chain Control Manager) register.
 269  */
 270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
 271 {
 272         writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
 273 }
 274
 275 /**
 276  * scc_mgr_initialize() - Initialize SCC Manager registers
 277  *
 278  * Initialize SCC Manager registers.
 279  */
 280 static void scc_mgr_initialize(void)
 281 {
 282         /*
 283          * Clear register file for HPS. 16 (2^4) is the size of the
 284          * full register file in the scc mgr:
 285          *      RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
 286          *                             MEM_IF_READ_DQS_WIDTH - 1);
 287          */
 288         int i;
 289
 290         for (i = 0; i < 16; i++) {
 291                 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 292                            __func__, __LINE__, i);
 293                 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
 294         }
 295 }
 296
 297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
 298 {
 299         scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
 300 }
 301
 302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
 303 {
 304         scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
 305 }
 306
 307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 308 {
 309         scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
 310 }
 311
 312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 313 {
 314         scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 315 }
 316
 317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
 318 {
 319         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 320                     delay);
 321 }
 322
 323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
 324 {
 325         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
 326 }
 327
 328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
 329 {
 330         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
 331 }
 332
 333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
 334 {
 335         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 336                     delay);
 337 }
 338
 339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
 340 {
 341         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
 342                     RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
 343                     delay);
 344 }
 345
 346 /* load up dqs config settings */
 347 static void scc_mgr_load_dqs(uint32_t dqs)
 348 {
 349         writel(dqs, &sdr_scc_mgr->dqs_ena);
 350 }
 351
 352 /* load up dqs io config settings */
 353 static void scc_mgr_load_dqs_io(void)
 354 {
 355         writel(0, &sdr_scc_mgr->dqs_io_ena);
 356 }
 357
 358 /* load up dq config settings */
 359 static void scc_mgr_load_dq(uint32_t dq_in_group)
 360 {
 361         writel(dq_in_group, &sdr_scc_mgr->dq_ena);
 362 }
 363
 364 /* load up dm config settings */
 365 static void scc_mgr_load_dm(uint32_t dm)
 366 {
 367         writel(dm, &sdr_scc_mgr->dm_ena);
 368 }
 369
 370 /**
 371  * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
 372  * @off:        Base offset in SCC Manager space
 373  * @grp:        Read/Write group
 374  * @val:        Value to be set
 375  * @update:     If non-zero, trigger SCC Manager update for all ranks
 376  *
 377  * This function sets the SCC Manager (Scan Chain Control Manager) register
 378  * and optionally triggers the SCC update for all ranks.
 379  */
 380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
 381                                   const int update)
 382 {
 383         u32 r;
 384
 385         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 386              r += NUM_RANKS_PER_SHADOW_REG) {
 387                 scc_mgr_set(off, grp, val);
 388
 389                 if (update || (r == 0)) {
 390                         writel(grp, &sdr_scc_mgr->dqs_ena);
 391                         writel(0, &sdr_scc_mgr->update);
 392                 }
 393         }
 394 }
 395
 396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
 397 {
 398         /*
 399          * USER although the h/w doesn't support different phases per
 400          * shadow register, for simplicity our scc manager modeling
 401          * keeps different phase settings per shadow reg, and it's
 402          * important for us to keep them in sync to match h/w.
 403          * for efficiency, the scan chain update should occur only
 404          * once to sr0.
 405          */
 406         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
 407                               read_group, phase, 0);
 408 }
 409
 410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
 411                                                      uint32_t phase)
 412 {
 413         /*
 414          * USER although the h/w doesn't support different phases per
 415          * shadow register, for simplicity our scc manager modeling
 416          * keeps different phase settings per shadow reg, and it's
 417          * important for us to keep them in sync to match h/w.
 418          * for efficiency, the scan chain update should occur only
 419          * once to sr0.
 420          */
 421         scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
 422                               write_group, phase, 0);
 423 }
 424
 425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 426                                                uint32_t delay)
 427 {
 428         /*
 429          * In shadow register mode, the T11 settings are stored in
 430          * registers in the core, which are updated by the DQS_ENA
 431          * signals. Not issuing the SCC_MGR_UPD command allows us to
 432          * save lots of rank switching overhead, by calling
 433          * select_shadow_regs_for_update with update_scan_chains
 434          * set to 0.
 435          */
 436         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
 437                               read_group, delay, 1);
 438         writel(0, &sdr_scc_mgr->update);
 439 }
 440
 441 /**
 442  * scc_mgr_set_oct_out1_delay() - Set OCT output delay
 443  * @write_group:        Write group
 444  * @delay:              Delay value
 445  *
 446  * This function sets the OCT output delay in SCC manager.
 447  */
 448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
 449 {
 450         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 451                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 452         const int base = write_group * ratio;
 453         int i;
 454         /*
 455          * Load the setting in the SCC manager
 456          * Although OCT affects only write data, the OCT delay is controlled
 457          * by the DQS logic block which is instantiated once per read group.
 458          * For protocols where a write group consists of multiple read groups,
 459          * the setting must be set multiple times.
 460          */
 461         for (i = 0; i < ratio; i++)
 462                 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
 463 }
 464
 465 /**
 466  * scc_mgr_set_hhp_extras() - Set HHP extras.
 467  *
 468  * Load the fixed setting in the SCC manager HHP extras.
 469  */
 470 static void scc_mgr_set_hhp_extras(void)
 471 {
 472         /*
 473          * Load the fixed setting in the SCC manager
 474          * bits: 0:0 = 1'b1     - DQS bypass
 475          * bits: 1:1 = 1'b1     - DQ bypass
 476          * bits: 4:2 = 3'b001   - rfifo_mode
 477          * bits: 6:5 = 2'b01    - rfifo clock_select
 478          * bits: 7:7 = 1'b0     - separate gating from ungating setting
 479          * bits: 8:8 = 1'b0     - separate OE from Output delay setting
 480          */
 481         const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
 482                           (1 << 2) | (1 << 1) | (1 << 0);
 483         const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
 484                          SCC_MGR_HHP_GLOBALS_OFFSET |
 485                          SCC_MGR_HHP_EXTRAS_OFFSET;
 486
 487         debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
 488                    __func__, __LINE__);
 489         writel(value, addr);
 490         debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
 491                    __func__, __LINE__);
 492 }
 493
 494 /**
 495  * scc_mgr_zero_all() - Zero all DQS config
 496  *
 497  * Zero all DQS config.
 498  */
 499 static void scc_mgr_zero_all(void)
 500 {
 501         int i, r;
 502
 503         /*
 504          * USER Zero all DQS config settings, across all groups and all
 505          * shadow registers
 506          */
 507         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 508              r += NUM_RANKS_PER_SHADOW_REG) {
 509                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
 510                         /*
 511                          * The phases actually don't exist on a per-rank basis,
 512                          * but there's no harm updating them several times, so
 513                          * let's keep the code simple.
 514                          */
 515                         scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
 516                         scc_mgr_set_dqs_en_phase(i, 0);
 517                         scc_mgr_set_dqs_en_delay(i, 0);
 518                 }
 519
 520                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
 521                         scc_mgr_set_dqdqs_output_phase(i, 0);
 522                         /* Arria V/Cyclone V don't have out2. */
 523                         scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
 524                 }
 525         }
 526
 527         /* Multicast to all DQS group enables. */
 528         writel(0xff, &sdr_scc_mgr->dqs_ena);
 529         writel(0, &sdr_scc_mgr->update);
 530 }
 531
 532 /**
 533  * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
 534  * @write_group:        Write group
 535  *
 536  * Set bypass mode and trigger SCC update.
 537  */
 538 static void scc_set_bypass_mode(const u32 write_group)
 539 {
 540         /* Multicast to all DQ enables. */
 541         writel(0xff, &sdr_scc_mgr->dq_ena);
 542         writel(0xff, &sdr_scc_mgr->dm_ena);
 543
 544         /* Update current DQS IO enable. */
 545         writel(0, &sdr_scc_mgr->dqs_io_ena);
 546
 547         /* Update the DQS logic. */
 548         writel(write_group, &sdr_scc_mgr->dqs_ena);
 549
 550         /* Hit update. */
 551         writel(0, &sdr_scc_mgr->update);
 552 }
 553
 554 /**
 555  * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
 556  * @write_group:        Write group
 557  *
 558  * Load DQS settings for Write Group, do not trigger SCC update.
 559  */
 560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
 561 {
 562         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 563                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 564         const int base = write_group * ratio;
 565         int i;
 566         /*
 567          * Load the setting in the SCC manager
 568          * Although OCT affects only write data, the OCT delay is controlled
 569          * by the DQS logic block which is instantiated once per read group.
 570          * For protocols where a write group consists of multiple read groups,
 571          * the setting must be set multiple times.
 572          */
 573         for (i = 0; i < ratio; i++)
 574                 writel(base + i, &sdr_scc_mgr->dqs_ena);
 575 }
 576
 577 /**
 578  * scc_mgr_zero_group() - Zero all configs for a group
 579  *
 580  * Zero DQ, DM, DQS and OCT configs for a group.
 581  */
 582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
 583 {
 584         int i, r;
 585
 586         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 587              r += NUM_RANKS_PER_SHADOW_REG) {
 588                 /* Zero all DQ config settings. */
 589                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 590                         scc_mgr_set_dq_out1_delay(i, 0);
 591                         if (!out_only)
 592                                 scc_mgr_set_dq_in_delay(i, 0);
 593                 }
 594
 595                 /* Multicast to all DQ enables. */
 596                 writel(0xff, &sdr_scc_mgr->dq_ena);
 597
 598                 /* Zero all DM config settings. */
 599                 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 600                         scc_mgr_set_dm_out1_delay(i, 0);
 601
 602                 /* Multicast to all DM enables. */
 603                 writel(0xff, &sdr_scc_mgr->dm_ena);
 604
 605                 /* Zero all DQS IO settings. */
 606                 if (!out_only)
 607                         scc_mgr_set_dqs_io_in_delay(0);
 608
 609                 /* Arria V/Cyclone V don't have out2. */
 610                 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
 611                 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 612                 scc_mgr_load_dqs_for_write_group(write_group);
 613
 614                 /* Multicast to all DQS IO enables (only 1 in total). */
 615                 writel(0, &sdr_scc_mgr->dqs_io_ena);
 616
 617                 /* Hit update to zero everything. */
 618                 writel(0, &sdr_scc_mgr->update);
 619         }
 620 }
 621
 622 /*
 623  * apply and load a particular input delay for the DQ pins in a group
 624  * group_bgn is the index of the first dq pin (in the write group)
 625  */
 626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
 627 {
 628         uint32_t i, p;
 629
 630         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
 631                 scc_mgr_set_dq_in_delay(p, delay);
 632                 scc_mgr_load_dq(p);
 633         }
 634 }
 635
 636 /**
 637  * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
 638  * @delay:              Delay value
 639  *
 640  * Apply and load a particular output delay for the DQ pins in a group.
 641  */
 642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
 643 {
 644         int i;
 645
 646         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 647                 scc_mgr_set_dq_out1_delay(i, delay);
 648                 scc_mgr_load_dq(i);
 649         }
 650 }
 651
 652 /* apply and load a particular output delay for the DM pins in a group */
 653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
 654 {
 655         uint32_t i;
 656
 657         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 658                 scc_mgr_set_dm_out1_delay(i, delay1);
 659                 scc_mgr_load_dm(i);
 660         }
 661 }
 662
 663
 664 /* apply and load delay on both DQS and OCT out1 */
 665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
 666                                                     uint32_t delay)
 667 {
 668         scc_mgr_set_dqs_out1_delay(delay);
 669         scc_mgr_load_dqs_io();
 670
 671         scc_mgr_set_oct_out1_delay(write_group, delay);
 672         scc_mgr_load_dqs_for_write_group(write_group);
 673 }
 674
 675 /**
 676  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
 677  * @write_group:        Write group
 678  * @delay:              Delay value
 679  *
 680  * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
 681  */
 682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 683                                                   const u32 delay)
 684 {
 685         u32 i, new_delay;
 686
 687         /* DQ shift */
 688         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
 689                 scc_mgr_load_dq(i);
 690
 691         /* DM shift */
 692         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 693                 scc_mgr_load_dm(i);
 694
 695         /* DQS shift */
 696         new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
 697         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 698                 debug_cond(DLEVEL == 1,
 699                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 700                            __func__, __LINE__, write_group, delay, new_delay,
 701                            IO_IO_OUT2_DELAY_MAX,
 702                            new_delay - IO_IO_OUT2_DELAY_MAX);
 703                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 704                 scc_mgr_set_dqs_out1_delay(new_delay);
 705         }
 706
 707         scc_mgr_load_dqs_io();
 708
 709         /* OCT shift */
 710         new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
 711         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 712                 debug_cond(DLEVEL == 1,
 713                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 714                            __func__, __LINE__, write_group, delay,
 715                            new_delay, IO_IO_OUT2_DELAY_MAX,
 716                            new_delay - IO_IO_OUT2_DELAY_MAX);
 717                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 718                 scc_mgr_set_oct_out1_delay(write_group, new_delay);
 719         }
 720
 721         scc_mgr_load_dqs_for_write_group(write_group);
 722 }
 723
 724 /**
 725  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
 726  * @write_group:        Write group
 727  * @delay:              Delay value
 728  *
 729  * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
 730  */
 731 static void
 732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
 733                                                 const u32 delay)
 734 {
 735         int r;
 736
 737         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 738              r += NUM_RANKS_PER_SHADOW_REG) {
 739                 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
 740                 writel(0, &sdr_scc_mgr->update);
 741         }
 742 }
 743
 744 /**
 745  * set_jump_as_return() - Return instruction optimization
 746  *
 747  * Optimization used to recover some slots in ddr3 inst_rom could be
 748  * applied to other protocols if we wanted to
 749  */
 750 static void set_jump_as_return(void)
 751 {
 752         /*
 753          * To save space, we replace return with jump to special shared
 754          * RETURN instruction so we set the counter to large value so that
 755          * we always jump.
 756          */
 757         writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
 758         writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 759 }
 760
 761 /*
 762  * should always use constants as argument to ensure all computations are
 763  * performed at compile time
 764  */
 765 static void delay_for_n_mem_clocks(const uint32_t clocks)
 766 {
 767         uint32_t afi_clocks;
 768         uint8_t inner = 0;
 769         uint8_t outer = 0;
 770         uint16_t c_loop = 0;
 771
 772         debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
 773
 774
 775         afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
 776         /* scale (rounding up) to get afi clocks */
 777
 778         /*
 779          * Note, we don't bother accounting for being off a little bit
 780          * because of a few extra instructions in outer loops
 781          * Note, the loops have a test at the end, and do the test before
 782          * the decrement, and so always perform the loop
 783          * 1 time more than the counter value
 784          */
 785         if (afi_clocks == 0) {
 786                 ;
 787         } else if (afi_clocks <= 0x100) {
 788                 inner = afi_clocks-1;
 789                 outer = 0;
 790                 c_loop = 0;
 791         } else if (afi_clocks <= 0x10000) {
 792                 inner = 0xff;
 793                 outer = (afi_clocks-1) >> 8;
 794                 c_loop = 0;
 795         } else {
 796                 inner = 0xff;
 797                 outer = 0xff;
 798                 c_loop = (afi_clocks-1) >> 16;
 799         }
 800
 801         /*
 802          * rom instructions are structured as follows:
 803          *
 804          *    IDLE_LOOP2: jnz cntr0, TARGET_A
 805          *    IDLE_LOOP1: jnz cntr1, TARGET_B
 806          *                return
 807          *
 808          * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
 809          * TARGET_B is set to IDLE_LOOP2 as well
 810          *
 811          * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
 812          * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
 813          *
 814          * a little confusing, but it helps save precious space in the inst_rom
 815          * and sequencer rom and keeps the delays more accurate and reduces
 816          * overhead
 817          */
 818         if (afi_clocks <= 0x100) {
 819                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 820                         &sdr_rw_load_mgr_regs->load_cntr1);
 821
 822                 writel(RW_MGR_IDLE_LOOP1,
 823                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 824
 825                 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 826                                           RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 827         } else {
 828                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 829                         &sdr_rw_load_mgr_regs->load_cntr0);
 830
 831                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
 832                         &sdr_rw_load_mgr_regs->load_cntr1);
 833
 834                 writel(RW_MGR_IDLE_LOOP2,
 835                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 836
 837                 writel(RW_MGR_IDLE_LOOP2,
 838                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 839
 840                 /* hack to get around compiler not being smart enough */
 841                 if (afi_clocks <= 0x10000) {
 842                         /* only need to run once */
 843                         writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 844                                                   RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 845                 } else {
 846                         do {
 847                                 writel(RW_MGR_IDLE_LOOP2,
 848                                         SDR_PHYGRP_RWMGRGRP_ADDRESS |
 849                                         RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 850                         } while (c_loop-- != 0);
 851                 }
 852         }
 853         debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
 854 }
 855
 856 /**
 857  * rw_mgr_mem_init_load_regs() - Load instruction registers
 858  * @cntr0:      Counter 0 value
 859  * @cntr1:      Counter 1 value
 860  * @cntr2:      Counter 2 value
 861  * @jump:       Jump instruction value
 862  *
 863  * Load instruction registers.
 864  */
 865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
 866 {
 867         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 868                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 869
 870         /* Load counters */
 871         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
 872                &sdr_rw_load_mgr_regs->load_cntr0);
 873         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
 874                &sdr_rw_load_mgr_regs->load_cntr1);
 875         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
 876                &sdr_rw_load_mgr_regs->load_cntr2);
 877
 878         /* Load jump address */
 879         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 880         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 881         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 882
 883         /* Execute count instruction */
 884         writel(jump, grpaddr);
 885 }
 886
 887 /**
 888  * rw_mgr_mem_load_user() - Load user calibration values
 889  * @fin1:       Final instruction 1
 890  * @fin2:       Final instruction 2
 891  * @precharge:  If 1, precharge the banks at the end
 892  *
 893  * Load user calibration values and optionally precharge the banks.
 894  */
 895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
 896                                  const int precharge)
 897 {
 898         u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 899                       RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 900         u32 r;
 901
 902         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
 903                 if (param->skip_ranks[r]) {
 904                         /* request to skip the rank */
 905                         continue;
 906                 }
 907
 908                 /* set rank */
 909                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
 910
 911                 /* precharge all banks ... */
 912                 if (precharge)
 913                         writel(RW_MGR_PRECHARGE_ALL, grpaddr);
 914
 915                 /*
 916                  * USER Use Mirror-ed commands for odd ranks if address
 917                  * mirrorring is on
 918                  */
 919                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
 920                         set_jump_as_return();
 921                         writel(RW_MGR_MRS2_MIRR, grpaddr);
 922                         delay_for_n_mem_clocks(4);
 923                         set_jump_as_return();
 924                         writel(RW_MGR_MRS3_MIRR, grpaddr);
 925                         delay_for_n_mem_clocks(4);
 926                         set_jump_as_return();
 927                         writel(RW_MGR_MRS1_MIRR, grpaddr);
 928                         delay_for_n_mem_clocks(4);
 929                         set_jump_as_return();
 930                         writel(fin1, grpaddr);
 931                 } else {
 932                         set_jump_as_return();
 933                         writel(RW_MGR_MRS2, grpaddr);
 934                         delay_for_n_mem_clocks(4);
 935                         set_jump_as_return();
 936                         writel(RW_MGR_MRS3, grpaddr);
 937                         delay_for_n_mem_clocks(4);
 938                         set_jump_as_return();
 939                         writel(RW_MGR_MRS1, grpaddr);
 940                         set_jump_as_return();
 941                         writel(fin2, grpaddr);
 942                 }
 943
 944                 if (precharge)
 945                         continue;
 946
 947                 set_jump_as_return();
 948                 writel(RW_MGR_ZQCL, grpaddr);
 949
 950                 /* tZQinit = tDLLK = 512 ck cycles */
 951                 delay_for_n_mem_clocks(512);
 952         }
 953 }
 954
 955 /**
 956  * rw_mgr_mem_initialize() - Initialize RW Manager
 957  *
 958  * Initialize RW Manager.
 959  */
 960 static void rw_mgr_mem_initialize(void)
 961 {
 962         debug("%s:%d\n", __func__, __LINE__);
 963
 964         /* The reset / cke part of initialization is broadcasted to all ranks */
 965         writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 966                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 967
 968         /*
 969          * Here's how you load register for a loop
 970          * Counters are located @ 0x800
 971          * Jump address are located @ 0xC00
 972          * For both, registers 0 to 3 are selected using bits 3 and 2, like
 973          * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
 974          * I know this ain't pretty, but Avalon bus throws away the 2 least
 975          * significant bits
 976          */
 977
 978         /* Start with memory RESET activated */
 979
 980         /* tINIT = 200us */
 981
 982         /*
 983          * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
 984          * If a and b are the number of iteration in 2 nested loops
 985          * it takes the following number of cycles to complete the operation:
 986          * number_of_cycles = ((2 + n) * a + 2) * b
 987          * where n is the number of instruction in the inner loop
 988          * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
 989          * b = 6A
 990          */
 991         rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
 992                                   SEQ_TINIT_CNTR2_VAL,
 993                                   RW_MGR_INIT_RESET_0_CKE_0);
 994
 995         /* Indicate that memory is stable. */
 996         writel(1, &phy_mgr_cfg->reset_mem_stbl);
 997
 998         /*
 999          * transition the RESET to high
1000          * Wait for 500us
1001          */
1002
1003         /*
1004          * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005          * If a and b are the number of iteration in 2 nested loops
1006          * it takes the following number of cycles to complete the operation
1007          * number_of_cycles = ((2 + n) * a + 2) * b
1008          * where n is the number of instruction in the inner loop
1009          * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1010          * b = FF
1011          */
1012         rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013                                   SEQ_TRESET_CNTR2_VAL,
1014                                   RW_MGR_INIT_RESET_1_CKE_0);
1015
1016         /* Bring up clock enable. */
1017
1018         /* tXRP < 250 ck cycles */
1019         delay_for_n_mem_clocks(250);
1020
1021         rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022                              0);
1023 }
1024
1025 /*
1026  * At the end of calibration we have to program the user settings in, and
1027  * USER  hand off the memory to the user.
1028  */
1029 static void rw_mgr_mem_handoff(void)
1030 {
1031         rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1032         /*
1033          * USER  need to wait tMOD (12CK or 15ns) time before issuing
1034          * other commands, but we will have plenty of NIOS cycles before
1035          * actual handoff so its okay.
1036          */
1037 }
1038
1039 /**
1040  * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041  * @rank_bgn:   Rank number
1042  * @group:      Read/Write Group
1043  * @all_ranks:  Test all ranks
1044  *
1045  * Performs a guaranteed read on the patterns we are going to use during a
1046  * read test to ensure memory works.
1047  */
1048 static int
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050                                         const u32 all_ranks)
1051 {
1052         const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053                          RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054         const u32 addr_offset =
1055                          (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056         const u32 rank_end = all_ranks ?
1057                                 RW_MGR_MEM_NUMBER_OF_RANKS :
1058                                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059         const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061         const u32 correct_mask_vg = param->read_correct_mask_vg;
1062
1063         u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1064         int vg, r;
1065         int ret = 0;
1066
1067         bit_chk = param->read_correct_mask;
1068
1069         for (r = rank_bgn; r < rank_end; r++) {
1070                 /* Request to skip the rank */
1071                 if (param->skip_ranks[r])
1072                         continue;
1073
1074                 /* Set rank */
1075                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1076
1077                 /* Load up a constant bursts of read commands */
1078                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079                 writel(RW_MGR_GUARANTEED_READ,
1080                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1081
1082                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083                 writel(RW_MGR_GUARANTEED_READ_CONT,
1084                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1085
1086                 tmp_bit_chk = 0;
1087                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1088                      vg >= 0; vg--) {
1089                         /* Reset the FIFOs to get pointers to known state. */
1090                         writel(0, &phy_mgr_cmd->fifo_reset);
1091                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093                         writel(RW_MGR_GUARANTEED_READ,
1094                                addr + addr_offset + (vg << 2));
1095
1096                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097                         tmp_bit_chk <<= shift_ratio;
1098                         tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1099                 }
1100
1101                 bit_chk &= tmp_bit_chk;
1102         }
1103
1104         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1105
1106         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1107
1108         if (bit_chk != param->read_correct_mask)
1109                 ret = -EIO;
1110
1111         debug_cond(DLEVEL == 1,
1112                    "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113                    __func__, __LINE__, group, bit_chk,
1114                    param->read_correct_mask, ret);
1115
1116         return ret;
1117 }
1118
1119 /**
1120  * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121  * @rank_bgn:   Rank number
1122  * @all_ranks:  Test all ranks
1123  *
1124  * Load up the patterns we are going to use during a read test.
1125  */
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127                                                     const int all_ranks)
1128 {
1129         const u32 rank_end = all_ranks ?
1130                         RW_MGR_MEM_NUMBER_OF_RANKS :
1131                         (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1132         u32 r;
1133
1134         debug("%s:%d\n", __func__, __LINE__);
1135
1136         for (r = rank_bgn; r < rank_end; r++) {
1137                 if (param->skip_ranks[r])
1138                         /* request to skip the rank */
1139                         continue;
1140
1141                 /* set rank */
1142                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1143
1144                 /* Load up a constant bursts */
1145                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1146
1147                 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1149
1150                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1151
1152                 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1154
1155                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1156
1157                 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1159
1160                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1161
1162                 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1164
1165                 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1167         }
1168
1169         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1170 }
1171
1172 /*
1173  * try a read and see if it returns correct data back. has dummy reads
1174  * inserted into the mix used to align dqs enable. has more thorough checks
1175  * than the regular read test.
1176  */
1177 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1178         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1179         uint32_t all_groups, uint32_t all_ranks)
1180 {
1181         uint32_t r, vg;
1182         uint32_t correct_mask_vg;
1183         uint32_t tmp_bit_chk;
1184         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1185                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1186         uint32_t addr;
1187         uint32_t base_rw_mgr;
1188
1189         *bit_chk = param->read_correct_mask;
1190         correct_mask_vg = param->read_correct_mask_vg;
1191
1192         uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1193                 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1194
1195         for (r = rank_bgn; r < rank_end; r++) {
1196                 if (param->skip_ranks[r])
1197                         /* request to skip the rank */
1198                         continue;
1199
1200                 /* set rank */
1201                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1202
1203                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1204
1205                 writel(RW_MGR_READ_B2B_WAIT1,
1206                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1207
1208                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1209                 writel(RW_MGR_READ_B2B_WAIT2,
1210                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1211
1212                 if (quick_read_mode)
1213                         writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1214                         /* need at least two (1+1) reads to capture failures */
1215                 else if (all_groups)
1216                         writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1217                 else
1218                         writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1219
1220                 writel(RW_MGR_READ_B2B,
1221                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1222                 if (all_groups)
1223                         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1224                                RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1225                                &sdr_rw_load_mgr_regs->load_cntr3);
1226                 else
1227                         writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1228
1229                 writel(RW_MGR_READ_B2B,
1230                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1231
1232                 tmp_bit_chk = 0;
1233                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1234                         /* reset the fifos to get pointers to known state */
1235                         writel(0, &phy_mgr_cmd->fifo_reset);
1236                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1237                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1238
1239                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1240                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1241
1242                         if (all_groups)
1243                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1244                         else
1245                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1246
1247                         writel(RW_MGR_READ_B2B, addr +
1248                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1249                                vg) << 2));
1250
1251                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1252                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1253
1254                         if (vg == 0)
1255                                 break;
1256                 }
1257                 *bit_chk &= tmp_bit_chk;
1258         }
1259
1260         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1261         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1262
1263         if (all_correct) {
1264                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1265                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1266                            (%u == %u) => %lu", __func__, __LINE__, group,
1267                            all_groups, *bit_chk, param->read_correct_mask,
1268                            (long unsigned int)(*bit_chk ==
1269                            param->read_correct_mask));
1270                 return *bit_chk == param->read_correct_mask;
1271         } else  {
1272                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1273                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1274                            (%u != %lu) => %lu\n", __func__, __LINE__,
1275                            group, all_groups, *bit_chk, (long unsigned int)0,
1276                            (long unsigned int)(*bit_chk != 0x00));
1277                 return *bit_chk != 0x00;
1278         }
1279 }
1280
1281 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1282         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1283         uint32_t all_groups)
1284 {
1285         return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1286                                               bit_chk, all_groups, 1);
1287 }
1288
1289 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1290 {
1291         writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1292         (*v)++;
1293 }
1294
1295 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1296 {
1297         uint32_t i;
1298
1299         for (i = 0; i < VFIFO_SIZE-1; i++)
1300                 rw_mgr_incr_vfifo(grp, v);
1301 }
1302
1303 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1304 {
1305         uint32_t  v;
1306         uint32_t fail_cnt = 0;
1307         uint32_t test_status;
1308
1309         for (v = 0; v < VFIFO_SIZE; ) {
1310                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1311                            __func__, __LINE__, v);
1312                 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1313                         (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1314                 if (!test_status) {
1315                         fail_cnt++;
1316
1317                         if (fail_cnt == 2)
1318                                 break;
1319                 }
1320
1321                 /* fiddle with FIFO */
1322                 rw_mgr_incr_vfifo(grp, &v);
1323         }
1324
1325         if (v >= VFIFO_SIZE) {
1326                 /* no failing read found!! Something must have gone wrong */
1327                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1328                            __func__, __LINE__);
1329                 return 0;
1330         } else {
1331                 return v;
1332         }
1333 }
1334
1335 static int sdr_working_phase(uint32_t grp,
1336                               uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1337                               uint32_t *v, uint32_t *d, uint32_t *p,
1338                               uint32_t *i, uint32_t *max_working_cnt)
1339 {
1340         uint32_t found_begin = 0;
1341         uint32_t tmp_delay = 0;
1342         uint32_t test_status;
1343         u32 bit_chk;
1344
1345         for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1346                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1347                 *work_bgn = tmp_delay;
1348                 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1349
1350                 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1351                         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1352                                 IO_DELAY_PER_OPA_TAP) {
1353                                 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1354
1355                                 test_status =
1356                                 rw_mgr_mem_calibrate_read_test_all_ranks
1357                                 (grp, 1, PASS_ONE_BIT, &bit_chk, 0);
1358
1359                                 if (test_status) {
1360                                         *max_working_cnt = 1;
1361                                         found_begin = 1;
1362                                         break;
1363                                 }
1364                         }
1365
1366                         if (found_begin)
1367                                 break;
1368
1369                         if (*p > IO_DQS_EN_PHASE_MAX)
1370                                 /* fiddle with FIFO */
1371                                 rw_mgr_incr_vfifo(grp, v);
1372                 }
1373
1374                 if (found_begin)
1375                         break;
1376         }
1377
1378         if (*i >= VFIFO_SIZE) {
1379                 /* cannot find working solution */
1380                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1381                            ptap/dtap\n", __func__, __LINE__);
1382                 return 0;
1383         } else {
1384                 return 1;
1385         }
1386 }
1387
1388 static void sdr_backup_phase(uint32_t grp,
1389                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1390                              uint32_t *p, uint32_t *max_working_cnt)
1391 {
1392         uint32_t found_begin = 0;
1393         uint32_t tmp_delay;
1394         u32 bit_chk;
1395
1396         /* Special case code for backing up a phase */
1397         if (*p == 0) {
1398                 *p = IO_DQS_EN_PHASE_MAX;
1399                 rw_mgr_decr_vfifo(grp, v);
1400         } else {
1401                 (*p)--;
1402         }
1403         tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1404         scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1405
1406         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1407                 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1408                 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1409
1410                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1411                                                              PASS_ONE_BIT,
1412                                                              &bit_chk, 0)) {
1413                         found_begin = 1;
1414                         *work_bgn = tmp_delay;
1415                         break;
1416                 }
1417         }
1418
1419         /* We have found a working dtap before the ptap found above */
1420         if (found_begin == 1)
1421                 (*max_working_cnt)++;
1422
1423         /*
1424          * Restore VFIFO to old state before we decremented it
1425          * (if needed).
1426          */
1427         (*p)++;
1428         if (*p > IO_DQS_EN_PHASE_MAX) {
1429                 *p = 0;
1430                 rw_mgr_incr_vfifo(grp, v);
1431         }
1432
1433         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1434 }
1435
1436 static int sdr_nonworking_phase(uint32_t grp,
1437                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1438                              uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1439                              uint32_t *work_end)
1440 {
1441         uint32_t found_end = 0;
1442         u32 bit_chk;
1443
1444         (*p)++;
1445         *work_end += IO_DELAY_PER_OPA_TAP;
1446         if (*p > IO_DQS_EN_PHASE_MAX) {
1447                 /* fiddle with FIFO */
1448                 *p = 0;
1449                 rw_mgr_incr_vfifo(grp, v);
1450         }
1451
1452         for (; *i < VFIFO_SIZE + 1; (*i)++) {
1453                 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1454                         += IO_DELAY_PER_OPA_TAP) {
1455                         scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1456
1457                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1458                                 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1459                                 found_end = 1;
1460                                 break;
1461                         } else {
1462                                 (*max_working_cnt)++;
1463                         }
1464                 }
1465
1466                 if (found_end)
1467                         break;
1468
1469                 if (*p > IO_DQS_EN_PHASE_MAX) {
1470                         /* fiddle with FIFO */
1471                         rw_mgr_incr_vfifo(grp, v);
1472                         *p = 0;
1473                 }
1474         }
1475
1476         if (*i >= VFIFO_SIZE + 1) {
1477                 /* cannot see edge of failing read */
1478                 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1479                            failed\n", __func__, __LINE__);
1480                 return 0;
1481         } else {
1482                 return 1;
1483         }
1484 }
1485
1486 /**
1487  * sdr_find_window_center() - Find center of the working DQS window.
1488  * @grp:        Read/Write group
1489  * @work_bgn:   First working settings
1490  * @work_end:   Last working settings
1491  * @val:        VFIFO value
1492  *
1493  * Find center of the working DQS enable window.
1494  */
1495 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1496                                   const u32 work_end, const u32 val)
1497 {
1498         u32 bit_chk, work_mid, v = val;
1499         int tmp_delay = 0;
1500         int i, p, d;
1501
1502         work_mid = (work_bgn + work_end) / 2;
1503
1504         debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1505                    work_bgn, work_end, work_mid);
1506         /* Get the middle delay to be less than a VFIFO delay */
1507         tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1508
1509         debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1510         work_mid %= tmp_delay;
1511         debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1512
1513         tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1514         if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1515                 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1516         p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1517
1518         debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1519
1520         d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1521         if (d > IO_DQS_EN_DELAY_MAX)
1522                 d = IO_DQS_EN_DELAY_MAX;
1523         tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1524
1525         debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1526
1527         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1528         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1529
1530         /*
1531          * push vfifo until we can successfully calibrate. We can do this
1532          * because the largest possible margin in 1 VFIFO cycle.
1533          */
1534         for (i = 0; i < VFIFO_SIZE; i++) {
1535                 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1536                            v);
1537                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1538                                                              PASS_ONE_BIT,
1539                                                              &bit_chk, 0)) {
1540                         debug_cond(DLEVEL == 2,
1541                                    "%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
1542                                    __func__, __LINE__, v, p, d);
1543                         return 0;
1544                 }
1545
1546                 /* Fiddle with FIFO. */
1547                 rw_mgr_incr_vfifo(grp, &v);
1548         }
1549
1550         debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1551                    __func__, __LINE__);
1552         return -EINVAL;
1553 }
1554
1555 /* find a good dqs enable to use */
1556 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1557 {
1558         uint32_t v, d, p, i;
1559         uint32_t max_working_cnt;
1560         uint32_t bit_chk;
1561         uint32_t dtaps_per_ptap;
1562         uint32_t work_bgn, work_end;
1563         uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1564
1565         debug("%s:%d %u\n", __func__, __LINE__, grp);
1566
1567         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1568
1569         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1570         scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1571
1572         /* ************************************************************** */
1573         /* * Step 0 : Determine number of delay taps for each phase tap * */
1574         dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1575
1576         /* ********************************************************* */
1577         /* * Step 1 : First push vfifo until we get a failing read * */
1578         v = find_vfifo_read(grp, &bit_chk);
1579
1580         max_working_cnt = 0;
1581
1582         /* ******************************************************** */
1583         /* * step 2: find first working phase, increment in ptaps * */
1584         work_bgn = 0;
1585         if (sdr_working_phase(grp, dtaps_per_ptap, &work_bgn, &v, &d,
1586                               &p, &i, &max_working_cnt) == 0)
1587                 return 0;
1588
1589         work_end = work_bgn;
1590
1591         /*
1592          * If d is 0 then the working window covers a phase tap and
1593          * we can follow the old procedure otherwise, we've found the beginning,
1594          * and we need to increment the dtaps until we find the end.
1595          */
1596         if (d == 0) {
1597                 /* ********************************************************* */
1598                 /* * step 3a: if we have room, back off by one and
1599                 increment in dtaps * */
1600
1601                 sdr_backup_phase(grp, &work_bgn, &v, &d, &p,
1602                                  &max_working_cnt);
1603
1604                 /* ********************************************************* */
1605                 /* * step 4a: go forward from working phase to non working
1606                 phase, increment in ptaps * */
1607                 if (sdr_nonworking_phase(grp, &work_bgn, &v, &d, &p,
1608                                          &i, &max_working_cnt, &work_end) == 0)
1609                         return 0;
1610
1611                 /* ********************************************************* */
1612                 /* * step 5a:  back off one from last, increment in dtaps  * */
1613
1614                 /* Special case code for backing up a phase */
1615                 if (p == 0) {
1616                         p = IO_DQS_EN_PHASE_MAX;
1617                         rw_mgr_decr_vfifo(grp, &v);
1618                 } else {
1619                         p = p - 1;
1620                 }
1621
1622                 work_end -= IO_DELAY_PER_OPA_TAP;
1623                 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1624
1625                 /* * The actual increment of dtaps is done outside of
1626                 the if/else loop to share code */
1627                 d = 0;
1628
1629                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1630                            vfifo=%u ptap=%u\n", __func__, __LINE__,
1631                            v, p);
1632         } else {
1633                 /* ******************************************************* */
1634                 /* * step 3-5b:  Find the right edge of the window using
1635                 delay taps   * */
1636                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1637                            ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1638                            v, p, d, work_bgn);
1639
1640                 work_end = work_bgn;
1641
1642                 /* * The actual increment of dtaps is done outside of the
1643                 if/else loop to share code */
1644
1645                 /* Only here to counterbalance a subtract later on which is
1646                 not needed if this branch of the algorithm is taken */
1647                 max_working_cnt++;
1648         }
1649
1650         /* The dtap increment to find the failing edge is done here */
1651         for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1652                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1653                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1654                                    end-2: dtap=%u\n", __func__, __LINE__, d);
1655                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1656
1657                         if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1658                                                                       PASS_ONE_BIT,
1659                                                                       &bit_chk, 0)) {
1660                                 break;
1661                         }
1662         }
1663
1664         /* Go back to working dtap */
1665         if (d != 0)
1666                 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1667
1668         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1669                    ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1670                    v, p, d-1, work_end);
1671
1672         if (work_end < work_bgn) {
1673                 /* nil range */
1674                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1675                            failed\n", __func__, __LINE__);
1676                 return 0;
1677         }
1678
1679         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1680                    __func__, __LINE__, work_bgn, work_end);
1681
1682         /* *************************************************************** */
1683         /*
1684          * * We need to calculate the number of dtaps that equal a ptap
1685          * * To do that we'll back up a ptap and re-find the edge of the
1686          * * window using dtaps
1687          */
1688
1689         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1690                    for tracking\n", __func__, __LINE__);
1691
1692         /* Special case code for backing up a phase */
1693         if (p == 0) {
1694                 p = IO_DQS_EN_PHASE_MAX;
1695                 rw_mgr_decr_vfifo(grp, &v);
1696                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1697                            cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1698                            v, p);
1699         } else {
1700                 p = p - 1;
1701                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1702                            phase only: v=%u p=%u", __func__, __LINE__,
1703                            v, p);
1704         }
1705
1706         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1707
1708         /*
1709          * Increase dtap until we first see a passing read (in case the
1710          * window is smaller than a ptap),
1711          * and then a failing read to mark the edge of the window again
1712          */
1713
1714         /* Find a passing read */
1715         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1716                    __func__, __LINE__);
1717         found_passing_read = 0;
1718         found_failing_read = 0;
1719         initial_failing_dtap = d;
1720         for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1721                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1722                            read d=%u\n", __func__, __LINE__, d);
1723                 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1724
1725                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1726                                                              PASS_ONE_BIT,
1727                                                              &bit_chk, 0)) {
1728                         found_passing_read = 1;
1729                         break;
1730                 }
1731         }
1732
1733         if (found_passing_read) {
1734                 /* Find a failing read */
1735                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1736                            read\n", __func__, __LINE__);
1737                 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1738                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1739                                    testing read d=%u\n", __func__, __LINE__, d);
1740                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1741
1742                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1743                                 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1744                                 found_failing_read = 1;
1745                                 break;
1746                         }
1747                 }
1748         } else {
1749                 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1750                            calculate dtaps", __func__, __LINE__);
1751                 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1752         }
1753
1754         /*
1755          * The dynamically calculated dtaps_per_ptap is only valid if we
1756          * found a passing/failing read. If we didn't, it means d hit the max
1757          * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1758          * statically calculated value.
1759          */
1760         if (found_passing_read && found_failing_read)
1761                 dtaps_per_ptap = d - initial_failing_dtap;
1762
1763         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1764         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1765                    - %u = %u",  __func__, __LINE__, d,
1766                    initial_failing_dtap, dtaps_per_ptap);
1767
1768         /* ******************************************** */
1769         /* * step 6:  Find the centre of the window   * */
1770         if (sdr_find_window_centre(grp, work_bgn, work_end, v))
1771                 return 0; /* FIXME: Old code, return 0 means failure :-( */
1772
1773         return 1;
1774 }
1775
1776 /* per-bit deskew DQ and center */
1777 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1778         uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1779         uint32_t use_read_test, uint32_t update_fom)
1780 {
1781         uint32_t i, p, d, min_index;
1782         /*
1783          * Store these as signed since there are comparisons with
1784          * signed numbers.
1785          */
1786         uint32_t bit_chk;
1787         uint32_t sticky_bit_chk;
1788         int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1789         int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1790         int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1791         int32_t mid;
1792         int32_t orig_mid_min, mid_min;
1793         int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1794                 final_dqs_en;
1795         int32_t dq_margin, dqs_margin;
1796         uint32_t stop;
1797         uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1798         uint32_t addr;
1799
1800         debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1801
1802         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1803         start_dqs = readl(addr + (read_group << 2));
1804         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1805                 start_dqs_en = readl(addr + ((read_group << 2)
1806                                      - IO_DQS_EN_DELAY_OFFSET));
1807
1808         /* set the left and right edge of each bit to an illegal value */
1809         /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1810         sticky_bit_chk = 0;
1811         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1812                 left_edge[i]  = IO_IO_IN_DELAY_MAX + 1;
1813                 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1814         }
1815
1816         /* Search for the left edge of the window for each bit */
1817         for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1818                 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1819
1820                 writel(0, &sdr_scc_mgr->update);
1821
1822                 /*
1823                  * Stop searching when the read test doesn't pass AND when
1824                  * we've seen a passing read on every bit.
1825                  */
1826                 if (use_read_test) {
1827                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1828                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1829                                 &bit_chk, 0, 0);
1830                 } else {
1831                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1832                                                         0, PASS_ONE_BIT,
1833                                                         &bit_chk, 0);
1834                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1835                                 (read_group - (write_group *
1836                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1837                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1838                         stop = (bit_chk == 0);
1839                 }
1840                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1841                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1842                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1843                            && %u", __func__, __LINE__, d,
1844                            sticky_bit_chk,
1845                         param->read_correct_mask, stop);
1846
1847                 if (stop == 1) {
1848                         break;
1849                 } else {
1850                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1851                                 if (bit_chk & 1) {
1852                                         /* Remember a passing test as the
1853                                         left_edge */
1854                                         left_edge[i] = d;
1855                                 } else {
1856                                         /* If a left edge has not been seen yet,
1857                                         then a future passing test will mark
1858                                         this edge as the right edge */
1859                                         if (left_edge[i] ==
1860                                                 IO_IO_IN_DELAY_MAX + 1) {
1861                                                 right_edge[i] = -(d + 1);
1862                                         }
1863                                 }
1864                                 bit_chk = bit_chk >> 1;
1865                         }
1866                 }
1867         }
1868
1869         /* Reset DQ delay chains to 0 */
1870         scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1871         sticky_bit_chk = 0;
1872         for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1873                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1874                            %d right_edge[%u]: %d\n", __func__, __LINE__,
1875                            i, left_edge[i], i, right_edge[i]);
1876
1877                 /*
1878                  * Check for cases where we haven't found the left edge,
1879                  * which makes our assignment of the the right edge invalid.
1880                  * Reset it to the illegal value.
1881                  */
1882                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1883                         right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1884                         right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1885                         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1886                                    right_edge[%u]: %d\n", __func__, __LINE__,
1887                                    i, right_edge[i]);
1888                 }
1889
1890                 /*
1891                  * Reset sticky bit (except for bits where we have seen
1892                  * both the left and right edge).
1893                  */
1894                 sticky_bit_chk = sticky_bit_chk << 1;
1895                 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1896                     (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1897                         sticky_bit_chk = sticky_bit_chk | 1;
1898                 }
1899
1900                 if (i == 0)
1901                         break;
1902         }
1903
1904         /* Search for the right edge of the window for each bit */
1905         for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1906                 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1907                 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1908                         uint32_t delay = d + start_dqs_en;
1909                         if (delay > IO_DQS_EN_DELAY_MAX)
1910                                 delay = IO_DQS_EN_DELAY_MAX;
1911                         scc_mgr_set_dqs_en_delay(read_group, delay);
1912                 }
1913                 scc_mgr_load_dqs(read_group);
1914
1915                 writel(0, &sdr_scc_mgr->update);
1916
1917                 /*
1918                  * Stop searching when the read test doesn't pass AND when
1919                  * we've seen a passing read on every bit.
1920                  */
1921                 if (use_read_test) {
1922                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1923                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1924                                 &bit_chk, 0, 0);
1925                 } else {
1926                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1927                                                         0, PASS_ONE_BIT,
1928                                                         &bit_chk, 0);
1929                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1930                                 (read_group - (write_group *
1931                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1932                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1933                         stop = (bit_chk == 0);
1934                 }
1935                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1936                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1937
1938                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1939                            %u && %u", __func__, __LINE__, d,
1940                            sticky_bit_chk, param->read_correct_mask, stop);
1941
1942                 if (stop == 1) {
1943                         break;
1944                 } else {
1945                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1946                                 if (bit_chk & 1) {
1947                                         /* Remember a passing test as
1948                                         the right_edge */
1949                                         right_edge[i] = d;
1950                                 } else {
1951                                         if (d != 0) {
1952                                                 /* If a right edge has not been
1953                                                 seen yet, then a future passing
1954                                                 test will mark this edge as the
1955                                                 left edge */
1956                                                 if (right_edge[i] ==
1957                                                 IO_IO_IN_DELAY_MAX + 1) {
1958                                                         left_edge[i] = -(d + 1);
1959                                                 }
1960                                         } else {
1961                                                 /* d = 0 failed, but it passed
1962                                                 when testing the left edge,
1963                                                 so it must be marginal,
1964                                                 set it to -1 */
1965                                                 if (right_edge[i] ==
1966                                                         IO_IO_IN_DELAY_MAX + 1 &&
1967                                                         left_edge[i] !=
1968                                                         IO_IO_IN_DELAY_MAX
1969                                                         + 1) {
1970                                                         right_edge[i] = -1;
1971                                                 }
1972                                                 /* If a right edge has not been
1973                                                 seen yet, then a future passing
1974                                                 test will mark this edge as the
1975                                                 left edge */
1976                                                 else if (right_edge[i] ==
1977                                                         IO_IO_IN_DELAY_MAX +
1978                                                         1) {
1979                                                         left_edge[i] = -(d + 1);
1980                                                 }
1981                                         }
1982                                 }
1983
1984                                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
1985                                            d=%u]: ", __func__, __LINE__, d);
1986                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
1987                                            (int)(bit_chk & 1), i, left_edge[i]);
1988                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
1989                                            right_edge[i]);
1990                                 bit_chk = bit_chk >> 1;
1991                         }
1992                 }
1993         }
1994
1995         /* Check that all bits have a window */
1996         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1997                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1998                            %d right_edge[%u]: %d", __func__, __LINE__,
1999                            i, left_edge[i], i, right_edge[i]);
2000                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2001                         == IO_IO_IN_DELAY_MAX + 1)) {
2002                         /*
2003                          * Restore delay chain settings before letting the loop
2004                          * in rw_mgr_mem_calibrate_vfifo to retry different
2005                          * dqs/ck relationships.
2006                          */
2007                         scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2008                         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2009                                 scc_mgr_set_dqs_en_delay(read_group,
2010                                                          start_dqs_en);
2011                         }
2012                         scc_mgr_load_dqs(read_group);
2013                         writel(0, &sdr_scc_mgr->update);
2014
2015                         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2016                                    find edge [%u]: %d %d", __func__, __LINE__,
2017                                    i, left_edge[i], right_edge[i]);
2018                         if (use_read_test) {
2019                                 set_failing_group_stage(read_group *
2020                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2021                                         CAL_STAGE_VFIFO,
2022                                         CAL_SUBSTAGE_VFIFO_CENTER);
2023                         } else {
2024                                 set_failing_group_stage(read_group *
2025                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2026                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2027                                         CAL_SUBSTAGE_VFIFO_CENTER);
2028                         }
2029                         return 0;
2030                 }
2031         }
2032
2033         /* Find middle of window for each DQ bit */
2034         mid_min = left_edge[0] - right_edge[0];
2035         min_index = 0;
2036         for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2037                 mid = left_edge[i] - right_edge[i];
2038                 if (mid < mid_min) {
2039                         mid_min = mid;
2040                         min_index = i;
2041                 }
2042         }
2043
2044         /*
2045          * -mid_min/2 represents the amount that we need to move DQS.
2046          * If mid_min is odd and positive we'll need to add one to
2047          * make sure the rounding in further calculations is correct
2048          * (always bias to the right), so just add 1 for all positive values.
2049          */
2050         if (mid_min > 0)
2051                 mid_min++;
2052
2053         mid_min = mid_min / 2;
2054
2055         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2056                    __func__, __LINE__, mid_min, min_index);
2057
2058         /* Determine the amount we can change DQS (which is -mid_min) */
2059         orig_mid_min = mid_min;
2060         new_dqs = start_dqs - mid_min;
2061         if (new_dqs > IO_DQS_IN_DELAY_MAX)
2062                 new_dqs = IO_DQS_IN_DELAY_MAX;
2063         else if (new_dqs < 0)
2064                 new_dqs = 0;
2065
2066         mid_min = start_dqs - new_dqs;
2067         debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2068                    mid_min, new_dqs);
2069
2070         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2071                 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2072                         mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2073                 else if (start_dqs_en - mid_min < 0)
2074                         mid_min += start_dqs_en - mid_min;
2075         }
2076         new_dqs = start_dqs - mid_min;
2077
2078         debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2079                    new_dqs=%d mid_min=%d\n", start_dqs,
2080                    IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2081                    new_dqs, mid_min);
2082
2083         /* Initialize data for export structures */
2084         dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2085         dq_margin  = IO_IO_IN_DELAY_MAX + 1;
2086
2087         /* add delay to bring centre of all DQ windows to the same "level" */
2088         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2089                 /* Use values before divide by 2 to reduce round off error */
2090                 shift_dq = (left_edge[i] - right_edge[i] -
2091                         (left_edge[min_index] - right_edge[min_index]))/2  +
2092                         (orig_mid_min - mid_min);
2093
2094                 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2095                            shift_dq[%u]=%d\n", i, shift_dq);
2096
2097                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2098                 temp_dq_in_delay1 = readl(addr + (p << 2));
2099                 temp_dq_in_delay2 = readl(addr + (i << 2));
2100
2101                 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2102                         (int32_t)IO_IO_IN_DELAY_MAX) {
2103                         shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2104                 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2105                         shift_dq = -(int32_t)temp_dq_in_delay1;
2106                 }
2107                 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2108                            shift_dq[%u]=%d\n", i, shift_dq);
2109                 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2110                 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2111                 scc_mgr_load_dq(p);
2112
2113                 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2114                            left_edge[i] - shift_dq + (-mid_min),
2115                            right_edge[i] + shift_dq - (-mid_min));
2116                 /* To determine values for export structures */
2117                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2118                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2119
2120                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2121                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2122         }
2123
2124         final_dqs = new_dqs;
2125         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2126                 final_dqs_en = start_dqs_en - mid_min;
2127
2128         /* Move DQS-en */
2129         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2130                 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2131                 scc_mgr_load_dqs(read_group);
2132         }
2133
2134         /* Move DQS */
2135         scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2136         scc_mgr_load_dqs(read_group);
2137         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2138                    dqs_margin=%d", __func__, __LINE__,
2139                    dq_margin, dqs_margin);
2140
2141         /*
2142          * Do not remove this line as it makes sure all of our decisions
2143          * have been applied. Apply the update bit.
2144          */
2145         writel(0, &sdr_scc_mgr->update);
2146
2147         return (dq_margin >= 0) && (dqs_margin >= 0);
2148 }
2149
2150 /**
2151  * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2152  * @rw_group:   Read/Write Group
2153  * @phase:      DQ/DQS phase
2154  *
2155  * Because initially no communication ca be reliably performed with the memory
2156  * device, the sequencer uses a guaranteed write mechanism to write data into
2157  * the memory device.
2158  */
2159 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2160                                                  const u32 phase)
2161 {
2162         int ret;
2163
2164         /* Set a particular DQ/DQS phase. */
2165         scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2166
2167         debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2168                    __func__, __LINE__, rw_group, phase);
2169
2170         /*
2171          * Altera EMI_RM 2015.05.04 :: Figure 1-25
2172          * Load up the patterns used by read calibration using the
2173          * current DQDQS phase.
2174          */
2175         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2176
2177         if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2178                 return 0;
2179
2180         /*
2181          * Altera EMI_RM 2015.05.04 :: Figure 1-26
2182          * Back-to-Back reads of the patterns used for calibration.
2183          */
2184         ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2185         if (ret)
2186                 debug_cond(DLEVEL == 1,
2187                            "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2188                            __func__, __LINE__, rw_group, phase);
2189         return ret;
2190 }
2191
2192 /**
2193  * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2194  * @rw_group:   Read/Write Group
2195  * @test_bgn:   Rank at which the test begins
2196  *
2197  * DQS enable calibration ensures reliable capture of the DQ signal without
2198  * glitches on the DQS line.
2199  */
2200 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2201                                                        const u32 test_bgn)
2202 {
2203         /*
2204          * Altera EMI_RM 2015.05.04 :: Figure 1-27
2205          * DQS and DQS Eanble Signal Relationships.
2206          */
2207
2208         /* We start at zero, so have one less dq to devide among */
2209         const u32 delay_step = IO_IO_IN_DELAY_MAX /
2210                                (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2211         int found;
2212         u32 i, p, d, r;
2213
2214         debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2215
2216         /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2217         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2218              r += NUM_RANKS_PER_SHADOW_REG) {
2219                 for (i = 0, p = test_bgn, d = 0;
2220                      i < RW_MGR_MEM_DQ_PER_READ_DQS;
2221                      i++, p++, d += delay_step) {
2222                         debug_cond(DLEVEL == 1,
2223                                    "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2224                                    __func__, __LINE__, rw_group, r, i, p, d);
2225
2226                         scc_mgr_set_dq_in_delay(p, d);
2227                         scc_mgr_load_dq(p);
2228                 }
2229
2230                 writel(0, &sdr_scc_mgr->update);
2231         }
2232
2233         /*
2234          * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2235          * dq_in_delay values
2236          */
2237         found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2238
2239         debug_cond(DLEVEL == 1,
2240                    "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2241                    __func__, __LINE__, rw_group, found);
2242
2243         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2244              r += NUM_RANKS_PER_SHADOW_REG) {
2245                 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2246                 writel(0, &sdr_scc_mgr->update);
2247         }
2248
2249         if (!found)
2250                 return -EINVAL;
2251
2252         return 0;
2253
2254 }
2255
2256 /**
2257  * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2258  * @rw_group:           Read/Write Group
2259  * @test_bgn:           Rank at which the test begins
2260  * @use_read_test:      Perform a read test
2261  * @update_fom:         Update FOM
2262  *
2263  * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2264  * within a group.
2265  */
2266 static int
2267 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2268                                       const int use_read_test,
2269                                       const int update_fom)
2270
2271 {
2272         int ret, grp_calibrated;
2273         u32 rank_bgn, sr;
2274
2275         /*
2276          * Altera EMI_RM 2015.05.04 :: Figure 1-28
2277          * Read per-bit deskew can be done on a per shadow register basis.
2278          */
2279         grp_calibrated = 1;
2280         for (rank_bgn = 0, sr = 0;
2281              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2282              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2283                 /* Check if this set of ranks should be skipped entirely. */
2284                 if (param->skip_shadow_regs[sr])
2285                         continue;
2286
2287                 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2288                                                         rw_group, test_bgn,
2289                                                         use_read_test,
2290                                                         update_fom);
2291                 if (ret)
2292                         continue;
2293
2294                 grp_calibrated = 0;
2295         }
2296
2297         if (!grp_calibrated)
2298                 return -EIO;
2299
2300         return 0;
2301 }
2302
2303 /**
2304  * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2305  * @rw_group:           Read/Write Group
2306  * @test_bgn:           Rank at which the test begins
2307  *
2308  * Stage 1: Calibrate the read valid prediction FIFO.
2309  *
2310  * This function implements UniPHY calibration Stage 1, as explained in
2311  * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2312  *
2313  * - read valid prediction will consist of finding:
2314  *   - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2315  *   - DQS input phase  and DQS input delay (DQ/DQS Centering)
2316  *  - we also do a per-bit deskew on the DQ lines.
2317  */
2318 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2319 {
2320         uint32_t p, d;
2321         uint32_t dtaps_per_ptap;
2322         uint32_t failed_substage;
2323
2324         int ret;
2325
2326         debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2327
2328         /* Update info for sims */
2329         reg_file_set_group(rw_group);
2330         reg_file_set_stage(CAL_STAGE_VFIFO);
2331         reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2332
2333         failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2334
2335         /* USER Determine number of delay taps for each phase tap. */
2336         dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2337                                       IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2338
2339         for (d = 0; d <= dtaps_per_ptap; d += 2) {
2340                 /*
2341                  * In RLDRAMX we may be messing the delay of pins in
2342                  * the same write rw_group but outside of the current read
2343                  * the rw_group, but that's ok because we haven't calibrated
2344                  * output side yet.
2345                  */
2346                 if (d > 0) {
2347                         scc_mgr_apply_group_all_out_delay_add_all_ranks(
2348                                                                 rw_group, d);
2349                 }
2350
2351                 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2352                         /* 1) Guaranteed Write */
2353                         ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2354                         if (ret)
2355                                 break;
2356
2357                         /* 2) DQS Enable Calibration */
2358                         ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2359                                                                           test_bgn);
2360                         if (ret) {
2361                                 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2362                                 continue;
2363                         }
2364
2365                         /* 3) Centering DQ/DQS */
2366                         /*
2367                          * If doing read after write calibration, do not update
2368                          * FOM now. Do it then.
2369                          */
2370                         ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2371                                                                 test_bgn, 1, 0);
2372                         if (ret) {
2373                                 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2374                                 continue;
2375                         }
2376
2377                         /* All done. */
2378                         goto cal_done_ok;
2379                 }
2380         }
2381
2382         /* Calibration Stage 1 failed. */
2383         set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2384         return 0;
2385
2386         /* Calibration Stage 1 completed OK. */
2387 cal_done_ok:
2388         /*
2389          * Reset the delay chains back to zero if they have moved > 1
2390          * (check for > 1 because loop will increase d even when pass in
2391          * first case).
2392          */
2393         if (d > 2)
2394                 scc_mgr_zero_group(rw_group, 1);
2395
2396         return 1;
2397 }
2398
2399 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2400 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2401                                                uint32_t test_bgn)
2402 {
2403         uint32_t rank_bgn, sr;
2404         uint32_t grp_calibrated;
2405         uint32_t write_group;
2406
2407         debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2408
2409         /* update info for sims */
2410
2411         reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2412         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2413
2414         write_group = read_group;
2415
2416         /* update info for sims */
2417         reg_file_set_group(read_group);
2418
2419         grp_calibrated = 1;
2420         /* Read per-bit deskew can be done on a per shadow register basis */
2421         for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2422                 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2423                 /* Determine if this set of ranks should be skipped entirely */
2424                 if (!param->skip_shadow_regs[sr]) {
2425                 /* This is the last calibration round, update FOM here */
2426                         if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2427                                                                 write_group,
2428                                                                 read_group,
2429                                                                 test_bgn, 0,
2430                                                                 1)) {
2431                                 grp_calibrated = 0;
2432                         }
2433                 }
2434         }
2435
2436
2437         if (grp_calibrated == 0) {
2438                 set_failing_group_stage(write_group,
2439                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2440                                         CAL_SUBSTAGE_VFIFO_CENTER);
2441                 return 0;
2442         }
2443
2444         return 1;
2445 }
2446
2447 /* Calibrate LFIFO to find smallest read latency */
2448 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2449 {
2450         uint32_t found_one;
2451         uint32_t bit_chk;
2452
2453         debug("%s:%d\n", __func__, __LINE__);
2454
2455         /* update info for sims */
2456         reg_file_set_stage(CAL_STAGE_LFIFO);
2457         reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2458
2459         /* Load up the patterns used by read calibration for all ranks */
2460         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2461         found_one = 0;
2462
2463         do {
2464                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2465                 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2466                            __func__, __LINE__, gbl->curr_read_lat);
2467
2468                 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2469                                                               NUM_READ_TESTS,
2470                                                               PASS_ALL_BITS,
2471                                                               &bit_chk, 1)) {
2472                         break;
2473                 }
2474
2475                 found_one = 1;
2476                 /* reduce read latency and see if things are working */
2477                 /* correctly */
2478                 gbl->curr_read_lat--;
2479         } while (gbl->curr_read_lat > 0);
2480
2481         /* reset the fifos to get pointers to known state */
2482
2483         writel(0, &phy_mgr_cmd->fifo_reset);
2484
2485         if (found_one) {
2486                 /* add a fudge factor to the read latency that was determined */
2487                 gbl->curr_read_lat += 2;
2488                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2489                 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2490                            read_lat=%u\n", __func__, __LINE__,
2491                            gbl->curr_read_lat);
2492                 return 1;
2493         } else {
2494                 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2495                                         CAL_SUBSTAGE_READ_LATENCY);
2496
2497                 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2498                            read_lat=%u\n", __func__, __LINE__,
2499                            gbl->curr_read_lat);
2500                 return 0;
2501         }
2502 }
2503
2504 /*
2505  * issue write test command.
2506  * two variants are provided. one that just tests a write pattern and
2507  * another that tests datamask functionality.
2508  */
2509 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2510                                                   uint32_t test_dm)
2511 {
2512         uint32_t mcc_instruction;
2513         uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2514                 ENABLE_SUPER_QUICK_CALIBRATION);
2515         uint32_t rw_wl_nop_cycles;
2516         uint32_t addr;
2517
2518         /*
2519          * Set counter and jump addresses for the right
2520          * number of NOP cycles.
2521          * The number of supported NOP cycles can range from -1 to infinity
2522          * Three different cases are handled:
2523          *
2524          * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2525          *    mechanism will be used to insert the right number of NOPs
2526          *
2527          * 2. For a number of NOP cycles equals to 0, the micro-instruction
2528          *    issuing the write command will jump straight to the
2529          *    micro-instruction that turns on DQS (for DDRx), or outputs write
2530          *    data (for RLD), skipping
2531          *    the NOP micro-instruction all together
2532          *
2533          * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2534          *    turned on in the same micro-instruction that issues the write
2535          *    command. Then we need
2536          *    to directly jump to the micro-instruction that sends out the data
2537          *
2538          * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2539          *       (2 and 3). One jump-counter (0) is used to perform multiple
2540          *       write-read operations.
2541          *       one counter left to issue this command in "multiple-group" mode
2542          */
2543
2544         rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2545
2546         if (rw_wl_nop_cycles == -1) {
2547                 /*
2548                  * CNTR 2 - We want to execute the special write operation that
2549                  * turns on DQS right away and then skip directly to the
2550                  * instruction that sends out the data. We set the counter to a
2551                  * large number so that the jump is always taken.
2552                  */
2553                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2554
2555                 /* CNTR 3 - Not used */
2556                 if (test_dm) {
2557                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2558                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2559                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2560                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2561                                &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2562                 } else {
2563                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2564                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2565                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2566                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2567                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2568                 }
2569         } else if (rw_wl_nop_cycles == 0) {
2570                 /*
2571                  * CNTR 2 - We want to skip the NOP operation and go straight
2572                  * to the DQS enable instruction. We set the counter to a large
2573                  * number so that the jump is always taken.
2574                  */
2575                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2576
2577                 /* CNTR 3 - Not used */
2578                 if (test_dm) {
2579                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2580                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2581                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2582                 } else {
2583                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2584                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2585                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2586                 }
2587         } else {
2588                 /*
2589                  * CNTR 2 - In this case we want to execute the next instruction
2590                  * and NOT take the jump. So we set the counter to 0. The jump
2591                  * address doesn't count.
2592                  */
2593                 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2594                 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2595
2596                 /*
2597                  * CNTR 3 - Set the nop counter to the number of cycles we
2598                  * need to loop for, minus 1.
2599                  */
2600                 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2601                 if (test_dm) {
2602                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2603                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2604                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2605                 } else {
2606                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2607                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2608                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2609                 }
2610         }
2611
2612         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2613                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
2614
2615         if (quick_write_mode)
2616                 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2617         else
2618                 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2619
2620         writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2621
2622         /*
2623          * CNTR 1 - This is used to ensure enough time elapses
2624          * for read data to come back.
2625          */
2626         writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2627
2628         if (test_dm) {
2629                 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2630                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2631         } else {
2632                 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2633                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2634         }
2635
2636         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2637         writel(mcc_instruction, addr + (group << 2));
2638 }
2639
2640 /* Test writes, can check for a single bit pass or multiple bit pass */
2641 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2642         uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2643         uint32_t *bit_chk, uint32_t all_ranks)
2644 {
2645         uint32_t r;
2646         uint32_t correct_mask_vg;
2647         uint32_t tmp_bit_chk;
2648         uint32_t vg;
2649         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2650                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2651         uint32_t addr_rw_mgr;
2652         uint32_t base_rw_mgr;
2653
2654         *bit_chk = param->write_correct_mask;
2655         correct_mask_vg = param->write_correct_mask_vg;
2656
2657         for (r = rank_bgn; r < rank_end; r++) {
2658                 if (param->skip_ranks[r]) {
2659                         /* request to skip the rank */
2660                         continue;
2661                 }
2662
2663                 /* set rank */
2664                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2665
2666                 tmp_bit_chk = 0;
2667                 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2668                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2669                         /* reset the fifos to get pointers to known state */
2670                         writel(0, &phy_mgr_cmd->fifo_reset);
2671
2672                         tmp_bit_chk = tmp_bit_chk <<
2673                                 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2674                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2675                         rw_mgr_mem_calibrate_write_test_issue(write_group *
2676                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2677                                 use_dm);
2678
2679                         base_rw_mgr = readl(addr_rw_mgr);
2680                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2681                         if (vg == 0)
2682                                 break;
2683                 }
2684                 *bit_chk &= tmp_bit_chk;
2685         }
2686
2687         if (all_correct) {
2688                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2689                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2690                            %u => %lu", write_group, use_dm,
2691                            *bit_chk, param->write_correct_mask,
2692                            (long unsigned int)(*bit_chk ==
2693                            param->write_correct_mask));
2694                 return *bit_chk == param->write_correct_mask;
2695         } else {
2696                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2697                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2698                        write_group, use_dm, *bit_chk);
2699                 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2700                         (long unsigned int)(*bit_chk != 0));
2701                 return *bit_chk != 0x00;
2702         }
2703 }
2704
2705 /*
2706  * center all windows. do per-bit-deskew to possibly increase size of
2707  * certain windows.
2708  */
2709 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2710         uint32_t write_group, uint32_t test_bgn)
2711 {
2712         uint32_t i, p, min_index;
2713         int32_t d;
2714         /*
2715          * Store these as signed since there are comparisons with
2716          * signed numbers.
2717          */
2718         uint32_t bit_chk;
2719         uint32_t sticky_bit_chk;
2720         int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2721         int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2722         int32_t mid;
2723         int32_t mid_min, orig_mid_min;
2724         int32_t new_dqs, start_dqs, shift_dq;
2725         int32_t dq_margin, dqs_margin, dm_margin;
2726         uint32_t stop;
2727         uint32_t temp_dq_out1_delay;
2728         uint32_t addr;
2729
2730         debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2731
2732         dm_margin = 0;
2733
2734         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2735         start_dqs = readl(addr +
2736                           (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2737
2738         /* per-bit deskew */
2739
2740         /*
2741          * set the left and right edge of each bit to an illegal value
2742          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2743          */
2744         sticky_bit_chk = 0;
2745         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2746                 left_edge[i]  = IO_IO_OUT1_DELAY_MAX + 1;
2747                 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2748         }
2749
2750         /* Search for the left edge of the window for each bit */
2751         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2752                 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2753
2754                 writel(0, &sdr_scc_mgr->update);
2755
2756                 /*
2757                  * Stop searching when the read test doesn't pass AND when
2758                  * we've seen a passing read on every bit.
2759                  */
2760                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2761                         0, PASS_ONE_BIT, &bit_chk, 0);
2762                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2763                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2764                 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2765                            == %u && %u [bit_chk= %u ]\n",
2766                         d, sticky_bit_chk, param->write_correct_mask,
2767                         stop, bit_chk);
2768
2769                 if (stop == 1) {
2770                         break;
2771                 } else {
2772                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2773                                 if (bit_chk & 1) {
2774                                         /*
2775                                          * Remember a passing test as the
2776                                          * left_edge.
2777                                          */
2778                                         left_edge[i] = d;
2779                                 } else {
2780                                         /*
2781                                          * If a left edge has not been seen
2782                                          * yet, then a future passing test will
2783                                          * mark this edge as the right edge.
2784                                          */
2785                                         if (left_edge[i] ==
2786                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2787                                                 right_edge[i] = -(d + 1);
2788                                         }
2789                                 }
2790                                 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2791                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2792                                            (int)(bit_chk & 1), i, left_edge[i]);
2793                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2794                                        right_edge[i]);
2795                                 bit_chk = bit_chk >> 1;
2796                         }
2797                 }
2798         }
2799
2800         /* Reset DQ delay chains to 0 */
2801         scc_mgr_apply_group_dq_out1_delay(0);
2802         sticky_bit_chk = 0;
2803         for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2804                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2805                            %d right_edge[%u]: %d\n", __func__, __LINE__,
2806                            i, left_edge[i], i, right_edge[i]);
2807
2808                 /*
2809                  * Check for cases where we haven't found the left edge,
2810                  * which makes our assignment of the the right edge invalid.
2811                  * Reset it to the illegal value.
2812                  */
2813                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2814                     (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2815                         right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2816                         debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2817                                    right_edge[%u]: %d\n", __func__, __LINE__,
2818                                    i, right_edge[i]);
2819                 }
2820
2821                 /*
2822                  * Reset sticky bit (except for bits where we have
2823                  * seen the left edge).
2824                  */
2825                 sticky_bit_chk = sticky_bit_chk << 1;
2826                 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2827                         sticky_bit_chk = sticky_bit_chk | 1;
2828
2829                 if (i == 0)
2830                         break;
2831         }
2832
2833         /* Search for the right edge of the window for each bit */
2834         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2835                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2836                                                         d + start_dqs);
2837
2838                 writel(0, &sdr_scc_mgr->update);
2839
2840                 /*
2841                  * Stop searching when the read test doesn't pass AND when
2842                  * we've seen a passing read on every bit.
2843                  */
2844                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2845                         0, PASS_ONE_BIT, &bit_chk, 0);
2846
2847                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2848                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2849
2850                 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2851                            %u && %u\n", d, sticky_bit_chk,
2852                            param->write_correct_mask, stop);
2853
2854                 if (stop == 1) {
2855                         if (d == 0) {
2856                                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2857                                         i++) {
2858                                         /* d = 0 failed, but it passed when
2859                                         testing the left edge, so it must be
2860                                         marginal, set it to -1 */
2861                                         if (right_edge[i] ==
2862                                                 IO_IO_OUT1_DELAY_MAX + 1 &&
2863                                                 left_edge[i] !=
2864                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2865                                                 right_edge[i] = -1;
2866                                         }
2867                                 }
2868                         }
2869                         break;
2870                 } else {
2871                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2872                                 if (bit_chk & 1) {
2873                                         /*
2874                                          * Remember a passing test as
2875                                          * the right_edge.
2876                                          */
2877                                         right_edge[i] = d;
2878                                 } else {
2879                                         if (d != 0) {
2880                                                 /*
2881                                                  * If a right edge has not
2882                                                  * been seen yet, then a future
2883                                                  * passing test will mark this
2884                                                  * edge as the left edge.
2885                                                  */
2886                                                 if (right_edge[i] ==
2887                                                     IO_IO_OUT1_DELAY_MAX + 1)
2888                                                         left_edge[i] = -(d + 1);
2889                                         } else {
2890                                                 /*
2891                                                  * d = 0 failed, but it passed
2892                                                  * when testing the left edge,
2893                                                  * so it must be marginal, set
2894                                                  * it to -1.
2895                                                  */
2896                                                 if (right_edge[i] ==
2897                                                     IO_IO_OUT1_DELAY_MAX + 1 &&
2898                                                     left_edge[i] !=
2899                                                     IO_IO_OUT1_DELAY_MAX + 1)
2900                                                         right_edge[i] = -1;
2901                                                 /*
2902                                                  * If a right edge has not been
2903                                                  * seen yet, then a future
2904                                                  * passing test will mark this
2905                                                  * edge as the left edge.
2906                                                  */
2907                                                 else if (right_edge[i] ==
2908                                                         IO_IO_OUT1_DELAY_MAX +
2909                                                         1)
2910                                                         left_edge[i] = -(d + 1);
2911                                         }
2912                                 }
2913                                 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2914                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2915                                            (int)(bit_chk & 1), i, left_edge[i]);
2916                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2917                                            right_edge[i]);
2918                                 bit_chk = bit_chk >> 1;
2919                         }
2920                 }
2921         }
2922
2923         /* Check that all bits have a window */
2924         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2925                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2926                            %d right_edge[%u]: %d", __func__, __LINE__,
2927                            i, left_edge[i], i, right_edge[i]);
2928                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2929                     (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2930                         set_failing_group_stage(test_bgn + i,
2931                                                 CAL_STAGE_WRITES,
2932                                                 CAL_SUBSTAGE_WRITES_CENTER);
2933                         return 0;
2934                 }
2935         }
2936
2937         /* Find middle of window for each DQ bit */
2938         mid_min = left_edge[0] - right_edge[0];
2939         min_index = 0;
2940         for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2941                 mid = left_edge[i] - right_edge[i];
2942                 if (mid < mid_min) {
2943                         mid_min = mid;
2944                         min_index = i;
2945                 }
2946         }
2947
2948         /*
2949          * -mid_min/2 represents the amount that we need to move DQS.
2950          * If mid_min is odd and positive we'll need to add one to
2951          * make sure the rounding in further calculations is correct
2952          * (always bias to the right), so just add 1 for all positive values.
2953          */
2954         if (mid_min > 0)
2955                 mid_min++;
2956         mid_min = mid_min / 2;
2957         debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2958                    __LINE__, mid_min);
2959
2960         /* Determine the amount we can change DQS (which is -mid_min) */
2961         orig_mid_min = mid_min;
2962         new_dqs = start_dqs;
2963         mid_min = 0;
2964         debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2965                    mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2966         /* Initialize data for export structures */
2967         dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2968         dq_margin  = IO_IO_OUT1_DELAY_MAX + 1;
2969
2970         /* add delay to bring centre of all DQ windows to the same "level" */
2971         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2972                 /* Use values before divide by 2 to reduce round off error */
2973                 shift_dq = (left_edge[i] - right_edge[i] -
2974                         (left_edge[min_index] - right_edge[min_index]))/2  +
2975                 (orig_mid_min - mid_min);
2976
2977                 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2978                            [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2979
2980                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2981                 temp_dq_out1_delay = readl(addr + (i << 2));
2982                 if (shift_dq + (int32_t)temp_dq_out1_delay >
2983                         (int32_t)IO_IO_OUT1_DELAY_MAX) {
2984                         shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2985                 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2986                         shift_dq = -(int32_t)temp_dq_out1_delay;
2987                 }
2988                 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2989                            i, shift_dq);
2990                 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2991                 scc_mgr_load_dq(i);
2992
2993                 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2994                            left_edge[i] - shift_dq + (-mid_min),
2995                            right_edge[i] + shift_dq - (-mid_min));
2996                 /* To determine values for export structures */
2997                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2998                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2999
3000                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
3001                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
3002         }
3003
3004         /* Move DQS */
3005         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3006         writel(0, &sdr_scc_mgr->update);
3007
3008         /* Centre DM */
3009         debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3010
3011         /*
3012          * set the left and right edge of each bit to an illegal value,
3013          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3014          */
3015         left_edge[0]  = IO_IO_OUT1_DELAY_MAX + 1;
3016         right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3017         int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3018         int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3019         int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
3020         int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
3021         int32_t win_best = 0;
3022
3023         /* Search for the/part of the window with DM shift */
3024         for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3025                 scc_mgr_apply_group_dm_out1_delay(d);
3026                 writel(0, &sdr_scc_mgr->update);
3027
3028                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3029                                                     PASS_ALL_BITS, &bit_chk,
3030                                                     0)) {
3031                         /* USE Set current end of the window */
3032                         end_curr = -d;
3033                         /*
3034                          * If a starting edge of our window has not been seen
3035                          * this is our current start of the DM window.
3036                          */
3037                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3038                                 bgn_curr = -d;
3039
3040                         /*
3041                          * If current window is bigger than best seen.
3042                          * Set best seen to be current window.
3043                          */
3044                         if ((end_curr-bgn_curr+1) > win_best) {
3045                                 win_best = end_curr-bgn_curr+1;
3046                                 bgn_best = bgn_curr;
3047                                 end_best = end_curr;
3048                         }
3049                 } else {
3050                         /* We just saw a failing test. Reset temp edge */
3051                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3052                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3053                         }
3054                 }
3055
3056
3057         /* Reset DM delay chains to 0 */
3058         scc_mgr_apply_group_dm_out1_delay(0);
3059
3060         /*
3061          * Check to see if the current window nudges up aganist 0 delay.
3062          * If so we need to continue the search by shifting DQS otherwise DQS
3063          * search begins as a new search. */
3064         if (end_curr != 0) {
3065                 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3066                 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3067         }
3068
3069         /* Search for the/part of the window with DQS shifts */
3070         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3071                 /*
3072                  * Note: This only shifts DQS, so are we limiting ourselve to
3073                  * width of DQ unnecessarily.
3074                  */
3075                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3076                                                         d + new_dqs);
3077
3078                 writel(0, &sdr_scc_mgr->update);
3079                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3080                                                     PASS_ALL_BITS, &bit_chk,
3081                                                     0)) {
3082                         /* USE Set current end of the window */
3083                         end_curr = d;
3084                         /*
3085                          * If a beginning edge of our window has not been seen
3086                          * this is our current begin of the DM window.
3087                          */
3088                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3089                                 bgn_curr = d;
3090
3091                         /*
3092                          * If current window is bigger than best seen. Set best
3093                          * seen to be current window.
3094                          */
3095                         if ((end_curr-bgn_curr+1) > win_best) {
3096                                 win_best = end_curr-bgn_curr+1;
3097                                 bgn_best = bgn_curr;
3098                                 end_best = end_curr;
3099                         }
3100                 } else {
3101                         /* We just saw a failing test. Reset temp edge */
3102                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3103                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3104
3105                         /* Early exit optimization: if ther remaining delay
3106                         chain space is less than already seen largest window
3107                         we can exit */
3108                         if ((win_best-1) >
3109                                 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3110                                         break;
3111                                 }
3112                         }
3113                 }
3114
3115         /* assign left and right edge for cal and reporting; */
3116         left_edge[0] = -1*bgn_best;
3117         right_edge[0] = end_best;
3118
3119         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3120                    __LINE__, left_edge[0], right_edge[0]);
3121
3122         /* Move DQS (back to orig) */
3123         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3124
3125         /* Move DM */
3126
3127         /* Find middle of window for the DM bit */
3128         mid = (left_edge[0] - right_edge[0]) / 2;
3129
3130         /* only move right, since we are not moving DQS/DQ */
3131         if (mid < 0)
3132                 mid = 0;
3133
3134         /* dm_marign should fail if we never find a window */
3135         if (win_best == 0)
3136                 dm_margin = -1;
3137         else
3138                 dm_margin = left_edge[0] - mid;
3139
3140         scc_mgr_apply_group_dm_out1_delay(mid);
3141         writel(0, &sdr_scc_mgr->update);
3142
3143         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3144                    dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3145                    right_edge[0], mid, dm_margin);
3146         /* Export values */
3147         gbl->fom_out += dq_margin + dqs_margin;
3148
3149         debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3150                    dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3151                    dq_margin, dqs_margin, dm_margin);
3152
3153         /*
3154          * Do not remove this line as it makes sure all of our
3155          * decisions have been applied.
3156          */
3157         writel(0, &sdr_scc_mgr->update);
3158         return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3159 }
3160
3161 /* calibrate the write operations */
3162 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3163         uint32_t test_bgn)
3164 {
3165         /* update info for sims */
3166         debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3167
3168         reg_file_set_stage(CAL_STAGE_WRITES);
3169         reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3170
3171         reg_file_set_group(g);
3172
3173         if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3174                 set_failing_group_stage(g, CAL_STAGE_WRITES,
3175                                         CAL_SUBSTAGE_WRITES_CENTER);
3176                 return 0;
3177         }
3178
3179         return 1;
3180 }
3181
3182 /**
3183  * mem_precharge_and_activate() - Precharge all banks and activate
3184  *
3185  * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3186  */
3187 static void mem_precharge_and_activate(void)
3188 {
3189         int r;
3190
3191         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3192                 /* Test if the rank should be skipped. */
3193                 if (param->skip_ranks[r])
3194                         continue;
3195
3196                 /* Set rank. */
3197                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3198
3199                 /* Precharge all banks. */
3200                 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3201                                              RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3202
3203                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3204                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3205                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3206
3207                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3208                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3209                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3210
3211                 /* Activate rows. */
3212                 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3213                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3214         }
3215 }
3216
3217 /**
3218  * mem_init_latency() - Configure memory RLAT and WLAT settings
3219  *
3220  * Configure memory RLAT and WLAT parameters.
3221  */
3222 static void mem_init_latency(void)
3223 {
3224         /*
3225          * For AV/CV, LFIFO is hardened and always runs at full rate
3226          * so max latency in AFI clocks, used here, is correspondingly
3227          * smaller.
3228          */
3229         const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3230         u32 rlat, wlat;
3231
3232         debug("%s:%d\n", __func__, __LINE__);
3233
3234         /*
3235          * Read in write latency.
3236          * WL for Hard PHY does not include additive latency.
3237          */
3238         wlat = readl(&data_mgr->t_wl_add);
3239         wlat += readl(&data_mgr->mem_t_add);
3240
3241         gbl->rw_wl_nop_cycles = wlat - 1;
3242
3243         /* Read in readl latency. */
3244         rlat = readl(&data_mgr->t_rl_add);
3245
3246         /* Set a pretty high read latency initially. */
3247         gbl->curr_read_lat = rlat + 16;
3248         if (gbl->curr_read_lat > max_latency)
3249                 gbl->curr_read_lat = max_latency;
3250
3251         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3252
3253         /* Advertise write latency. */
3254         writel(wlat, &phy_mgr_cfg->afi_wlat);
3255 }
3256
3257 /**
3258  * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3259  *
3260  * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3261  */
3262 static void mem_skip_calibrate(void)
3263 {
3264         uint32_t vfifo_offset;
3265         uint32_t i, j, r;
3266
3267         debug("%s:%d\n", __func__, __LINE__);
3268         /* Need to update every shadow register set used by the interface */
3269         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3270              r += NUM_RANKS_PER_SHADOW_REG) {
3271                 /*
3272                  * Set output phase alignment settings appropriate for
3273                  * skip calibration.
3274                  */
3275                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3276                         scc_mgr_set_dqs_en_phase(i, 0);
3277 #if IO_DLL_CHAIN_LENGTH == 6
3278                         scc_mgr_set_dqdqs_output_phase(i, 6);
3279 #else
3280                         scc_mgr_set_dqdqs_output_phase(i, 7);
3281 #endif
3282                         /*
3283                          * Case:33398
3284                          *
3285                          * Write data arrives to the I/O two cycles before write
3286                          * latency is reached (720 deg).
3287                          *   -> due to bit-slip in a/c bus
3288                          *   -> to allow board skew where dqs is longer than ck
3289                          *      -> how often can this happen!?
3290                          *      -> can claim back some ptaps for high freq
3291                          *       support if we can relax this, but i digress...
3292                          *
3293                          * The write_clk leads mem_ck by 90 deg
3294                          * The minimum ptap of the OPA is 180 deg
3295                          * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3296                          * The write_clk is always delayed by 2 ptaps
3297                          *
3298                          * Hence, to make DQS aligned to CK, we need to delay
3299                          * DQS by:
3300                          *    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3301                          *
3302                          * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3303                          * gives us the number of ptaps, which simplies to:
3304                          *
3305                          *    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3306                          */
3307                         scc_mgr_set_dqdqs_output_phase(i,
3308                                         1.25 * IO_DLL_CHAIN_LENGTH - 2);
3309                 }
3310                 writel(0xff, &sdr_scc_mgr->dqs_ena);
3311                 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3312
3313                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3314                         writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3315                                   SCC_MGR_GROUP_COUNTER_OFFSET);
3316                 }
3317                 writel(0xff, &sdr_scc_mgr->dq_ena);
3318                 writel(0xff, &sdr_scc_mgr->dm_ena);
3319                 writel(0, &sdr_scc_mgr->update);
3320         }
3321
3322         /* Compensate for simulation model behaviour */
3323         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3324                 scc_mgr_set_dqs_bus_in_delay(i, 10);
3325                 scc_mgr_load_dqs(i);
3326         }
3327         writel(0, &sdr_scc_mgr->update);
3328
3329         /*
3330          * ArriaV has hard FIFOs that can only be initialized by incrementing
3331          * in sequencer.
3332          */
3333         vfifo_offset = CALIB_VFIFO_OFFSET;
3334         for (j = 0; j < vfifo_offset; j++)
3335                 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3336         writel(0, &phy_mgr_cmd->fifo_reset);
3337
3338         /*
3339          * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3340          * setting from generation-time constant.
3341          */
3342         gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3343         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3344 }
3345
3346 /**
3347  * mem_calibrate() - Memory calibration entry point.
3348  *
3349  * Perform memory calibration.
3350  */
3351 static uint32_t mem_calibrate(void)
3352 {
3353         uint32_t i;
3354         uint32_t rank_bgn, sr;
3355         uint32_t write_group, write_test_bgn;
3356         uint32_t read_group, read_test_bgn;
3357         uint32_t run_groups, current_run;
3358         uint32_t failing_groups = 0;
3359         uint32_t group_failed = 0;
3360
3361         const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3362                                 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3363
3364         debug("%s:%d\n", __func__, __LINE__);
3365
3366         /* Initialize the data settings */
3367         gbl->error_substage = CAL_SUBSTAGE_NIL;
3368         gbl->error_stage = CAL_STAGE_NIL;
3369         gbl->error_group = 0xff;
3370         gbl->fom_in = 0;
3371         gbl->fom_out = 0;
3372
3373         /* Initialize WLAT and RLAT. */
3374         mem_init_latency();
3375
3376         /* Initialize bit slips. */
3377         mem_precharge_and_activate();
3378
3379         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3380                 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3381                           SCC_MGR_GROUP_COUNTER_OFFSET);
3382                 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3383                 if (i == 0)
3384                         scc_mgr_set_hhp_extras();
3385
3386                 scc_set_bypass_mode(i);
3387         }
3388
3389         /* Calibration is skipped. */
3390         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3391                 /*
3392                  * Set VFIFO and LFIFO to instant-on settings in skip
3393                  * calibration mode.
3394                  */
3395                 mem_skip_calibrate();
3396
3397                 /*
3398                  * Do not remove this line as it makes sure all of our
3399                  * decisions have been applied.
3400                  */
3401                 writel(0, &sdr_scc_mgr->update);
3402                 return 1;
3403         }
3404
3405         /* Calibration is not skipped. */
3406         for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3407                 /*
3408                  * Zero all delay chain/phase settings for all
3409                  * groups and all shadow register sets.
3410                  */
3411                 scc_mgr_zero_all();
3412
3413                 run_groups = ~param->skip_groups;
3414
3415                 for (write_group = 0, write_test_bgn = 0; write_group
3416                         < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3417                         write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3418
3419                         /* Initialize the group failure */
3420                         group_failed = 0;
3421
3422                         current_run = run_groups & ((1 <<
3423                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3424                         run_groups = run_groups >>
3425                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3426
3427                         if (current_run == 0)
3428                                 continue;
3429
3430                         writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3431                                             SCC_MGR_GROUP_COUNTER_OFFSET);
3432                         scc_mgr_zero_group(write_group, 0);
3433
3434                         for (read_group = write_group * rwdqs_ratio,
3435                              read_test_bgn = 0;
3436                              read_group < (write_group + 1) * rwdqs_ratio;
3437                              read_group++,
3438                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3439                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3440                                         continue;
3441
3442                                 /* Calibrate the VFIFO */
3443                                 if (rw_mgr_mem_calibrate_vfifo(read_group,
3444                                                                read_test_bgn))
3445                                         continue;
3446
3447                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3448                                         return 0;
3449
3450                                 /* The group failed, we're done. */
3451                                 goto grp_failed;
3452                         }
3453
3454                         /* Calibrate the output side */
3455                         for (rank_bgn = 0, sr = 0;
3456                              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3457                              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3458                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3459                                         continue;
3460
3461                                 /* Not needed in quick mode! */
3462                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3463                                         continue;
3464
3465                                 /*
3466                                  * Determine if this set of ranks
3467                                  * should be skipped entirely.
3468                                  */
3469                                 if (param->skip_shadow_regs[sr])
3470                                         continue;
3471
3472                                 /* Calibrate WRITEs */
3473                                 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3474                                                 write_group, write_test_bgn))
3475                                         continue;
3476
3477                                 group_failed = 1;
3478                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3479                                         return 0;
3480                         }
3481
3482                         /* Some group failed, we're done. */
3483                         if (group_failed)
3484                                 goto grp_failed;
3485
3486                         for (read_group = write_group * rwdqs_ratio,
3487                              read_test_bgn = 0;
3488                              read_group < (write_group + 1) * rwdqs_ratio;
3489                              read_group++,
3490                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3491                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3492                                         continue;
3493
3494                                 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3495                                                                 read_test_bgn))
3496                                         continue;
3497
3498                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3499                                         return 0;
3500
3501                                 /* The group failed, we're done. */
3502                                 goto grp_failed;
3503                         }
3504
3505                         /* No group failed, continue as usual. */
3506                         continue;
3507
3508 grp_failed:             /* A group failed, increment the counter. */
3509                         failing_groups++;
3510                 }
3511
3512                 /*
3513                  * USER If there are any failing groups then report
3514                  * the failure.
3515                  */
3516                 if (failing_groups != 0)
3517                         return 0;
3518
3519                 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3520                         continue;
3521
3522                 /*
3523                  * If we're skipping groups as part of debug,
3524                  * don't calibrate LFIFO.
3525                  */
3526                 if (param->skip_groups != 0)
3527                         continue;
3528
3529                 /* Calibrate the LFIFO */
3530                 if (!rw_mgr_mem_calibrate_lfifo())
3531                         return 0;
3532         }
3533
3534         /*
3535          * Do not remove this line as it makes sure all of our decisions
3536          * have been applied.
3537          */
3538         writel(0, &sdr_scc_mgr->update);
3539         return 1;
3540 }
3541
3542 /**
3543  * run_mem_calibrate() - Perform memory calibration
3544  *
3545  * This function triggers the entire memory calibration procedure.
3546  */
3547 static int run_mem_calibrate(void)
3548 {
3549         int pass;
3550
3551         debug("%s:%d\n", __func__, __LINE__);
3552
3553         /* Reset pass/fail status shown on afi_cal_success/fail */
3554         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3555
3556         /* Stop tracking manager. */
3557         clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3558
3559         phy_mgr_initialize();
3560         rw_mgr_mem_initialize();
3561
3562         /* Perform the actual memory calibration. */
3563         pass = mem_calibrate();
3564
3565         mem_precharge_and_activate();
3566         writel(0, &phy_mgr_cmd->fifo_reset);
3567
3568         /* Handoff. */
3569         rw_mgr_mem_handoff();
3570         /*
3571          * In Hard PHY this is a 2-bit control:
3572          * 0: AFI Mux Select
3573          * 1: DDIO Mux Select
3574          */
3575         writel(0x2, &phy_mgr_cfg->mux_sel);
3576
3577         /* Start tracking manager. */
3578         setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3579
3580         return pass;
3581 }
3582
3583 /**
3584  * debug_mem_calibrate() - Report result of memory calibration
3585  * @pass:       Value indicating whether calibration passed or failed
3586  *
3587  * This function reports the results of the memory calibration
3588  * and writes debug information into the register file.
3589  */
3590 static void debug_mem_calibrate(int pass)
3591 {
3592         uint32_t debug_info;
3593
3594         if (pass) {
3595                 printf("%s: CALIBRATION PASSED\n", __FILE__);
3596
3597                 gbl->fom_in /= 2;
3598                 gbl->fom_out /= 2;
3599
3600                 if (gbl->fom_in > 0xff)
3601                         gbl->fom_in = 0xff;
3602
3603                 if (gbl->fom_out > 0xff)
3604                         gbl->fom_out = 0xff;
3605
3606                 /* Update the FOM in the register file */
3607                 debug_info = gbl->fom_in;
3608                 debug_info |= gbl->fom_out << 8;
3609                 writel(debug_info, &sdr_reg_file->fom);
3610
3611                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3612                 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3613         } else {
3614                 printf("%s: CALIBRATION FAILED\n", __FILE__);
3615
3616                 debug_info = gbl->error_stage;
3617                 debug_info |= gbl->error_substage << 8;
3618                 debug_info |= gbl->error_group << 16;
3619
3620                 writel(debug_info, &sdr_reg_file->failing_stage);
3621                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3622                 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3623
3624                 /* Update the failing group/stage in the register file */
3625                 debug_info = gbl->error_stage;
3626                 debug_info |= gbl->error_substage << 8;
3627                 debug_info |= gbl->error_group << 16;
3628                 writel(debug_info, &sdr_reg_file->failing_stage);
3629         }
3630
3631         printf("%s: Calibration complete\n", __FILE__);
3632 }
3633
3634 /**
3635  * hc_initialize_rom_data() - Initialize ROM data
3636  *
3637  * Initialize ROM data.
3638  */
3639 static void hc_initialize_rom_data(void)
3640 {
3641         u32 i, addr;
3642
3643         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3644         for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3645                 writel(inst_rom_init[i], addr + (i << 2));
3646
3647         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3648         for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3649                 writel(ac_rom_init[i], addr + (i << 2));
3650 }
3651
3652 /**
3653  * initialize_reg_file() - Initialize SDR register file
3654  *
3655  * Initialize SDR register file.
3656  */
3657 static void initialize_reg_file(void)
3658 {
3659         /* Initialize the register file with the correct data */
3660         writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3661         writel(0, &sdr_reg_file->debug_data_addr);
3662         writel(0, &sdr_reg_file->cur_stage);
3663         writel(0, &sdr_reg_file->fom);
3664         writel(0, &sdr_reg_file->failing_stage);
3665         writel(0, &sdr_reg_file->debug1);
3666         writel(0, &sdr_reg_file->debug2);
3667 }
3668
3669 /**
3670  * initialize_hps_phy() - Initialize HPS PHY
3671  *
3672  * Initialize HPS PHY.
3673  */
3674 static void initialize_hps_phy(void)
3675 {
3676         uint32_t reg;
3677         /*
3678          * Tracking also gets configured here because it's in the
3679          * same register.
3680          */
3681         uint32_t trk_sample_count = 7500;
3682         uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3683         /*
3684          * Format is number of outer loops in the 16 MSB, sample
3685          * count in 16 LSB.
3686          */
3687
3688         reg = 0;
3689         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3690         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3691         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3692         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3693         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3694         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3695         /*
3696          * This field selects the intrinsic latency to RDATA_EN/FULL path.
3697          * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3698          */
3699         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3700         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3701                 trk_sample_count);
3702         writel(reg, &sdr_ctrl->phy_ctrl0);
3703
3704         reg = 0;
3705         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3706                 trk_sample_count >>
3707                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3708         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3709                 trk_long_idle_sample_count);
3710         writel(reg, &sdr_ctrl->phy_ctrl1);
3711
3712         reg = 0;
3713         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3714                 trk_long_idle_sample_count >>
3715                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3716         writel(reg, &sdr_ctrl->phy_ctrl2);
3717 }
3718
3719 /**
3720  * initialize_tracking() - Initialize tracking
3721  *
3722  * Initialize the register file with usable initial data.
3723  */
3724 static void initialize_tracking(void)
3725 {
3726         /*
3727          * Initialize the register file with the correct data.
3728          * Compute usable version of value in case we skip full
3729          * computation later.
3730          */
3731         writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3732                &sdr_reg_file->dtaps_per_ptap);
3733
3734         /* trk_sample_count */
3735         writel(7500, &sdr_reg_file->trk_sample_count);
3736
3737         /* longidle outer loop [15:0] */
3738         writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3739
3740         /*
3741          * longidle sample count [31:24]
3742          * trfc, worst case of 933Mhz 4Gb [23:16]
3743          * trcd, worst case [15:8]
3744          * vfifo wait [7:0]
3745          */
3746         writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3747                &sdr_reg_file->delays);
3748
3749         /* mux delay */
3750         writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3751                (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3752                &sdr_reg_file->trk_rw_mgr_addr);
3753
3754         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3755                &sdr_reg_file->trk_read_dqs_width);
3756
3757         /* trefi [7:0] */
3758         writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3759                &sdr_reg_file->trk_rfsh);
3760 }
3761
3762 int sdram_calibration_full(void)
3763 {
3764         struct param_type my_param;
3765         struct gbl_type my_gbl;
3766         uint32_t pass;
3767
3768         memset(&my_param, 0, sizeof(my_param));
3769         memset(&my_gbl, 0, sizeof(my_gbl));
3770
3771         param = &my_param;
3772         gbl = &my_gbl;
3773
3774         /* Set the calibration enabled by default */
3775         gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3776         /*
3777          * Only sweep all groups (regardless of fail state) by default
3778          * Set enabled read test by default.
3779          */
3780 #if DISABLE_GUARANTEED_READ
3781         gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3782 #endif
3783         /* Initialize the register file */
3784         initialize_reg_file();
3785
3786         /* Initialize any PHY CSR */
3787         initialize_hps_phy();
3788
3789         scc_mgr_initialize();
3790
3791         initialize_tracking();
3792
3793         printf("%s: Preparing to start memory calibration\n", __FILE__);
3794
3795         debug("%s:%d\n", __func__, __LINE__);
3796         debug_cond(DLEVEL == 1,
3797                    "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3798                    RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3799                    RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3800                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3801                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3802         debug_cond(DLEVEL == 1,
3803                    "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3804                    RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3805                    RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3806                    IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3807         debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3808                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3809         debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3810                    IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3811                    IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3812         debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3813                    IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3814                    IO_IO_OUT2_DELAY_MAX);
3815         debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3816                    IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3817
3818         hc_initialize_rom_data();
3819
3820         /* update info for sims */
3821         reg_file_set_stage(CAL_STAGE_NIL);
3822         reg_file_set_group(0);
3823
3824         /*
3825          * Load global needed for those actions that require
3826          * some dynamic calibration support.
3827          */
3828         dyn_calib_steps = STATIC_CALIB_STEPS;
3829         /*
3830          * Load global to allow dynamic selection of delay loop settings
3831          * based on calibration mode.
3832          */
3833         if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3834                 skip_delay_mask = 0xff;
3835         else
3836                 skip_delay_mask = 0x0;
3837
3838         pass = run_mem_calibrate();
3839         debug_mem_calibrate(pass);
3840         return pass;
3841 }