2 * Copyright 2008-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017-2018 NXP Semiconductor
5 * SPDX-License-Identifier: GPL-2.0+
9 * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
10 * Based on code from spd_sdram.c
11 * Author: James Yang [at freescale.com]
15 #include <fsl_ddr_sdram.h>
16 #include <fsl_errata.h>
18 #include <fsl_immap.h>
20 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
22 #include <asm/arch/clock.h>
26 * Determine Rtt value.
28 * This should likely be either board or controller specific.
30 * Rtt(nominal) - DDR2:
35 * Rtt(nominal) - DDR3:
43 * FIXME: Apparently 8641 needs a value of 2
44 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
46 * FIXME: There was some effort down this line earlier:
49 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
50 * if (popts->dimmslot[i].num_valid_cs
51 * && (popts->cs_local_opts[2*i].odt_rd_cfg
52 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
58 static inline int fsl_ddr_get_rtt(void)
62 #if defined(CONFIG_SYS_FSL_DDR1)
64 #elif defined(CONFIG_SYS_FSL_DDR2)
73 #ifdef CONFIG_SYS_FSL_DDR4
75 * compute CAS write latency according to DDR4 spec
76 * CWL = 9 for <= 1600MT/s
84 static inline unsigned int compute_cas_write_latency(
85 const unsigned int ctrl_num)
88 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
91 else if (mclk_ps >= 1070)
93 else if (mclk_ps >= 935)
95 else if (mclk_ps >= 833)
97 else if (mclk_ps >= 750)
99 else if (mclk_ps >= 681)
108 * compute the CAS write latency according to DDR3 spec
109 * CWL = 5 if tCK >= 2.5ns
110 * 6 if 2.5ns > tCK >= 1.875ns
111 * 7 if 1.875ns > tCK >= 1.5ns
112 * 8 if 1.5ns > tCK >= 1.25ns
113 * 9 if 1.25ns > tCK >= 1.07ns
114 * 10 if 1.07ns > tCK >= 0.935ns
115 * 11 if 0.935ns > tCK >= 0.833ns
116 * 12 if 0.833ns > tCK >= 0.75ns
118 static inline unsigned int compute_cas_write_latency(
119 const unsigned int ctrl_num)
122 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
126 else if (mclk_ps >= 1875)
128 else if (mclk_ps >= 1500)
130 else if (mclk_ps >= 1250)
132 else if (mclk_ps >= 1070)
134 else if (mclk_ps >= 935)
136 else if (mclk_ps >= 833)
138 else if (mclk_ps >= 750)
142 printf("Warning: CWL is out of range\n");
148 /* Chip Select Configuration (CSn_CONFIG) */
149 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
150 const memctl_options_t *popts,
151 const dimm_params_t *dimm_params)
153 unsigned int cs_n_en = 0; /* Chip Select enable */
154 unsigned int intlv_en = 0; /* Memory controller interleave enable */
155 unsigned int intlv_ctl = 0; /* Interleaving control */
156 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
157 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
158 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
159 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
160 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
161 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
163 #ifdef CONFIG_SYS_FSL_DDR4
164 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
166 unsigned int n_banks_per_sdram_device;
169 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
172 if (dimm_params[dimm_number].n_ranks > 0) {
174 /* These fields only available in CS0_CONFIG */
175 if (!popts->memctl_interleaving)
177 switch (popts->memctl_interleaving_mode) {
178 case FSL_DDR_256B_INTERLEAVING:
179 case FSL_DDR_CACHE_LINE_INTERLEAVING:
180 case FSL_DDR_PAGE_INTERLEAVING:
181 case FSL_DDR_BANK_INTERLEAVING:
182 case FSL_DDR_SUPERBANK_INTERLEAVING:
183 intlv_en = popts->memctl_interleaving;
184 intlv_ctl = popts->memctl_interleaving_mode;
192 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
193 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
197 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
198 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
202 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
203 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
204 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
212 ap_n_en = popts->cs_local_opts[i].auto_precharge;
213 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
214 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
215 #ifdef CONFIG_SYS_FSL_DDR4
216 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
217 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
219 n_banks_per_sdram_device
220 = dimm_params[dimm_number].n_banks_per_sdram_device;
221 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
223 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
224 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
226 ddr->cs[i].config = (0
227 | ((cs_n_en & 0x1) << 31)
228 | ((intlv_en & 0x3) << 29)
229 | ((intlv_ctl & 0xf) << 24)
230 | ((ap_n_en & 0x1) << 23)
232 /* XXX: some implementation only have 1 bit starting at left */
233 | ((odt_rd_cfg & 0x7) << 20)
235 /* XXX: Some implementation only have 1 bit starting at left */
236 | ((odt_wr_cfg & 0x7) << 16)
238 | ((ba_bits_cs_n & 0x3) << 14)
239 | ((row_bits_cs_n & 0x7) << 8)
240 #ifdef CONFIG_SYS_FSL_DDR4
241 | ((bg_bits_cs_n & 0x3) << 4)
243 | ((col_bits_cs_n & 0x7) << 0)
245 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
248 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
250 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
252 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
254 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
255 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
258 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
260 #if !defined(CONFIG_SYS_FSL_DDR1)
262 * Check DIMM configuration, return 2 if quad-rank or two dual-rank
263 * Return 1 if other two slots configuration. Return 0 if single slot.
265 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
267 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
268 if (dimm_params[0].n_ranks == 4)
272 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
273 if ((dimm_params[0].n_ranks == 2) &&
274 (dimm_params[1].n_ranks == 2))
277 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
278 if (dimm_params[0].n_ranks == 4)
282 if ((dimm_params[0].n_ranks != 0) &&
283 (dimm_params[2].n_ranks != 0))
290 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
292 * Avoid writing for DDR I. The new PQ38 DDR controller
293 * dreams up non-zero default values to be backwards compatible.
295 static void set_timing_cfg_0(const unsigned int ctrl_num,
296 fsl_ddr_cfg_regs_t *ddr,
297 const memctl_options_t *popts,
298 const dimm_params_t *dimm_params)
300 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
301 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
302 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
303 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
304 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
306 /* Active powerdown exit timing (tXARD and tXARDS). */
307 unsigned char act_pd_exit_mclk;
308 /* Precharge powerdown exit timing (tXP). */
309 unsigned char pre_pd_exit_mclk;
310 /* ODT powerdown exit timing (tAXPD). */
311 unsigned char taxpd_mclk = 0;
312 /* Mode register set cycle time (tMRD). */
313 unsigned char tmrd_mclk;
314 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
315 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
318 #ifdef CONFIG_SYS_FSL_DDR4
319 /* tXP=max(4nCK, 6ns) */
320 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
321 unsigned int data_rate = get_ddr_freq(ctrl_num);
323 /* for faster clock, need more time for data setup */
324 trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
327 * for single quad-rank DIMM and two-slot DIMMs
328 * to avoid ODT overlap
330 switch (avoid_odt_overlap(dimm_params)) {
343 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
344 pre_pd_exit_mclk = act_pd_exit_mclk;
346 * MRS_CYC = max(tMRD, tMOD)
347 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
349 tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
350 #elif defined(CONFIG_SYS_FSL_DDR3)
351 unsigned int data_rate = get_ddr_freq(ctrl_num);
356 * (tXARD and tXARDS). Empirical?
357 * The DDR3 spec has not tXARD,
358 * we use the tXP instead of it.
359 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
360 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
361 * spec has not the tAXPD, we use
362 * tAXPD=1, need design to confirm.
364 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
366 ip_rev = fsl_ddr_get_version(ctrl_num);
367 if (ip_rev >= 0x40700) {
369 * MRS_CYC = max(tMRD, tMOD)
370 * tMRD = 4nCK (8nCK for RDIMM)
371 * tMOD = max(12nCK, 15ns)
373 tmrd_mclk = max((unsigned int)12,
374 picos_to_mclk(ctrl_num, 15000));
378 * tMRD = 4nCK (8nCK for RDIMM)
380 if (popts->registered_dimm_en)
386 /* set the turnaround time */
389 * for single quad-rank DIMM and two-slot DIMMs
390 * to avoid ODT overlap
392 odt_overlap = avoid_odt_overlap(dimm_params);
393 switch (odt_overlap) {
406 /* for faster clock, need more time for data setup */
407 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
409 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
412 if (popts->dynamic_power == 0) { /* powerdown is not used */
413 act_pd_exit_mclk = 1;
414 pre_pd_exit_mclk = 1;
417 /* act_pd_exit_mclk = tXARD, see above */
418 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
419 /* Mode register MR0[A12] is '1' - fast exit */
420 pre_pd_exit_mclk = act_pd_exit_mclk;
423 #else /* CONFIG_SYS_FSL_DDR2 */
425 * (tXARD and tXARDS). Empirical?
430 act_pd_exit_mclk = 2;
431 pre_pd_exit_mclk = 2;
436 if (popts->trwt_override)
437 trwt_mclk = popts->trwt;
439 ddr->timing_cfg_0 = (0
440 | ((trwt_mclk & 0x3) << 30) /* RWT */
441 | ((twrt_mclk & 0x3) << 28) /* WRT */
442 | ((trrt_mclk & 0x3) << 26) /* RRT */
443 | ((twwt_mclk & 0x3) << 24) /* WWT */
444 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
445 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
446 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
447 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
449 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
451 #endif /* !defined(CONFIG_SYS_FSL_DDR1) */
453 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
454 static void set_timing_cfg_3(const unsigned int ctrl_num,
455 fsl_ddr_cfg_regs_t *ddr,
456 const memctl_options_t *popts,
457 const common_timing_params_t *common_dimm,
458 unsigned int cas_latency,
459 unsigned int additive_latency)
461 /* Extended precharge to activate interval (tRP) */
462 unsigned int ext_pretoact = 0;
463 /* Extended Activate to precharge interval (tRAS) */
464 unsigned int ext_acttopre = 0;
465 /* Extended activate to read/write interval (tRCD) */
466 unsigned int ext_acttorw = 0;
467 /* Extended refresh recovery time (tRFC) */
468 unsigned int ext_refrec;
469 /* Extended MCAS latency from READ cmd */
470 unsigned int ext_caslat = 0;
471 /* Extended additive latency */
472 unsigned int ext_add_lat = 0;
473 /* Extended last data to precharge interval (tWR) */
474 unsigned int ext_wrrec = 0;
476 unsigned int cntl_adj = 0;
478 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
479 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
480 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
481 ext_caslat = (2 * cas_latency - 1) >> 4;
482 ext_add_lat = additive_latency >> 4;
483 #ifdef CONFIG_SYS_FSL_DDR4
484 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
486 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
487 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
489 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
490 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
492 ddr->timing_cfg_3 = (0
493 | ((ext_pretoact & 0x1) << 28)
494 | ((ext_acttopre & 0x3) << 24)
495 | ((ext_acttorw & 0x1) << 22)
496 | ((ext_refrec & 0x3F) << 16)
497 | ((ext_caslat & 0x3) << 12)
498 | ((ext_add_lat & 0x1) << 10)
499 | ((ext_wrrec & 0x1) << 8)
500 | ((cntl_adj & 0x7) << 0)
502 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
505 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
506 static void set_timing_cfg_1(const unsigned int ctrl_num,
507 fsl_ddr_cfg_regs_t *ddr,
508 const memctl_options_t *popts,
509 const common_timing_params_t *common_dimm,
510 unsigned int cas_latency)
512 /* Precharge-to-activate interval (tRP) */
513 unsigned char pretoact_mclk;
514 /* Activate to precharge interval (tRAS) */
515 unsigned char acttopre_mclk;
516 /* Activate to read/write interval (tRCD) */
517 unsigned char acttorw_mclk;
519 unsigned char caslat_ctrl;
520 /* Refresh recovery time (tRFC) ; trfc_low */
521 unsigned char refrec_ctrl;
522 /* Last data to precharge minimum interval (tWR) */
523 unsigned char wrrec_mclk;
524 /* Activate-to-activate interval (tRRD) */
525 unsigned char acttoact_mclk;
526 /* Last write data pair to read command issue interval (tWTR) */
527 unsigned char wrtord_mclk;
528 #ifdef CONFIG_SYS_FSL_DDR4
529 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
530 static const u8 wrrec_table[] = {
537 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
538 static const u8 wrrec_table[] = {
539 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
542 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
543 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
544 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
547 * Translate CAS Latency to a DDR controller field value:
549 * CAS Lat DDR I DDR II Ctrl
550 * Clocks SPD Bit SPD Bit Value
551 * ------- ------- ------- -----
562 #if defined(CONFIG_SYS_FSL_DDR1)
563 caslat_ctrl = (cas_latency + 1) & 0x07;
564 #elif defined(CONFIG_SYS_FSL_DDR2)
565 caslat_ctrl = 2 * cas_latency - 1;
568 * if the CAS latency more than 8 cycle,
569 * we need set extend bit for it at
570 * TIMING_CFG_3[EXT_CASLAT]
572 if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
573 caslat_ctrl = 2 * cas_latency - 1;
575 caslat_ctrl = (cas_latency - 1) << 1;
578 #ifdef CONFIG_SYS_FSL_DDR4
579 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
580 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
581 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
582 wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
583 if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
584 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
586 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
588 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
589 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
590 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
591 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
592 if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
593 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
595 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
597 if (popts->otf_burst_chop_en)
601 * JEDEC has min requirement for tRRD
603 #if defined(CONFIG_SYS_FSL_DDR3)
604 if (acttoact_mclk < 4)
608 * JEDEC has some min requirements for tWTR
610 #if defined(CONFIG_SYS_FSL_DDR2)
613 #elif defined(CONFIG_SYS_FSL_DDR3)
617 if (popts->otf_burst_chop_en)
620 ddr->timing_cfg_1 = (0
621 | ((pretoact_mclk & 0x0F) << 28)
622 | ((acttopre_mclk & 0x0F) << 24)
623 | ((acttorw_mclk & 0xF) << 20)
624 | ((caslat_ctrl & 0xF) << 16)
625 | ((refrec_ctrl & 0xF) << 12)
626 | ((wrrec_mclk & 0x0F) << 8)
627 | ((acttoact_mclk & 0x0F) << 4)
628 | ((wrtord_mclk & 0x0F) << 0)
630 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
633 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
634 static void set_timing_cfg_2(const unsigned int ctrl_num,
635 fsl_ddr_cfg_regs_t *ddr,
636 const memctl_options_t *popts,
637 const common_timing_params_t *common_dimm,
638 unsigned int cas_latency,
639 unsigned int additive_latency)
641 /* Additive latency */
642 unsigned char add_lat_mclk;
643 /* CAS-to-preamble override */
646 unsigned char wr_lat;
647 /* Read to precharge (tRTP) */
648 unsigned char rd_to_pre;
649 /* Write command to write data strobe timing adjustment */
650 unsigned char wr_data_delay;
651 /* Minimum CKE pulse width (tCKE) */
652 unsigned char cke_pls;
653 /* Window for four activates (tFAW) */
654 unsigned short four_act;
655 #ifdef CONFIG_SYS_FSL_DDR3
656 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
659 /* FIXME add check that this must be less than acttorw_mclk */
660 add_lat_mclk = additive_latency;
661 cpo = popts->cpo_override;
663 #if defined(CONFIG_SYS_FSL_DDR1)
665 * This is a lie. It should really be 1, but if it is
666 * set to 1, bits overlap into the old controller's
667 * otherwise unused ACSM field. If we leave it 0, then
668 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
671 #elif defined(CONFIG_SYS_FSL_DDR2)
672 wr_lat = cas_latency - 1;
674 wr_lat = compute_cas_write_latency(ctrl_num);
677 #ifdef CONFIG_SYS_FSL_DDR4
678 rd_to_pre = picos_to_mclk(ctrl_num, 7500);
680 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
683 * JEDEC has some min requirements for tRTP
685 #if defined(CONFIG_SYS_FSL_DDR2)
688 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
692 if (popts->otf_burst_chop_en)
693 rd_to_pre += 2; /* according to UM */
695 wr_data_delay = popts->write_data_delay;
696 #ifdef CONFIG_SYS_FSL_DDR4
698 cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
699 #elif defined(CONFIG_SYS_FSL_DDR3)
701 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
702 * max(3nCK, 5.625ns) for DDR3-1066, 1333
703 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
705 cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
706 (mclk_ps > 1245 ? 5625 : 5000)));
708 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
710 four_act = picos_to_mclk(ctrl_num,
711 popts->tfaw_window_four_activates_ps);
713 ddr->timing_cfg_2 = (0
714 | ((add_lat_mclk & 0xf) << 28)
715 | ((cpo & 0x1f) << 23)
716 | ((wr_lat & 0xf) << 19)
717 | (((wr_lat & 0x10) >> 4) << 18)
718 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
719 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
720 | ((cke_pls & 0x7) << 6)
721 | ((four_act & 0x3f) << 0)
723 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
726 /* DDR SDRAM Register Control Word */
727 static void set_ddr_sdram_rcw(const unsigned int ctrl_num,
728 fsl_ddr_cfg_regs_t *ddr,
729 const memctl_options_t *popts,
730 const common_timing_params_t *common_dimm)
732 unsigned int ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
733 unsigned int rc0a, rc0f;
735 if (common_dimm->all_dimms_registered &&
736 !common_dimm->all_dimms_unbuffered) {
737 if (popts->rcw_override) {
738 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
739 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
740 ddr->ddr_sdram_rcw_3 = popts->rcw_3;
742 rc0a = ddr_freq > 3200 ? 0x7 :
743 (ddr_freq > 2933 ? 0x6 :
744 (ddr_freq > 2666 ? 0x5 :
745 (ddr_freq > 2400 ? 0x4 :
746 (ddr_freq > 2133 ? 0x3 :
747 (ddr_freq > 1866 ? 0x2 :
748 (ddr_freq > 1600 ? 1 : 0))))));
749 rc0f = ddr_freq > 3200 ? 0x3 :
750 (ddr_freq > 2400 ? 0x2 :
751 (ddr_freq > 2133 ? 0x1 : 0));
752 ddr->ddr_sdram_rcw_1 =
753 common_dimm->rcw[0] << 28 | \
754 common_dimm->rcw[1] << 24 | \
755 common_dimm->rcw[2] << 20 | \
756 common_dimm->rcw[3] << 16 | \
757 common_dimm->rcw[4] << 12 | \
758 common_dimm->rcw[5] << 8 | \
759 common_dimm->rcw[6] << 4 | \
761 ddr->ddr_sdram_rcw_2 =
762 common_dimm->rcw[8] << 28 | \
763 common_dimm->rcw[9] << 24 | \
765 common_dimm->rcw[11] << 16 | \
766 common_dimm->rcw[12] << 12 | \
767 common_dimm->rcw[13] << 8 | \
768 common_dimm->rcw[14] << 4 | \
770 ddr->ddr_sdram_rcw_3 =
771 ((ddr_freq - 1260 + 19) / 20) << 8;
773 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n",
774 ddr->ddr_sdram_rcw_1);
775 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n",
776 ddr->ddr_sdram_rcw_2);
777 debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n",
778 ddr->ddr_sdram_rcw_3);
782 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
783 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
784 const memctl_options_t *popts,
785 const common_timing_params_t *common_dimm)
787 unsigned int mem_en; /* DDR SDRAM interface logic enable */
788 unsigned int sren; /* Self refresh enable (during sleep) */
789 unsigned int ecc_en; /* ECC enable. */
790 unsigned int rd_en; /* Registered DIMM enable */
791 unsigned int sdram_type; /* Type of SDRAM */
792 unsigned int dyn_pwr; /* Dynamic power management mode */
793 unsigned int dbw; /* DRAM dta bus width */
794 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
795 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
796 unsigned int threet_en; /* Enable 3T timing */
797 unsigned int twot_en; /* Enable 2T timing */
798 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
799 unsigned int x32_en = 0; /* x32 enable */
800 unsigned int pchb8 = 0; /* precharge bit 8 enable */
801 unsigned int hse; /* Global half strength override */
802 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
803 unsigned int mem_halt = 0; /* memory controller halt */
804 unsigned int bi = 0; /* Bypass initialization */
807 sren = popts->self_refresh_in_sleep;
808 if (common_dimm->all_dimms_ecc_capable) {
809 /* Allow setting of ECC only if all DIMMs are ECC. */
810 ecc_en = popts->ecc_mode;
815 if (common_dimm->all_dimms_registered &&
816 !common_dimm->all_dimms_unbuffered) {
821 twot_en = popts->twot_en;
824 sdram_type = CONFIG_FSL_SDRAM_TYPE;
826 dyn_pwr = popts->dynamic_power;
827 dbw = popts->data_bus_width;
828 /* 8-beat burst enable DDR-III case
829 * we must clear it when use the on-the-fly mode,
830 * must set it when use the 32-bits bus mode.
832 if ((sdram_type == SDRAM_TYPE_DDR3) ||
833 (sdram_type == SDRAM_TYPE_DDR4)) {
834 if (popts->burst_length == DDR_BL8)
836 if (popts->burst_length == DDR_OTF)
842 threet_en = popts->threet_en;
843 ba_intlv_ctl = popts->ba_intlv_ctl;
844 hse = popts->half_strength_driver_enable;
846 /* set when ddr bus width < 64 */
847 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
849 ddr->ddr_sdram_cfg = (0
850 | ((mem_en & 0x1) << 31)
851 | ((sren & 0x1) << 30)
852 | ((ecc_en & 0x1) << 29)
853 | ((rd_en & 0x1) << 28)
854 | ((sdram_type & 0x7) << 24)
855 | ((dyn_pwr & 0x1) << 21)
856 | ((dbw & 0x3) << 19)
857 | ((eight_be & 0x1) << 18)
858 | ((ncap & 0x1) << 17)
859 | ((threet_en & 0x1) << 16)
860 | ((twot_en & 0x1) << 15)
861 | ((ba_intlv_ctl & 0x7F) << 8)
862 | ((x32_en & 0x1) << 5)
863 | ((pchb8 & 0x1) << 4)
865 | ((acc_ecc_en & 0x1) << 2)
866 | ((mem_halt & 0x1) << 1)
869 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
872 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
873 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
874 fsl_ddr_cfg_regs_t *ddr,
875 const memctl_options_t *popts,
876 const unsigned int unq_mrs_en)
878 unsigned int frc_sr = 0; /* Force self refresh */
879 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
880 unsigned int odt_cfg = 0; /* ODT configuration */
881 unsigned int num_pr; /* Number of posted refreshes */
882 unsigned int slow = 0; /* DDR will be run less than 1250 */
883 unsigned int x4_en = 0; /* x4 DRAM enable */
884 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
885 unsigned int ap_en; /* Address Parity Enable */
886 unsigned int d_init; /* DRAM data initialization */
887 unsigned int rcw_en = 0; /* Register Control Word Enable */
888 unsigned int md_en = 0; /* Mirrored DIMM Enable */
889 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
891 #ifndef CONFIG_SYS_FSL_DDR4
892 unsigned int dll_rst_dis = 1; /* DLL reset disable */
893 unsigned int dqs_cfg; /* DQS configuration */
895 dqs_cfg = popts->dqs_config;
897 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
898 if (popts->cs_local_opts[i].odt_rd_cfg
899 || popts->cs_local_opts[i].odt_wr_cfg) {
900 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
904 sr_ie = popts->self_refresh_interrupt_en;
905 num_pr = popts->package_3ds + 1;
909 * {TIMING_CFG_1[PRETOACT]
910 * + [DDR_SDRAM_CFG_2[NUM_PR]
911 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
912 * << DDR_SDRAM_INTERVAL[REFINT]
914 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
915 obc_cfg = popts->otf_burst_chop_en;
920 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
921 slow = get_ddr_freq(ctrl_num) < 1249000000;
924 if (popts->registered_dimm_en)
927 /* DDR4 can have address parity for UDIMM and discrete */
928 if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
929 (!popts->registered_dimm_en)) {
932 ap_en = popts->ap_en;
935 x4_en = popts->x4_en ? 1 : 0;
937 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
938 /* Use the DDR controller to auto initialize memory. */
939 d_init = popts->ecc_init_using_memctl;
940 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
941 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
943 /* Memory will be initialized via DMA, or not at all. */
947 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
948 md_en = popts->mirrored_dimm;
950 qd_en = popts->quad_rank_present ? 1 : 0;
951 ddr->ddr_sdram_cfg_2 = (0
952 | ((frc_sr & 0x1) << 31)
953 | ((sr_ie & 0x1) << 30)
954 #ifndef CONFIG_SYS_FSL_DDR4
955 | ((dll_rst_dis & 0x1) << 29)
956 | ((dqs_cfg & 0x3) << 26)
958 | ((odt_cfg & 0x3) << 21)
959 | ((num_pr & 0xf) << 12)
964 | ((obc_cfg & 0x1) << 6)
965 | ((ap_en & 0x1) << 5)
966 | ((d_init & 0x1) << 4)
967 | ((rcw_en & 0x1) << 2)
968 | ((md_en & 0x1) << 0)
970 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
973 #ifdef CONFIG_SYS_FSL_DDR4
974 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
975 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
976 fsl_ddr_cfg_regs_t *ddr,
977 const memctl_options_t *popts,
978 const common_timing_params_t *common_dimm,
979 const unsigned int unq_mrs_en)
981 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
982 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
984 unsigned int wr_crc = 0; /* Disable */
985 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
986 unsigned int srt = 0; /* self-refresh temerature, normal range */
987 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
988 unsigned int mpr = 0; /* serial */
990 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
992 if (popts->rtt_override)
993 rtt_wr = popts->rtt_wr_override_value;
995 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
997 if (common_dimm->extended_op_srt)
998 srt = common_dimm->extended_op_srt;
1001 | ((wr_crc & 0x1) << 12)
1002 | ((rtt_wr & 0x3) << 9)
1003 | ((srt & 0x3) << 6)
1004 | ((cwl & 0x7) << 3));
1006 if (mclk_ps >= 1250)
1008 else if (mclk_ps >= 833)
1014 | ((mpr & 0x3) << 11)
1015 | ((wc_lat & 0x3) << 9));
1017 ddr->ddr_sdram_mode_2 = (0
1018 | ((esdmode2 & 0xFFFF) << 16)
1019 | ((esdmode3 & 0xFFFF) << 0)
1021 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1023 if (unq_mrs_en) { /* unique mode registers are supported */
1024 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1025 if (popts->rtt_override)
1026 rtt_wr = popts->rtt_wr_override_value;
1028 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1030 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1031 esdmode2 |= (rtt_wr & 0x3) << 9;
1034 ddr->ddr_sdram_mode_4 = (0
1035 | ((esdmode2 & 0xFFFF) << 16)
1036 | ((esdmode3 & 0xFFFF) << 0)
1040 ddr->ddr_sdram_mode_6 = (0
1041 | ((esdmode2 & 0xFFFF) << 16)
1042 | ((esdmode3 & 0xFFFF) << 0)
1046 ddr->ddr_sdram_mode_8 = (0
1047 | ((esdmode2 & 0xFFFF) << 16)
1048 | ((esdmode3 & 0xFFFF) << 0)
1053 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1054 ddr->ddr_sdram_mode_4);
1055 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1056 ddr->ddr_sdram_mode_6);
1057 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1058 ddr->ddr_sdram_mode_8);
1061 #elif defined(CONFIG_SYS_FSL_DDR3)
1062 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1063 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1064 fsl_ddr_cfg_regs_t *ddr,
1065 const memctl_options_t *popts,
1066 const common_timing_params_t *common_dimm,
1067 const unsigned int unq_mrs_en)
1069 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1070 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1072 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
1073 unsigned int srt = 0; /* self-refresh temerature, normal range */
1074 unsigned int asr = 0; /* auto self-refresh disable */
1075 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1076 unsigned int pasr = 0; /* partial array self refresh disable */
1078 if (popts->rtt_override)
1079 rtt_wr = popts->rtt_wr_override_value;
1081 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1083 if (common_dimm->extended_op_srt)
1084 srt = common_dimm->extended_op_srt;
1087 | ((rtt_wr & 0x3) << 9)
1088 | ((srt & 0x1) << 7)
1089 | ((asr & 0x1) << 6)
1090 | ((cwl & 0x7) << 3)
1091 | ((pasr & 0x7) << 0));
1092 ddr->ddr_sdram_mode_2 = (0
1093 | ((esdmode2 & 0xFFFF) << 16)
1094 | ((esdmode3 & 0xFFFF) << 0)
1096 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1098 if (unq_mrs_en) { /* unique mode registers are supported */
1099 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1100 if (popts->rtt_override)
1101 rtt_wr = popts->rtt_wr_override_value;
1103 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1105 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1106 esdmode2 |= (rtt_wr & 0x3) << 9;
1109 ddr->ddr_sdram_mode_4 = (0
1110 | ((esdmode2 & 0xFFFF) << 16)
1111 | ((esdmode3 & 0xFFFF) << 0)
1115 ddr->ddr_sdram_mode_6 = (0
1116 | ((esdmode2 & 0xFFFF) << 16)
1117 | ((esdmode3 & 0xFFFF) << 0)
1121 ddr->ddr_sdram_mode_8 = (0
1122 | ((esdmode2 & 0xFFFF) << 16)
1123 | ((esdmode3 & 0xFFFF) << 0)
1128 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1129 ddr->ddr_sdram_mode_4);
1130 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1131 ddr->ddr_sdram_mode_6);
1132 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1133 ddr->ddr_sdram_mode_8);
1137 #else /* for DDR2 and DDR1 */
1138 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1139 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1140 fsl_ddr_cfg_regs_t *ddr,
1141 const memctl_options_t *popts,
1142 const common_timing_params_t *common_dimm,
1143 const unsigned int unq_mrs_en)
1145 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1146 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1148 ddr->ddr_sdram_mode_2 = (0
1149 | ((esdmode2 & 0xFFFF) << 16)
1150 | ((esdmode3 & 0xFFFF) << 0)
1152 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1156 #ifdef CONFIG_SYS_FSL_DDR4
1157 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1158 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1159 const memctl_options_t *popts,
1160 const common_timing_params_t *common_dimm,
1161 const unsigned int unq_mrs_en)
1164 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1165 unsigned short esdmode5; /* Extended SDRAM mode 5 */
1167 bool four_cs = false;
1168 const unsigned int mclk_ps = get_memory_clk_period_ps(0);
1170 #if CONFIG_CHIP_SELECTS_PER_CTRL == 4
1171 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
1172 (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
1173 (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
1174 (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
1177 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1178 esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */
1179 rtt_park = four_cs ? 0 : 1;
1181 esdmode5 = 0x00000400; /* Data mask enabled */
1185 * For DDR3, set C/A latency if address parity is enabled.
1186 * For DDR4, set C/A latency for UDIMM only. For RDIMM the delay is
1187 * handled by register chip and RCW settings.
1189 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1190 ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1191 !popts->registered_dimm_en)) {
1192 if (mclk_ps >= 935) {
1193 /* for DDR4-1600/1866/2133 */
1194 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1195 } else if (mclk_ps >= 833) {
1197 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1199 printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1203 ddr->ddr_sdram_mode_9 = (0
1204 | ((esdmode4 & 0xffff) << 16)
1205 | ((esdmode5 & 0xffff) << 0)
1208 /* Normally only the first enabled CS use 0x500, others use 0x400
1209 * But when four chip-selects are all enabled, all mode registers
1210 * need 0x500 to park.
1213 debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9);
1214 if (unq_mrs_en) { /* unique mode registers are supported */
1215 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1217 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1218 esdmode5 |= 0x00000500; /* RTT_PARK */
1219 rtt_park = four_cs ? 0 : 1;
1221 esdmode5 = 0x00000400;
1224 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1225 ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1226 !popts->registered_dimm_en)) {
1227 if (mclk_ps >= 935) {
1228 /* for DDR4-1600/1866/2133 */
1229 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1230 } else if (mclk_ps >= 833) {
1232 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1234 printf("parity: mclk_ps = %d not supported\n",
1241 ddr->ddr_sdram_mode_11 = (0
1242 | ((esdmode4 & 0xFFFF) << 16)
1243 | ((esdmode5 & 0xFFFF) << 0)
1247 ddr->ddr_sdram_mode_13 = (0
1248 | ((esdmode4 & 0xFFFF) << 16)
1249 | ((esdmode5 & 0xFFFF) << 0)
1253 ddr->ddr_sdram_mode_15 = (0
1254 | ((esdmode4 & 0xFFFF) << 16)
1255 | ((esdmode5 & 0xFFFF) << 0)
1260 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1261 ddr->ddr_sdram_mode_11);
1262 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1263 ddr->ddr_sdram_mode_13);
1264 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1265 ddr->ddr_sdram_mode_15);
1269 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1270 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1271 fsl_ddr_cfg_regs_t *ddr,
1272 const memctl_options_t *popts,
1273 const common_timing_params_t *common_dimm,
1274 const unsigned int unq_mrs_en)
1277 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
1278 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
1279 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1281 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1283 if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1284 esdmode6 |= 1 << 6; /* Range 2 */
1286 ddr->ddr_sdram_mode_10 = (0
1287 | ((esdmode6 & 0xffff) << 16)
1288 | ((esdmode7 & 0xffff) << 0)
1290 debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10);
1291 if (unq_mrs_en) { /* unique mode registers are supported */
1292 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1295 ddr->ddr_sdram_mode_12 = (0
1296 | ((esdmode6 & 0xFFFF) << 16)
1297 | ((esdmode7 & 0xFFFF) << 0)
1301 ddr->ddr_sdram_mode_14 = (0
1302 | ((esdmode6 & 0xFFFF) << 16)
1303 | ((esdmode7 & 0xFFFF) << 0)
1307 ddr->ddr_sdram_mode_16 = (0
1308 | ((esdmode6 & 0xFFFF) << 16)
1309 | ((esdmode7 & 0xFFFF) << 0)
1314 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1315 ddr->ddr_sdram_mode_12);
1316 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1317 ddr->ddr_sdram_mode_14);
1318 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1319 ddr->ddr_sdram_mode_16);
1325 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1326 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1327 fsl_ddr_cfg_regs_t *ddr,
1328 const memctl_options_t *popts,
1329 const common_timing_params_t *common_dimm)
1331 unsigned int refint; /* Refresh interval */
1332 unsigned int bstopre; /* Precharge interval */
1334 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1336 bstopre = popts->bstopre;
1338 /* refint field used 0x3FFF in earlier controllers */
1339 ddr->ddr_sdram_interval = (0
1340 | ((refint & 0xFFFF) << 16)
1341 | ((bstopre & 0x3FFF) << 0)
1343 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1346 #ifdef CONFIG_SYS_FSL_DDR4
1347 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1348 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1349 fsl_ddr_cfg_regs_t *ddr,
1350 const memctl_options_t *popts,
1351 const common_timing_params_t *common_dimm,
1352 unsigned int cas_latency,
1353 unsigned int additive_latency,
1354 const unsigned int unq_mrs_en)
1357 unsigned short esdmode; /* Extended SDRAM mode */
1358 unsigned short sdmode; /* SDRAM mode */
1360 /* Mode Register - MR1 */
1361 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1362 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1364 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1365 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1366 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1367 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
1368 0=Disable (Test/Debug) */
1370 /* Mode Register - MR0 */
1371 unsigned int wr = 0; /* Write Recovery */
1372 unsigned int dll_rst; /* DLL Reset */
1373 unsigned int mode; /* Normal=0 or Test=1 */
1374 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1375 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1377 unsigned int bl; /* BL: Burst Length */
1379 unsigned int wr_mclk;
1380 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1381 static const u8 wr_table[] = {
1382 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1383 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1384 static const u8 cas_latency_table[] = {
1385 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1386 9, 9, 10, 10, 11, 11};
1388 if (popts->rtt_override)
1389 rtt = popts->rtt_override_value;
1391 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1393 if (additive_latency == (cas_latency - 1))
1395 if (additive_latency == (cas_latency - 2))
1398 if (popts->quad_rank_present)
1399 dic = 1; /* output driver impedance 240/7 ohm */
1402 * The esdmode value will also be used for writing
1403 * MR1 during write leveling for DDR3, although the
1404 * bits specifically related to the write leveling
1405 * scheme will be handled automatically by the DDR
1406 * controller. so we set the wrlvl_en = 0 here.
1409 | ((qoff & 0x1) << 12)
1410 | ((tdqs_en & 0x1) << 11)
1411 | ((rtt & 0x7) << 8)
1412 | ((wrlvl_en & 0x1) << 7)
1414 | ((dic & 0x3) << 1) /* DIC field is split */
1415 | ((dll_en & 0x1) << 0)
1419 * DLL control for precharge PD
1420 * 0=slow exit DLL off (tXPDLL)
1421 * 1=fast exit DLL on (tXP)
1424 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1425 if (wr_mclk <= 24) {
1426 wr = wr_table[wr_mclk - 10];
1428 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1432 dll_rst = 0; /* dll no reset */
1433 mode = 0; /* normal mode */
1435 /* look up table to get the cas latency bits */
1436 if (cas_latency >= 9 && cas_latency <= 24)
1437 caslat = cas_latency_table[cas_latency - 9];
1439 printf("Error: unsupported cas latency for mode register\n");
1441 bt = 0; /* Nibble sequential */
1443 switch (popts->burst_length) {
1454 printf("Error: invalid burst length of %u specified. ",
1455 popts->burst_length);
1456 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1463 | ((dll_rst & 0x1) << 8)
1464 | ((mode & 0x1) << 7)
1465 | (((caslat >> 1) & 0x7) << 4)
1467 | ((caslat & 1) << 2)
1471 ddr->ddr_sdram_mode = (0
1472 | ((esdmode & 0xFFFF) << 16)
1473 | ((sdmode & 0xFFFF) << 0)
1476 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1478 if (unq_mrs_en) { /* unique mode registers are supported */
1479 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1480 if (popts->rtt_override)
1481 rtt = popts->rtt_override_value;
1483 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1485 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
1486 esdmode |= (rtt & 0x7) << 8;
1489 ddr->ddr_sdram_mode_3 = (0
1490 | ((esdmode & 0xFFFF) << 16)
1491 | ((sdmode & 0xFFFF) << 0)
1495 ddr->ddr_sdram_mode_5 = (0
1496 | ((esdmode & 0xFFFF) << 16)
1497 | ((sdmode & 0xFFFF) << 0)
1501 ddr->ddr_sdram_mode_7 = (0
1502 | ((esdmode & 0xFFFF) << 16)
1503 | ((sdmode & 0xFFFF) << 0)
1508 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1509 ddr->ddr_sdram_mode_3);
1510 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1511 ddr->ddr_sdram_mode_5);
1512 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1513 ddr->ddr_sdram_mode_5);
1517 #elif defined(CONFIG_SYS_FSL_DDR3)
1518 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1519 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1520 fsl_ddr_cfg_regs_t *ddr,
1521 const memctl_options_t *popts,
1522 const common_timing_params_t *common_dimm,
1523 unsigned int cas_latency,
1524 unsigned int additive_latency,
1525 const unsigned int unq_mrs_en)
1528 unsigned short esdmode; /* Extended SDRAM mode */
1529 unsigned short sdmode; /* SDRAM mode */
1531 /* Mode Register - MR1 */
1532 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1533 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1535 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1536 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1537 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1538 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1539 1=Disable (Test/Debug) */
1541 /* Mode Register - MR0 */
1542 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
1543 unsigned int wr = 0; /* Write Recovery */
1544 unsigned int dll_rst; /* DLL Reset */
1545 unsigned int mode; /* Normal=0 or Test=1 */
1546 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1547 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1549 unsigned int bl; /* BL: Burst Length */
1551 unsigned int wr_mclk;
1553 * DDR_SDRAM_MODE doesn't support 9,11,13,15
1554 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1557 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1559 if (popts->rtt_override)
1560 rtt = popts->rtt_override_value;
1562 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1564 if (additive_latency == (cas_latency - 1))
1566 if (additive_latency == (cas_latency - 2))
1569 if (popts->quad_rank_present)
1570 dic = 1; /* output driver impedance 240/7 ohm */
1573 * The esdmode value will also be used for writing
1574 * MR1 during write leveling for DDR3, although the
1575 * bits specifically related to the write leveling
1576 * scheme will be handled automatically by the DDR
1577 * controller. so we set the wrlvl_en = 0 here.
1580 | ((qoff & 0x1) << 12)
1581 | ((tdqs_en & 0x1) << 11)
1582 | ((rtt & 0x4) << 7) /* rtt field is split */
1583 | ((wrlvl_en & 0x1) << 7)
1584 | ((rtt & 0x2) << 5) /* rtt field is split */
1585 | ((dic & 0x2) << 4) /* DIC field is split */
1587 | ((rtt & 0x1) << 2) /* rtt field is split */
1588 | ((dic & 0x1) << 1) /* DIC field is split */
1589 | ((dll_en & 0x1) << 0)
1593 * DLL control for precharge PD
1594 * 0=slow exit DLL off (tXPDLL)
1595 * 1=fast exit DLL on (tXP)
1599 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1600 if (wr_mclk <= 16) {
1601 wr = wr_table[wr_mclk - 5];
1603 printf("Error: unsupported write recovery for mode register "
1604 "wr_mclk = %d\n", wr_mclk);
1607 dll_rst = 0; /* dll no reset */
1608 mode = 0; /* normal mode */
1610 /* look up table to get the cas latency bits */
1611 if (cas_latency >= 5 && cas_latency <= 16) {
1612 unsigned char cas_latency_table[] = {
1618 0xc, /* 10 clocks */
1619 0xe, /* 11 clocks */
1620 0x1, /* 12 clocks */
1621 0x3, /* 13 clocks */
1622 0x5, /* 14 clocks */
1623 0x7, /* 15 clocks */
1624 0x9, /* 16 clocks */
1626 caslat = cas_latency_table[cas_latency - 5];
1628 printf("Error: unsupported cas latency for mode register\n");
1631 bt = 0; /* Nibble sequential */
1633 switch (popts->burst_length) {
1644 printf("Error: invalid burst length of %u specified. "
1645 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1646 popts->burst_length);
1652 | ((dll_on & 0x1) << 12)
1654 | ((dll_rst & 0x1) << 8)
1655 | ((mode & 0x1) << 7)
1656 | (((caslat >> 1) & 0x7) << 4)
1658 | ((caslat & 1) << 2)
1662 ddr->ddr_sdram_mode = (0
1663 | ((esdmode & 0xFFFF) << 16)
1664 | ((sdmode & 0xFFFF) << 0)
1667 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1669 if (unq_mrs_en) { /* unique mode registers are supported */
1670 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1671 if (popts->rtt_override)
1672 rtt = popts->rtt_override_value;
1674 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1676 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1678 | ((rtt & 0x4) << 7) /* rtt field is split */
1679 | ((rtt & 0x2) << 5) /* rtt field is split */
1680 | ((rtt & 0x1) << 2) /* rtt field is split */
1684 ddr->ddr_sdram_mode_3 = (0
1685 | ((esdmode & 0xFFFF) << 16)
1686 | ((sdmode & 0xFFFF) << 0)
1690 ddr->ddr_sdram_mode_5 = (0
1691 | ((esdmode & 0xFFFF) << 16)
1692 | ((sdmode & 0xFFFF) << 0)
1696 ddr->ddr_sdram_mode_7 = (0
1697 | ((esdmode & 0xFFFF) << 16)
1698 | ((sdmode & 0xFFFF) << 0)
1703 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1704 ddr->ddr_sdram_mode_3);
1705 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1706 ddr->ddr_sdram_mode_5);
1707 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1708 ddr->ddr_sdram_mode_5);
1712 #else /* !CONFIG_SYS_FSL_DDR3 */
1714 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1715 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1716 fsl_ddr_cfg_regs_t *ddr,
1717 const memctl_options_t *popts,
1718 const common_timing_params_t *common_dimm,
1719 unsigned int cas_latency,
1720 unsigned int additive_latency,
1721 const unsigned int unq_mrs_en)
1723 unsigned short esdmode; /* Extended SDRAM mode */
1724 unsigned short sdmode; /* SDRAM mode */
1727 * FIXME: This ought to be pre-calculated in a
1728 * technology-specific routine,
1729 * e.g. compute_DDR2_mode_register(), and then the
1730 * sdmode and esdmode passed in as part of common_dimm.
1733 /* Extended Mode Register */
1734 unsigned int mrs = 0; /* Mode Register Set */
1735 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1736 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1737 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1738 unsigned int ocd = 0; /* 0x0=OCD not supported,
1739 0x7=OCD default state */
1741 unsigned int al; /* Posted CAS# additive latency (AL) */
1742 unsigned int ods = 0; /* Output Drive Strength:
1743 0 = Full strength (18ohm)
1744 1 = Reduced strength (4ohm) */
1745 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1746 1=Disable (Test/Debug) */
1748 /* Mode Register (MR) */
1749 unsigned int mr; /* Mode Register Definition */
1750 unsigned int pd; /* Power-Down Mode */
1751 unsigned int wr; /* Write Recovery */
1752 unsigned int dll_res; /* DLL Reset */
1753 unsigned int mode; /* Normal=0 or Test=1 */
1754 unsigned int caslat = 0;/* CAS# latency */
1755 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1757 unsigned int bl; /* BL: Burst Length */
1759 dqs_en = !popts->dqs_config;
1760 rtt = fsl_ddr_get_rtt();
1762 al = additive_latency;
1765 | ((mrs & 0x3) << 14)
1766 | ((outputs & 0x1) << 12)
1767 | ((rdqs_en & 0x1) << 11)
1768 | ((dqs_en & 0x1) << 10)
1769 | ((ocd & 0x7) << 7)
1770 | ((rtt & 0x2) << 5) /* rtt field is split */
1772 | ((rtt & 0x1) << 2) /* rtt field is split */
1773 | ((ods & 0x1) << 1)
1774 | ((dll_en & 0x1) << 0)
1777 mr = 0; /* FIXME: CHECKME */
1780 * 0 = Fast Exit (Normal)
1781 * 1 = Slow Exit (Low Power)
1785 #if defined(CONFIG_SYS_FSL_DDR1)
1786 wr = 0; /* Historical */
1787 #elif defined(CONFIG_SYS_FSL_DDR2)
1788 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1793 #if defined(CONFIG_SYS_FSL_DDR1)
1794 if (1 <= cas_latency && cas_latency <= 4) {
1795 unsigned char mode_caslat_table[4] = {
1796 0x5, /* 1.5 clocks */
1797 0x2, /* 2.0 clocks */
1798 0x6, /* 2.5 clocks */
1799 0x3 /* 3.0 clocks */
1801 caslat = mode_caslat_table[cas_latency - 1];
1803 printf("Warning: unknown cas_latency %d\n", cas_latency);
1805 #elif defined(CONFIG_SYS_FSL_DDR2)
1806 caslat = cas_latency;
1810 switch (popts->burst_length) {
1818 printf("Error: invalid burst length of %u specified. "
1819 " Defaulting to 4 beats.\n",
1820 popts->burst_length);
1826 | ((mr & 0x3) << 14)
1827 | ((pd & 0x1) << 12)
1829 | ((dll_res & 0x1) << 8)
1830 | ((mode & 0x1) << 7)
1831 | ((caslat & 0x7) << 4)
1836 ddr->ddr_sdram_mode = (0
1837 | ((esdmode & 0xFFFF) << 16)
1838 | ((sdmode & 0xFFFF) << 0)
1840 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1844 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1845 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1847 unsigned int init_value; /* Initialization value */
1849 #ifdef CONFIG_MEM_INIT_VALUE
1850 init_value = CONFIG_MEM_INIT_VALUE;
1852 init_value = 0xDEADBEEF;
1854 ddr->ddr_data_init = init_value;
1858 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1859 * The old controller on the 8540/60 doesn't have this register.
1860 * Hope it's OK to set it (to 0) anyway.
1862 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1863 const memctl_options_t *popts)
1865 unsigned int clk_adjust; /* Clock adjust */
1866 unsigned int ss_en = 0; /* Source synchronous enable */
1868 #if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
1869 /* Per FSL Application Note: AN2805 */
1872 if (fsl_ddr_get_version(0) >= 0x40701) {
1873 /* clk_adjust in 5-bits on T-series and LS-series */
1874 clk_adjust = (popts->clk_adjust & 0x1F) << 22;
1876 /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
1877 clk_adjust = (popts->clk_adjust & 0xF) << 23;
1880 ddr->ddr_sdram_clk_cntl = (0
1881 | ((ss_en & 0x1) << 31)
1884 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1887 /* DDR Initialization Address (DDR_INIT_ADDR) */
1888 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1890 unsigned int init_addr = 0; /* Initialization address */
1892 ddr->ddr_init_addr = init_addr;
1895 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1896 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1898 unsigned int uia = 0; /* Use initialization address */
1899 unsigned int init_ext_addr = 0; /* Initialization address */
1901 ddr->ddr_init_ext_addr = (0
1902 | ((uia & 0x1) << 31)
1903 | (init_ext_addr & 0xF)
1907 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1908 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1909 const memctl_options_t *popts)
1911 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1912 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1913 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1914 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1915 unsigned int trwt_mclk = 0; /* ext_rwt */
1916 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1918 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1919 if (popts->burst_length == DDR_BL8) {
1920 /* We set BL/2 for fixed BL8 */
1921 rrt = 0; /* BL/2 clocks */
1922 wwt = 0; /* BL/2 clocks */
1924 /* We need to set BL/2 + 2 to BC4 and OTF */
1925 rrt = 2; /* BL/2 + 2 clocks */
1926 wwt = 2; /* BL/2 + 2 clocks */
1929 #ifdef CONFIG_SYS_FSL_DDR4
1930 dll_lock = 2; /* tDLLK = 1024 clocks */
1931 #elif defined(CONFIG_SYS_FSL_DDR3)
1932 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1935 if (popts->trwt_override)
1936 trwt_mclk = popts->trwt;
1938 ddr->timing_cfg_4 = (0
1939 | ((rwt & 0xf) << 28)
1940 | ((wrt & 0xf) << 24)
1941 | ((rrt & 0xf) << 20)
1942 | ((wwt & 0xf) << 16)
1943 | ((trwt_mclk & 0xc) << 12)
1946 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1949 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1950 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1952 unsigned int rodt_on = 0; /* Read to ODT on */
1953 unsigned int rodt_off = 0; /* Read to ODT off */
1954 unsigned int wodt_on = 0; /* Write to ODT on */
1955 unsigned int wodt_off = 0; /* Write to ODT off */
1957 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1958 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1959 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1960 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1961 if (cas_latency >= wr_lat)
1962 rodt_on = cas_latency - wr_lat + 1;
1963 rodt_off = 4; /* 4 clocks */
1964 wodt_on = 1; /* 1 clocks */
1965 wodt_off = 4; /* 4 clocks */
1968 ddr->timing_cfg_5 = (0
1969 | ((rodt_on & 0x1f) << 24)
1970 | ((rodt_off & 0x7) << 20)
1971 | ((wodt_on & 0x1f) << 12)
1972 | ((wodt_off & 0x7) << 8)
1974 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1977 #ifdef CONFIG_SYS_FSL_DDR4
1978 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1980 unsigned int hs_caslat = 0;
1981 unsigned int hs_wrlat = 0;
1982 unsigned int hs_wrrec = 0;
1983 unsigned int hs_clkadj = 0;
1984 unsigned int hs_wrlvl_start = 0;
1986 ddr->timing_cfg_6 = (0
1987 | ((hs_caslat & 0x1f) << 24)
1988 | ((hs_wrlat & 0x1f) << 19)
1989 | ((hs_wrrec & 0x1f) << 12)
1990 | ((hs_clkadj & 0x1f) << 6)
1991 | ((hs_wrlvl_start & 0x1f) << 0)
1993 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1996 static void set_timing_cfg_7(const unsigned int ctrl_num,
1997 fsl_ddr_cfg_regs_t *ddr,
1998 const memctl_options_t *popts,
1999 const common_timing_params_t *common_dimm)
2001 unsigned int txpr, tcksre, tcksrx;
2002 unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
2003 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
2005 txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
2006 tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
2007 tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
2009 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN &&
2010 CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
2012 par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1;
2013 debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps);
2020 else if (txpr <= 256)
2022 else if (txpr <= 512)
2037 ddr->timing_cfg_7 = (0
2038 | ((cke_rst & 0x3) << 28)
2039 | ((cksre & 0xf) << 24)
2040 | ((cksrx & 0xf) << 20)
2041 | ((par_lat & 0xf) << 16)
2042 | ((cs_to_cmd & 0xf) << 4)
2044 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
2047 static void set_timing_cfg_8(const unsigned int ctrl_num,
2048 fsl_ddr_cfg_regs_t *ddr,
2049 const memctl_options_t *popts,
2050 const common_timing_params_t *common_dimm,
2051 unsigned int cas_latency)
2053 int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
2054 unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
2055 int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
2056 int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
2057 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
2059 rwt_bg = cas_latency + 2 + 4 - wr_lat;
2061 rwt_bg = tccdl - rwt_bg;
2065 wrt_bg = wr_lat + 4 + 1 - cas_latency;
2067 wrt_bg = tccdl - wrt_bg;
2071 if (popts->burst_length == DDR_BL8) {
2079 acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
2080 wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
2081 if (popts->otf_burst_chop_en)
2086 ddr->timing_cfg_8 = (0
2087 | ((rwt_bg & 0xf) << 28)
2088 | ((wrt_bg & 0xf) << 24)
2089 | ((rrt_bg & 0xf) << 20)
2090 | ((wwt_bg & 0xf) << 16)
2091 | ((acttoact_bg & 0xf) << 12)
2092 | ((wrtord_bg & 0xf) << 8)
2093 | ((pre_all_rec & 0x1f) << 0)
2096 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
2099 static void set_timing_cfg_9(const unsigned int ctrl_num,
2100 fsl_ddr_cfg_regs_t *ddr,
2101 const memctl_options_t *popts,
2102 const common_timing_params_t *common_dimm)
2104 unsigned int refrec_cid_mclk = 0;
2105 unsigned int acttoact_cid_mclk = 0;
2107 if (popts->package_3ds) {
2109 picos_to_mclk(ctrl_num, common_dimm->trfc_slr_ps);
2110 acttoact_cid_mclk = 4U; /* tRRDS_slr */
2113 ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16 |
2114 (acttoact_cid_mclk & 0xf) << 8;
2116 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
2119 /* This function needs to be called after set_ddr_sdram_cfg() is called */
2120 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
2121 const dimm_params_t *dimm_params)
2123 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
2126 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
2127 if (dimm_params[i].n_ranks)
2130 if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
2131 puts("DDR error: no DIMM found!\n");
2135 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2136 ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2137 ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2138 ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2139 ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
2141 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2142 ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2143 ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2144 ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2145 ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
2147 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2148 ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2149 ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2150 ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2151 ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
2153 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
2154 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2155 ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
2157 (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2158 dimm_params[i].dq_mapping_ors;
2160 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2161 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2162 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2163 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2165 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2166 const memctl_options_t *popts)
2170 rd_pre = popts->quad_rank_present ? 1 : 0;
2172 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2173 /* Disable MRS on parity error for RDIMMs */
2174 ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0;
2176 if (popts->package_3ds) { /* only 2,4,8 are supported */
2177 if ((popts->package_3ds + 1) & 0x1) {
2178 printf("Error: Unsupported 3DS DIMM with %d die\n",
2179 popts->package_3ds + 1);
2181 ddr->ddr_sdram_cfg_3 |= ((popts->package_3ds + 1) >> 1)
2186 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2188 #endif /* CONFIG_SYS_FSL_DDR4 */
2190 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2191 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2193 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2194 /* Normal Operation Full Calibration Time (tZQoper) */
2195 unsigned int zqoper = 0;
2196 /* Normal Operation Short Calibration Time (tZQCS) */
2197 unsigned int zqcs = 0;
2198 #ifdef CONFIG_SYS_FSL_DDR4
2199 unsigned int zqcs_init;
2203 #ifdef CONFIG_SYS_FSL_DDR4
2204 zqinit = 10; /* 1024 clocks */
2205 zqoper = 9; /* 512 clocks */
2206 zqcs = 7; /* 128 clocks */
2207 zqcs_init = 5; /* 1024 refresh sequences */
2209 zqinit = 9; /* 512 clocks */
2210 zqoper = 8; /* 256 clocks */
2211 zqcs = 6; /* 64 clocks */
2215 ddr->ddr_zq_cntl = (0
2216 | ((zq_en & 0x1) << 31)
2217 | ((zqinit & 0xF) << 24)
2218 | ((zqoper & 0xF) << 16)
2219 | ((zqcs & 0xF) << 8)
2220 #ifdef CONFIG_SYS_FSL_DDR4
2221 | ((zqcs_init & 0xF) << 0)
2224 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2227 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2228 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2229 const memctl_options_t *popts)
2232 * First DQS pulse rising edge after margining mode
2233 * is programmed (tWL_MRD)
2235 unsigned int wrlvl_mrd = 0;
2236 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2237 unsigned int wrlvl_odten = 0;
2238 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2239 unsigned int wrlvl_dqsen = 0;
2240 /* WRLVL_SMPL: Write leveling sample time */
2241 unsigned int wrlvl_smpl = 0;
2242 /* WRLVL_WLR: Write leveling repeition time */
2243 unsigned int wrlvl_wlr = 0;
2244 /* WRLVL_START: Write leveling start time */
2245 unsigned int wrlvl_start = 0;
2247 /* suggest enable write leveling for DDR3 due to fly-by topology */
2249 /* tWL_MRD min = 40 nCK, we set it 64 */
2253 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2256 * Write leveling sample time at least need 6 clocks
2257 * higher than tWLO to allow enough time for progagation
2258 * delay and sampling the prime data bits.
2262 * Write leveling repetition time
2263 * at least tWLO + 6 clocks clocks
2268 * Write leveling start time
2269 * The value use for the DQS_ADJUST for the first sample
2270 * when write leveling is enabled. It probably needs to be
2271 * overridden per platform.
2275 * Override the write leveling sample and start time
2276 * according to specific board
2278 if (popts->wrlvl_override) {
2279 wrlvl_smpl = popts->wrlvl_sample;
2280 wrlvl_start = popts->wrlvl_start;
2284 ddr->ddr_wrlvl_cntl = (0
2285 | ((wrlvl_en & 0x1) << 31)
2286 | ((wrlvl_mrd & 0x7) << 24)
2287 | ((wrlvl_odten & 0x7) << 20)
2288 | ((wrlvl_dqsen & 0x7) << 16)
2289 | ((wrlvl_smpl & 0xf) << 12)
2290 | ((wrlvl_wlr & 0x7) << 8)
2291 | ((wrlvl_start & 0x1F) << 0)
2293 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2294 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2295 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2296 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2297 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2301 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2302 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2304 /* Self Refresh Idle Threshold */
2305 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2308 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2310 if (popts->addr_hash) {
2311 ddr->ddr_eor = 0x40000000; /* address hash enable */
2312 puts("Address hashing enabled.\n");
2316 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2318 ddr->ddr_cdr1 = popts->ddr_cdr1;
2319 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2322 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2324 ddr->ddr_cdr2 = popts->ddr_cdr2;
2325 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2329 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2331 unsigned int res = 0;
2334 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2335 * not set at the same time.
2337 if (ddr->ddr_sdram_cfg & 0x10000000
2338 && ddr->ddr_sdram_cfg & 0x00008000) {
2339 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2340 " should not be set at the same time.\n");
2348 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2349 const memctl_options_t *popts,
2350 fsl_ddr_cfg_regs_t *ddr,
2351 const common_timing_params_t *common_dimm,
2352 const dimm_params_t *dimm_params,
2353 unsigned int dbw_cap_adj,
2354 unsigned int size_only)
2357 unsigned int cas_latency;
2358 unsigned int additive_latency;
2361 unsigned int wrlvl_en;
2362 unsigned int ip_rev = 0;
2363 unsigned int unq_mrs_en = 0;
2365 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2366 unsigned int ddr_freq;
2368 #if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
2369 defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
2370 defined(CONFIG_SYS_FSL_ERRATUM_A009942)
2371 struct ccsr_ddr __iomem *ddrc;
2375 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
2377 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
2379 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
2382 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
2384 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
2387 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
2389 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
2393 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
2398 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2400 if (common_dimm == NULL) {
2401 printf("Error: subset DIMM params struct null pointer\n");
2406 * Process overrides first.
2408 * FIXME: somehow add dereated caslat to this
2410 cas_latency = (popts->cas_latency_override)
2411 ? popts->cas_latency_override_value
2412 : common_dimm->lowest_common_spd_caslat;
2414 additive_latency = (popts->additive_latency_override)
2415 ? popts->additive_latency_override_value
2416 : common_dimm->additive_latency;
2418 sr_it = (popts->auto_self_refresh_en)
2421 /* ZQ calibration */
2422 zq_en = (popts->zq_en) ? 1 : 0;
2423 /* write leveling */
2424 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2426 /* Chip Select Memory Bounds (CSn_BNDS) */
2427 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2428 unsigned long long ea, sa;
2429 unsigned int cs_per_dimm
2430 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2431 unsigned int dimm_number
2433 unsigned long long rank_density
2434 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2436 if (dimm_params[dimm_number].n_ranks == 0) {
2437 debug("Skipping setup of CS%u "
2438 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2441 if (popts->memctl_interleaving) {
2442 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2443 case FSL_DDR_CS0_CS1_CS2_CS3:
2445 case FSL_DDR_CS0_CS1:
2446 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2450 case FSL_DDR_CS2_CS3:
2456 sa = common_dimm->base_address;
2457 ea = sa + common_dimm->total_mem - 1;
2458 } else if (!popts->memctl_interleaving) {
2460 * If memory interleaving between controllers is NOT
2461 * enabled, the starting address for each memory
2462 * controller is distinct. However, because rank
2463 * interleaving is enabled, the starting and ending
2464 * addresses of the total memory on that memory
2465 * controller needs to be programmed into its
2466 * respective CS0_BNDS.
2468 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2469 case FSL_DDR_CS0_CS1_CS2_CS3:
2470 sa = common_dimm->base_address;
2471 ea = sa + common_dimm->total_mem - 1;
2473 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2474 if ((i >= 2) && (dimm_number == 0)) {
2475 sa = dimm_params[dimm_number].base_address +
2477 ea = sa + 2 * rank_density - 1;
2479 sa = dimm_params[dimm_number].base_address;
2480 ea = sa + 2 * rank_density - 1;
2483 case FSL_DDR_CS0_CS1:
2484 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2485 sa = dimm_params[dimm_number].base_address;
2486 ea = sa + rank_density - 1;
2488 sa += (i % cs_per_dimm) * rank_density;
2489 ea += (i % cs_per_dimm) * rank_density;
2497 case FSL_DDR_CS2_CS3:
2498 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2499 sa = dimm_params[dimm_number].base_address;
2500 ea = sa + rank_density - 1;
2502 sa += (i % cs_per_dimm) * rank_density;
2503 ea += (i % cs_per_dimm) * rank_density;
2509 ea += (rank_density >> dbw_cap_adj);
2511 default: /* No bank(chip-select) interleaving */
2512 sa = dimm_params[dimm_number].base_address;
2513 ea = sa + rank_density - 1;
2514 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2515 sa += (i % cs_per_dimm) * rank_density;
2516 ea += (i % cs_per_dimm) * rank_density;
2529 ddr->cs[i].bnds = (0
2530 | ((sa & 0xffff) << 16) /* starting address */
2531 | ((ea & 0xffff) << 0) /* ending address */
2534 /* setting bnds to 0xffffffff for inactive CS */
2535 ddr->cs[i].bnds = 0xffffffff;
2538 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2539 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2540 set_csn_config_2(i, ddr);
2544 * In the case we only need to compute the ddr sdram size, we only need
2545 * to set csn registers, so return from here.
2550 set_ddr_eor(ddr, popts);
2552 #if !defined(CONFIG_SYS_FSL_DDR1)
2553 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2556 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2558 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2559 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2560 cas_latency, additive_latency);
2562 set_ddr_cdr1(ddr, popts);
2563 set_ddr_cdr2(ddr, popts);
2564 set_ddr_sdram_cfg(ddr, popts, common_dimm);
2565 ip_rev = fsl_ddr_get_version(ctrl_num);
2566 if (ip_rev > 0x40400)
2569 if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2570 ddr->debug[18] = popts->cswl_override;
2572 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2573 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2574 cas_latency, additive_latency, unq_mrs_en);
2575 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2576 #ifdef CONFIG_SYS_FSL_DDR4
2577 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2578 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2580 set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm);
2582 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2583 set_ddr_data_init(ddr);
2584 set_ddr_sdram_clk_cntl(ddr, popts);
2585 set_ddr_init_addr(ddr);
2586 set_ddr_init_ext_addr(ddr);
2587 set_timing_cfg_4(ddr, popts);
2588 set_timing_cfg_5(ddr, cas_latency);
2589 #ifdef CONFIG_SYS_FSL_DDR4
2590 set_ddr_sdram_cfg_3(ddr, popts);
2591 set_timing_cfg_6(ddr);
2592 set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm);
2593 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2594 set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm);
2595 set_ddr_dq_mapping(ddr, dimm_params);
2598 set_ddr_zq_cntl(ddr, zq_en);
2599 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2601 set_ddr_sr_cntr(ddr, sr_it);
2603 #ifdef CONFIG_SYS_FSL_DDR_EMU
2604 /* disble DDR training for emulator */
2605 ddr->debug[2] = 0x00000400;
2606 ddr->debug[4] = 0xff800800;
2607 ddr->debug[5] = 0x08000800;
2608 ddr->debug[6] = 0x08000800;
2609 ddr->debug[7] = 0x08000800;
2610 ddr->debug[8] = 0x08000800;
2612 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2613 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2614 ddr->debug[2] |= 0x00000200; /* set bit 22 */
2617 #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
2618 /* Erratum applies when accumulated ECC is used, or DBI is enabled */
2619 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
2620 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
2621 if (has_erratum_a008378()) {
2622 if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
2623 IS_DBI(ddr->ddr_sdram_cfg_3)) {
2624 ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
2625 ddr->debug[28] |= (0x9 << 20);
2630 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2631 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
2632 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
2633 ddr->debug[28] &= 0xff0fff00;
2634 if (ddr_freq <= 1333)
2635 ddr->debug[28] |= 0x0080006a;
2636 else if (ddr_freq <= 1600)
2637 ddr->debug[28] |= 0x0070006f;
2638 else if (ddr_freq <= 1867)
2639 ddr->debug[28] |= 0x00700076;
2640 else if (ddr_freq <= 2133)
2641 ddr->debug[28] |= 0x0060007b;
2642 if (popts->cpo_sample)
2643 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
2647 return check_fsl_memctl_config_regs(ddr);
2650 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2652 * This additional workaround of A009942 checks the condition to determine if
2653 * the CPO value set by the existing A009942 workaround needs to be updated.
2654 * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
2655 * expected optimal value, the optimal value is highly board dependent.
2657 void erratum_a009942_check_cpo(void)
2659 struct ccsr_ddr __iomem *ddr =
2660 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
2661 u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
2662 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
2663 u32 cpo_max = cpo_min;
2664 u32 sdram_cfg, i, tmp, lanes, ddr_type;
2665 bool update_cpo = false, has_ecc = false;
2667 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
2668 if (sdram_cfg & SDRAM_CFG_32_BE)
2670 else if (sdram_cfg & SDRAM_CFG_16_BE)
2675 if (sdram_cfg & SDRAM_CFG_ECC_EN)
2678 /* determine the maximum and minimum CPO values */
2679 for (i = 9; i < 9 + lanes / 2; i++) {
2680 cpo = ddr_in32(&ddr->debug[i]);
2682 cpo_o = (cpo >> 8) & 0xff;
2683 tmp = min(cpo_e, cpo_o);
2686 tmp = max(cpo_e, cpo_o);
2692 cpo = ddr_in32(&ddr->debug[13]);
2700 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
2701 cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
2702 debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
2704 debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
2706 ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
2707 SDRAM_CFG_SDRAM_TYPE_SHIFT;
2708 if (ddr_type == SDRAM_TYPE_DDR4)
2709 update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
2710 else if (ddr_type == SDRAM_TYPE_DDR3)
2711 update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
2714 printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
2715 printf("in <board>/ddr.c to optimize cpo\n");