2 * Copyright 2008-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017-2018 NXP Semiconductor
5 * SPDX-License-Identifier: GPL-2.0+
9 * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
10 * Based on code from spd_sdram.c
11 * Author: James Yang [at freescale.com]
15 #include <fsl_ddr_sdram.h>
16 #include <fsl_errata.h>
18 #include <fsl_immap.h>
20 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
22 #include <asm/arch/clock.h>
26 * Determine Rtt value.
28 * This should likely be either board or controller specific.
30 * Rtt(nominal) - DDR2:
35 * Rtt(nominal) - DDR3:
43 * FIXME: Apparently 8641 needs a value of 2
44 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
46 * FIXME: There was some effort down this line earlier:
49 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
50 * if (popts->dimmslot[i].num_valid_cs
51 * && (popts->cs_local_opts[2*i].odt_rd_cfg
52 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
58 static inline int fsl_ddr_get_rtt(void)
62 #if defined(CONFIG_SYS_FSL_DDR1)
64 #elif defined(CONFIG_SYS_FSL_DDR2)
73 #ifdef CONFIG_SYS_FSL_DDR4
75 * compute CAS write latency according to DDR4 spec
76 * CWL = 9 for <= 1600MT/s
84 static inline unsigned int compute_cas_write_latency(
85 const unsigned int ctrl_num)
88 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
91 else if (mclk_ps >= 1070)
93 else if (mclk_ps >= 935)
95 else if (mclk_ps >= 833)
97 else if (mclk_ps >= 750)
99 else if (mclk_ps >= 681)
108 * compute the CAS write latency according to DDR3 spec
109 * CWL = 5 if tCK >= 2.5ns
110 * 6 if 2.5ns > tCK >= 1.875ns
111 * 7 if 1.875ns > tCK >= 1.5ns
112 * 8 if 1.5ns > tCK >= 1.25ns
113 * 9 if 1.25ns > tCK >= 1.07ns
114 * 10 if 1.07ns > tCK >= 0.935ns
115 * 11 if 0.935ns > tCK >= 0.833ns
116 * 12 if 0.833ns > tCK >= 0.75ns
118 static inline unsigned int compute_cas_write_latency(
119 const unsigned int ctrl_num)
122 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
126 else if (mclk_ps >= 1875)
128 else if (mclk_ps >= 1500)
130 else if (mclk_ps >= 1250)
132 else if (mclk_ps >= 1070)
134 else if (mclk_ps >= 935)
136 else if (mclk_ps >= 833)
138 else if (mclk_ps >= 750)
142 printf("Warning: CWL is out of range\n");
148 /* Chip Select Configuration (CSn_CONFIG) */
149 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
150 const memctl_options_t *popts,
151 const dimm_params_t *dimm_params)
153 unsigned int cs_n_en = 0; /* Chip Select enable */
154 unsigned int intlv_en = 0; /* Memory controller interleave enable */
155 unsigned int intlv_ctl = 0; /* Interleaving control */
156 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
157 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
158 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
159 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
160 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
161 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
163 #ifdef CONFIG_SYS_FSL_DDR4
164 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
166 unsigned int n_banks_per_sdram_device;
169 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
172 if (dimm_params[dimm_number].n_ranks > 0) {
174 /* These fields only available in CS0_CONFIG */
175 if (!popts->memctl_interleaving)
177 switch (popts->memctl_interleaving_mode) {
178 case FSL_DDR_256B_INTERLEAVING:
179 case FSL_DDR_CACHE_LINE_INTERLEAVING:
180 case FSL_DDR_PAGE_INTERLEAVING:
181 case FSL_DDR_BANK_INTERLEAVING:
182 case FSL_DDR_SUPERBANK_INTERLEAVING:
183 intlv_en = popts->memctl_interleaving;
184 intlv_ctl = popts->memctl_interleaving_mode;
192 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
193 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
197 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
198 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
202 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
203 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
204 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
212 ap_n_en = popts->cs_local_opts[i].auto_precharge;
213 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
214 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
215 #ifdef CONFIG_SYS_FSL_DDR4
216 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
217 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
219 n_banks_per_sdram_device
220 = dimm_params[dimm_number].n_banks_per_sdram_device;
221 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
223 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
224 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
226 ddr->cs[i].config = (0
227 | ((cs_n_en & 0x1) << 31)
228 | ((intlv_en & 0x3) << 29)
229 | ((intlv_ctl & 0xf) << 24)
230 | ((ap_n_en & 0x1) << 23)
232 /* XXX: some implementation only have 1 bit starting at left */
233 | ((odt_rd_cfg & 0x7) << 20)
235 /* XXX: Some implementation only have 1 bit starting at left */
236 | ((odt_wr_cfg & 0x7) << 16)
238 | ((ba_bits_cs_n & 0x3) << 14)
239 | ((row_bits_cs_n & 0x7) << 8)
240 #ifdef CONFIG_SYS_FSL_DDR4
241 | ((bg_bits_cs_n & 0x3) << 4)
243 | ((col_bits_cs_n & 0x7) << 0)
245 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
248 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
250 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
252 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
254 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
255 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
258 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
260 #if !defined(CONFIG_SYS_FSL_DDR1)
262 * Check DIMM configuration, return 2 if quad-rank or two dual-rank
263 * Return 1 if other two slots configuration. Return 0 if single slot.
265 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
267 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
268 if (dimm_params[0].n_ranks == 4)
272 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
273 if ((dimm_params[0].n_ranks == 2) &&
274 (dimm_params[1].n_ranks == 2))
277 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
278 if (dimm_params[0].n_ranks == 4)
282 if ((dimm_params[0].n_ranks != 0) &&
283 (dimm_params[2].n_ranks != 0))
290 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
292 * Avoid writing for DDR I. The new PQ38 DDR controller
293 * dreams up non-zero default values to be backwards compatible.
295 static void set_timing_cfg_0(const unsigned int ctrl_num,
296 fsl_ddr_cfg_regs_t *ddr,
297 const memctl_options_t *popts,
298 const dimm_params_t *dimm_params)
300 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
301 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
302 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
303 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
304 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
306 /* Active powerdown exit timing (tXARD and tXARDS). */
307 unsigned char act_pd_exit_mclk;
308 /* Precharge powerdown exit timing (tXP). */
309 unsigned char pre_pd_exit_mclk;
310 /* ODT powerdown exit timing (tAXPD). */
311 unsigned char taxpd_mclk = 0;
312 /* Mode register set cycle time (tMRD). */
313 unsigned char tmrd_mclk;
314 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
315 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
318 #ifdef CONFIG_SYS_FSL_DDR4
319 /* tXP=max(4nCK, 6ns) */
320 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
321 unsigned int data_rate = get_ddr_freq(ctrl_num);
323 /* for faster clock, need more time for data setup */
324 trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
327 * for single quad-rank DIMM and two-slot DIMMs
328 * to avoid ODT overlap
330 switch (avoid_odt_overlap(dimm_params)) {
343 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
344 pre_pd_exit_mclk = act_pd_exit_mclk;
346 * MRS_CYC = max(tMRD, tMOD)
347 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
349 tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
350 #elif defined(CONFIG_SYS_FSL_DDR3)
351 unsigned int data_rate = get_ddr_freq(ctrl_num);
356 * (tXARD and tXARDS). Empirical?
357 * The DDR3 spec has not tXARD,
358 * we use the tXP instead of it.
359 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
360 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
361 * spec has not the tAXPD, we use
362 * tAXPD=1, need design to confirm.
364 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
366 ip_rev = fsl_ddr_get_version(ctrl_num);
367 if (ip_rev >= 0x40700) {
369 * MRS_CYC = max(tMRD, tMOD)
370 * tMRD = 4nCK (8nCK for RDIMM)
371 * tMOD = max(12nCK, 15ns)
373 tmrd_mclk = max((unsigned int)12,
374 picos_to_mclk(ctrl_num, 15000));
378 * tMRD = 4nCK (8nCK for RDIMM)
380 if (popts->registered_dimm_en)
386 /* set the turnaround time */
389 * for single quad-rank DIMM and two-slot DIMMs
390 * to avoid ODT overlap
392 odt_overlap = avoid_odt_overlap(dimm_params);
393 switch (odt_overlap) {
406 /* for faster clock, need more time for data setup */
407 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
409 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
412 if (popts->dynamic_power == 0) { /* powerdown is not used */
413 act_pd_exit_mclk = 1;
414 pre_pd_exit_mclk = 1;
417 /* act_pd_exit_mclk = tXARD, see above */
418 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
419 /* Mode register MR0[A12] is '1' - fast exit */
420 pre_pd_exit_mclk = act_pd_exit_mclk;
423 #else /* CONFIG_SYS_FSL_DDR2 */
425 * (tXARD and tXARDS). Empirical?
430 act_pd_exit_mclk = 2;
431 pre_pd_exit_mclk = 2;
436 if (popts->trwt_override)
437 trwt_mclk = popts->trwt;
439 ddr->timing_cfg_0 = (0
440 | ((trwt_mclk & 0x3) << 30) /* RWT */
441 | ((twrt_mclk & 0x3) << 28) /* WRT */
442 | ((trrt_mclk & 0x3) << 26) /* RRT */
443 | ((twwt_mclk & 0x3) << 24) /* WWT */
444 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
445 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
446 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
447 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
449 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
451 #endif /* !defined(CONFIG_SYS_FSL_DDR1) */
453 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
454 static void set_timing_cfg_3(const unsigned int ctrl_num,
455 fsl_ddr_cfg_regs_t *ddr,
456 const memctl_options_t *popts,
457 const common_timing_params_t *common_dimm,
458 unsigned int cas_latency,
459 unsigned int additive_latency)
461 /* Extended precharge to activate interval (tRP) */
462 unsigned int ext_pretoact = 0;
463 /* Extended Activate to precharge interval (tRAS) */
464 unsigned int ext_acttopre = 0;
465 /* Extended activate to read/write interval (tRCD) */
466 unsigned int ext_acttorw = 0;
467 /* Extended refresh recovery time (tRFC) */
468 unsigned int ext_refrec;
469 /* Extended MCAS latency from READ cmd */
470 unsigned int ext_caslat = 0;
471 /* Extended additive latency */
472 unsigned int ext_add_lat = 0;
473 /* Extended last data to precharge interval (tWR) */
474 unsigned int ext_wrrec = 0;
476 unsigned int cntl_adj = 0;
478 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
479 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
480 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
481 ext_caslat = (2 * cas_latency - 1) >> 4;
482 ext_add_lat = additive_latency >> 4;
483 #ifdef CONFIG_SYS_FSL_DDR4
484 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
486 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
487 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
489 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
490 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
492 ddr->timing_cfg_3 = (0
493 | ((ext_pretoact & 0x1) << 28)
494 | ((ext_acttopre & 0x3) << 24)
495 | ((ext_acttorw & 0x1) << 22)
496 | ((ext_refrec & 0x3F) << 16)
497 | ((ext_caslat & 0x3) << 12)
498 | ((ext_add_lat & 0x1) << 10)
499 | ((ext_wrrec & 0x1) << 8)
500 | ((cntl_adj & 0x7) << 0)
502 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
505 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
506 static void set_timing_cfg_1(const unsigned int ctrl_num,
507 fsl_ddr_cfg_regs_t *ddr,
508 const memctl_options_t *popts,
509 const common_timing_params_t *common_dimm,
510 unsigned int cas_latency)
512 /* Precharge-to-activate interval (tRP) */
513 unsigned char pretoact_mclk;
514 /* Activate to precharge interval (tRAS) */
515 unsigned char acttopre_mclk;
516 /* Activate to read/write interval (tRCD) */
517 unsigned char acttorw_mclk;
519 unsigned char caslat_ctrl;
520 /* Refresh recovery time (tRFC) ; trfc_low */
521 unsigned char refrec_ctrl;
522 /* Last data to precharge minimum interval (tWR) */
523 unsigned char wrrec_mclk;
524 /* Activate-to-activate interval (tRRD) */
525 unsigned char acttoact_mclk;
526 /* Last write data pair to read command issue interval (tWTR) */
527 unsigned char wrtord_mclk;
528 #ifdef CONFIG_SYS_FSL_DDR4
529 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
530 static const u8 wrrec_table[] = {
537 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
538 static const u8 wrrec_table[] = {
539 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
542 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
543 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
544 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
547 * Translate CAS Latency to a DDR controller field value:
549 * CAS Lat DDR I DDR II Ctrl
550 * Clocks SPD Bit SPD Bit Value
551 * ------- ------- ------- -----
562 #if defined(CONFIG_SYS_FSL_DDR1)
563 caslat_ctrl = (cas_latency + 1) & 0x07;
564 #elif defined(CONFIG_SYS_FSL_DDR2)
565 caslat_ctrl = 2 * cas_latency - 1;
568 * if the CAS latency more than 8 cycle,
569 * we need set extend bit for it at
570 * TIMING_CFG_3[EXT_CASLAT]
572 if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
573 caslat_ctrl = 2 * cas_latency - 1;
575 caslat_ctrl = (cas_latency - 1) << 1;
578 #ifdef CONFIG_SYS_FSL_DDR4
579 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
580 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
581 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
582 wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
583 if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
584 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
586 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
588 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
589 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
590 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
591 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
592 if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
593 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
595 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
597 if (popts->otf_burst_chop_en)
601 * JEDEC has min requirement for tRRD
603 #if defined(CONFIG_SYS_FSL_DDR3)
604 if (acttoact_mclk < 4)
608 * JEDEC has some min requirements for tWTR
610 #if defined(CONFIG_SYS_FSL_DDR2)
613 #elif defined(CONFIG_SYS_FSL_DDR3)
617 if (popts->otf_burst_chop_en)
620 ddr->timing_cfg_1 = (0
621 | ((pretoact_mclk & 0x0F) << 28)
622 | ((acttopre_mclk & 0x0F) << 24)
623 | ((acttorw_mclk & 0xF) << 20)
624 | ((caslat_ctrl & 0xF) << 16)
625 | ((refrec_ctrl & 0xF) << 12)
626 | ((wrrec_mclk & 0x0F) << 8)
627 | ((acttoact_mclk & 0x0F) << 4)
628 | ((wrtord_mclk & 0x0F) << 0)
630 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
633 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
634 static void set_timing_cfg_2(const unsigned int ctrl_num,
635 fsl_ddr_cfg_regs_t *ddr,
636 const memctl_options_t *popts,
637 const common_timing_params_t *common_dimm,
638 unsigned int cas_latency,
639 unsigned int additive_latency)
641 /* Additive latency */
642 unsigned char add_lat_mclk;
643 /* CAS-to-preamble override */
646 unsigned char wr_lat;
647 /* Read to precharge (tRTP) */
648 unsigned char rd_to_pre;
649 /* Write command to write data strobe timing adjustment */
650 unsigned char wr_data_delay;
651 /* Minimum CKE pulse width (tCKE) */
652 unsigned char cke_pls;
653 /* Window for four activates (tFAW) */
654 unsigned short four_act;
655 #ifdef CONFIG_SYS_FSL_DDR3
656 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
659 /* FIXME add check that this must be less than acttorw_mclk */
660 add_lat_mclk = additive_latency;
661 cpo = popts->cpo_override;
663 #if defined(CONFIG_SYS_FSL_DDR1)
665 * This is a lie. It should really be 1, but if it is
666 * set to 1, bits overlap into the old controller's
667 * otherwise unused ACSM field. If we leave it 0, then
668 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
671 #elif defined(CONFIG_SYS_FSL_DDR2)
672 wr_lat = cas_latency - 1;
674 wr_lat = compute_cas_write_latency(ctrl_num);
677 #ifdef CONFIG_SYS_FSL_DDR4
678 rd_to_pre = picos_to_mclk(ctrl_num, 7500);
680 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
683 * JEDEC has some min requirements for tRTP
685 #if defined(CONFIG_SYS_FSL_DDR2)
688 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
692 if (popts->otf_burst_chop_en)
693 rd_to_pre += 2; /* according to UM */
695 wr_data_delay = popts->write_data_delay;
696 #ifdef CONFIG_SYS_FSL_DDR4
698 cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
699 #elif defined(CONFIG_SYS_FSL_DDR3)
701 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
702 * max(3nCK, 5.625ns) for DDR3-1066, 1333
703 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
705 cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
706 (mclk_ps > 1245 ? 5625 : 5000)));
708 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
710 four_act = picos_to_mclk(ctrl_num,
711 popts->tfaw_window_four_activates_ps);
713 ddr->timing_cfg_2 = (0
714 | ((add_lat_mclk & 0xf) << 28)
715 | ((cpo & 0x1f) << 23)
716 | ((wr_lat & 0xf) << 19)
717 | (((wr_lat & 0x10) >> 4) << 18)
718 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
719 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
720 | ((cke_pls & 0x7) << 6)
721 | ((four_act & 0x3f) << 0)
723 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
726 /* DDR SDRAM Register Control Word */
727 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
728 const memctl_options_t *popts,
729 const common_timing_params_t *common_dimm)
731 if (common_dimm->all_dimms_registered &&
732 !common_dimm->all_dimms_unbuffered) {
733 if (popts->rcw_override) {
734 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
735 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
736 ddr->ddr_sdram_rcw_3 = popts->rcw_3;
738 ddr->ddr_sdram_rcw_1 =
739 common_dimm->rcw[0] << 28 | \
740 common_dimm->rcw[1] << 24 | \
741 common_dimm->rcw[2] << 20 | \
742 common_dimm->rcw[3] << 16 | \
743 common_dimm->rcw[4] << 12 | \
744 common_dimm->rcw[5] << 8 | \
745 common_dimm->rcw[6] << 4 | \
747 ddr->ddr_sdram_rcw_2 =
748 common_dimm->rcw[8] << 28 | \
749 common_dimm->rcw[9] << 24 | \
750 common_dimm->rcw[10] << 20 | \
751 common_dimm->rcw[11] << 16 | \
752 common_dimm->rcw[12] << 12 | \
753 common_dimm->rcw[13] << 8 | \
754 common_dimm->rcw[14] << 4 | \
755 common_dimm->rcw[15];
757 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n",
758 ddr->ddr_sdram_rcw_1);
759 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n",
760 ddr->ddr_sdram_rcw_2);
761 debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n",
762 ddr->ddr_sdram_rcw_3);
766 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
767 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
768 const memctl_options_t *popts,
769 const common_timing_params_t *common_dimm)
771 unsigned int mem_en; /* DDR SDRAM interface logic enable */
772 unsigned int sren; /* Self refresh enable (during sleep) */
773 unsigned int ecc_en; /* ECC enable. */
774 unsigned int rd_en; /* Registered DIMM enable */
775 unsigned int sdram_type; /* Type of SDRAM */
776 unsigned int dyn_pwr; /* Dynamic power management mode */
777 unsigned int dbw; /* DRAM dta bus width */
778 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
779 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
780 unsigned int threet_en; /* Enable 3T timing */
781 unsigned int twot_en; /* Enable 2T timing */
782 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
783 unsigned int x32_en = 0; /* x32 enable */
784 unsigned int pchb8 = 0; /* precharge bit 8 enable */
785 unsigned int hse; /* Global half strength override */
786 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
787 unsigned int mem_halt = 0; /* memory controller halt */
788 unsigned int bi = 0; /* Bypass initialization */
791 sren = popts->self_refresh_in_sleep;
792 if (common_dimm->all_dimms_ecc_capable) {
793 /* Allow setting of ECC only if all DIMMs are ECC. */
794 ecc_en = popts->ecc_mode;
799 if (common_dimm->all_dimms_registered &&
800 !common_dimm->all_dimms_unbuffered) {
805 twot_en = popts->twot_en;
808 sdram_type = CONFIG_FSL_SDRAM_TYPE;
810 dyn_pwr = popts->dynamic_power;
811 dbw = popts->data_bus_width;
812 /* 8-beat burst enable DDR-III case
813 * we must clear it when use the on-the-fly mode,
814 * must set it when use the 32-bits bus mode.
816 if ((sdram_type == SDRAM_TYPE_DDR3) ||
817 (sdram_type == SDRAM_TYPE_DDR4)) {
818 if (popts->burst_length == DDR_BL8)
820 if (popts->burst_length == DDR_OTF)
826 threet_en = popts->threet_en;
827 ba_intlv_ctl = popts->ba_intlv_ctl;
828 hse = popts->half_strength_driver_enable;
830 /* set when ddr bus width < 64 */
831 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
833 ddr->ddr_sdram_cfg = (0
834 | ((mem_en & 0x1) << 31)
835 | ((sren & 0x1) << 30)
836 | ((ecc_en & 0x1) << 29)
837 | ((rd_en & 0x1) << 28)
838 | ((sdram_type & 0x7) << 24)
839 | ((dyn_pwr & 0x1) << 21)
840 | ((dbw & 0x3) << 19)
841 | ((eight_be & 0x1) << 18)
842 | ((ncap & 0x1) << 17)
843 | ((threet_en & 0x1) << 16)
844 | ((twot_en & 0x1) << 15)
845 | ((ba_intlv_ctl & 0x7F) << 8)
846 | ((x32_en & 0x1) << 5)
847 | ((pchb8 & 0x1) << 4)
849 | ((acc_ecc_en & 0x1) << 2)
850 | ((mem_halt & 0x1) << 1)
853 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
856 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
857 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
858 fsl_ddr_cfg_regs_t *ddr,
859 const memctl_options_t *popts,
860 const unsigned int unq_mrs_en)
862 unsigned int frc_sr = 0; /* Force self refresh */
863 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
864 unsigned int odt_cfg = 0; /* ODT configuration */
865 unsigned int num_pr; /* Number of posted refreshes */
866 unsigned int slow = 0; /* DDR will be run less than 1250 */
867 unsigned int x4_en = 0; /* x4 DRAM enable */
868 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
869 unsigned int ap_en; /* Address Parity Enable */
870 unsigned int d_init; /* DRAM data initialization */
871 unsigned int rcw_en = 0; /* Register Control Word Enable */
872 unsigned int md_en = 0; /* Mirrored DIMM Enable */
873 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
875 #ifndef CONFIG_SYS_FSL_DDR4
876 unsigned int dll_rst_dis = 1; /* DLL reset disable */
877 unsigned int dqs_cfg; /* DQS configuration */
879 dqs_cfg = popts->dqs_config;
881 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
882 if (popts->cs_local_opts[i].odt_rd_cfg
883 || popts->cs_local_opts[i].odt_wr_cfg) {
884 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
888 sr_ie = popts->self_refresh_interrupt_en;
889 num_pr = popts->package_3ds + 1;
893 * {TIMING_CFG_1[PRETOACT]
894 * + [DDR_SDRAM_CFG_2[NUM_PR]
895 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
896 * << DDR_SDRAM_INTERVAL[REFINT]
898 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
899 obc_cfg = popts->otf_burst_chop_en;
904 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
905 slow = get_ddr_freq(ctrl_num) < 1249000000;
908 if (popts->registered_dimm_en)
911 /* DDR4 can have address parity for UDIMM and discrete */
912 if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
913 (!popts->registered_dimm_en)) {
916 ap_en = popts->ap_en;
919 x4_en = popts->x4_en ? 1 : 0;
921 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
922 /* Use the DDR controller to auto initialize memory. */
923 d_init = popts->ecc_init_using_memctl;
924 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
925 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
927 /* Memory will be initialized via DMA, or not at all. */
931 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
932 md_en = popts->mirrored_dimm;
934 qd_en = popts->quad_rank_present ? 1 : 0;
935 ddr->ddr_sdram_cfg_2 = (0
936 | ((frc_sr & 0x1) << 31)
937 | ((sr_ie & 0x1) << 30)
938 #ifndef CONFIG_SYS_FSL_DDR4
939 | ((dll_rst_dis & 0x1) << 29)
940 | ((dqs_cfg & 0x3) << 26)
942 | ((odt_cfg & 0x3) << 21)
943 | ((num_pr & 0xf) << 12)
948 | ((obc_cfg & 0x1) << 6)
949 | ((ap_en & 0x1) << 5)
950 | ((d_init & 0x1) << 4)
951 | ((rcw_en & 0x1) << 2)
952 | ((md_en & 0x1) << 0)
954 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
957 #ifdef CONFIG_SYS_FSL_DDR4
958 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
959 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
960 fsl_ddr_cfg_regs_t *ddr,
961 const memctl_options_t *popts,
962 const common_timing_params_t *common_dimm,
963 const unsigned int unq_mrs_en)
965 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
966 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
968 unsigned int wr_crc = 0; /* Disable */
969 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
970 unsigned int srt = 0; /* self-refresh temerature, normal range */
971 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
972 unsigned int mpr = 0; /* serial */
974 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
976 if (popts->rtt_override)
977 rtt_wr = popts->rtt_wr_override_value;
979 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
981 if (common_dimm->extended_op_srt)
982 srt = common_dimm->extended_op_srt;
985 | ((wr_crc & 0x1) << 12)
986 | ((rtt_wr & 0x3) << 9)
988 | ((cwl & 0x7) << 3));
992 else if (mclk_ps >= 833)
998 | ((mpr & 0x3) << 11)
999 | ((wc_lat & 0x3) << 9));
1001 ddr->ddr_sdram_mode_2 = (0
1002 | ((esdmode2 & 0xFFFF) << 16)
1003 | ((esdmode3 & 0xFFFF) << 0)
1005 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1007 if (unq_mrs_en) { /* unique mode registers are supported */
1008 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1009 if (popts->rtt_override)
1010 rtt_wr = popts->rtt_wr_override_value;
1012 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1014 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1015 esdmode2 |= (rtt_wr & 0x3) << 9;
1018 ddr->ddr_sdram_mode_4 = (0
1019 | ((esdmode2 & 0xFFFF) << 16)
1020 | ((esdmode3 & 0xFFFF) << 0)
1024 ddr->ddr_sdram_mode_6 = (0
1025 | ((esdmode2 & 0xFFFF) << 16)
1026 | ((esdmode3 & 0xFFFF) << 0)
1030 ddr->ddr_sdram_mode_8 = (0
1031 | ((esdmode2 & 0xFFFF) << 16)
1032 | ((esdmode3 & 0xFFFF) << 0)
1037 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1038 ddr->ddr_sdram_mode_4);
1039 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1040 ddr->ddr_sdram_mode_6);
1041 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1042 ddr->ddr_sdram_mode_8);
1045 #elif defined(CONFIG_SYS_FSL_DDR3)
1046 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1047 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1048 fsl_ddr_cfg_regs_t *ddr,
1049 const memctl_options_t *popts,
1050 const common_timing_params_t *common_dimm,
1051 const unsigned int unq_mrs_en)
1053 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1054 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1056 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
1057 unsigned int srt = 0; /* self-refresh temerature, normal range */
1058 unsigned int asr = 0; /* auto self-refresh disable */
1059 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1060 unsigned int pasr = 0; /* partial array self refresh disable */
1062 if (popts->rtt_override)
1063 rtt_wr = popts->rtt_wr_override_value;
1065 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1067 if (common_dimm->extended_op_srt)
1068 srt = common_dimm->extended_op_srt;
1071 | ((rtt_wr & 0x3) << 9)
1072 | ((srt & 0x1) << 7)
1073 | ((asr & 0x1) << 6)
1074 | ((cwl & 0x7) << 3)
1075 | ((pasr & 0x7) << 0));
1076 ddr->ddr_sdram_mode_2 = (0
1077 | ((esdmode2 & 0xFFFF) << 16)
1078 | ((esdmode3 & 0xFFFF) << 0)
1080 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1082 if (unq_mrs_en) { /* unique mode registers are supported */
1083 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1084 if (popts->rtt_override)
1085 rtt_wr = popts->rtt_wr_override_value;
1087 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1089 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1090 esdmode2 |= (rtt_wr & 0x3) << 9;
1093 ddr->ddr_sdram_mode_4 = (0
1094 | ((esdmode2 & 0xFFFF) << 16)
1095 | ((esdmode3 & 0xFFFF) << 0)
1099 ddr->ddr_sdram_mode_6 = (0
1100 | ((esdmode2 & 0xFFFF) << 16)
1101 | ((esdmode3 & 0xFFFF) << 0)
1105 ddr->ddr_sdram_mode_8 = (0
1106 | ((esdmode2 & 0xFFFF) << 16)
1107 | ((esdmode3 & 0xFFFF) << 0)
1112 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1113 ddr->ddr_sdram_mode_4);
1114 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1115 ddr->ddr_sdram_mode_6);
1116 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1117 ddr->ddr_sdram_mode_8);
1121 #else /* for DDR2 and DDR1 */
1122 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1123 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1124 fsl_ddr_cfg_regs_t *ddr,
1125 const memctl_options_t *popts,
1126 const common_timing_params_t *common_dimm,
1127 const unsigned int unq_mrs_en)
1129 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1130 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1132 ddr->ddr_sdram_mode_2 = (0
1133 | ((esdmode2 & 0xFFFF) << 16)
1134 | ((esdmode3 & 0xFFFF) << 0)
1136 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1140 #ifdef CONFIG_SYS_FSL_DDR4
1141 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1142 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1143 const memctl_options_t *popts,
1144 const common_timing_params_t *common_dimm,
1145 const unsigned int unq_mrs_en)
1148 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1149 unsigned short esdmode5; /* Extended SDRAM mode 5 */
1151 bool four_cs = false;
1152 const unsigned int mclk_ps = get_memory_clk_period_ps(0);
1154 #if CONFIG_CHIP_SELECTS_PER_CTRL == 4
1155 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
1156 (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
1157 (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
1158 (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
1161 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1162 esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */
1163 rtt_park = four_cs ? 0 : 1;
1165 esdmode5 = 0x00000400; /* Data mask enabled */
1169 * For DDR3, set C/A latency if address parity is enabled.
1170 * For DDR4, set C/A latency for UDIMM only. For RDIMM the delay is
1171 * handled by register chip and RCW settings.
1173 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1174 ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1175 !popts->registered_dimm_en)) {
1176 if (mclk_ps >= 935) {
1177 /* for DDR4-1600/1866/2133 */
1178 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1179 } else if (mclk_ps >= 833) {
1181 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1183 printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1187 ddr->ddr_sdram_mode_9 = (0
1188 | ((esdmode4 & 0xffff) << 16)
1189 | ((esdmode5 & 0xffff) << 0)
1192 /* Normally only the first enabled CS use 0x500, others use 0x400
1193 * But when four chip-selects are all enabled, all mode registers
1194 * need 0x500 to park.
1197 debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9);
1198 if (unq_mrs_en) { /* unique mode registers are supported */
1199 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1201 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1202 esdmode5 |= 0x00000500; /* RTT_PARK */
1203 rtt_park = four_cs ? 0 : 1;
1205 esdmode5 = 0x00000400;
1208 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1209 ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1210 !popts->registered_dimm_en)) {
1211 if (mclk_ps >= 935) {
1212 /* for DDR4-1600/1866/2133 */
1213 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1214 } else if (mclk_ps >= 833) {
1216 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1218 printf("parity: mclk_ps = %d not supported\n",
1225 ddr->ddr_sdram_mode_11 = (0
1226 | ((esdmode4 & 0xFFFF) << 16)
1227 | ((esdmode5 & 0xFFFF) << 0)
1231 ddr->ddr_sdram_mode_13 = (0
1232 | ((esdmode4 & 0xFFFF) << 16)
1233 | ((esdmode5 & 0xFFFF) << 0)
1237 ddr->ddr_sdram_mode_15 = (0
1238 | ((esdmode4 & 0xFFFF) << 16)
1239 | ((esdmode5 & 0xFFFF) << 0)
1244 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1245 ddr->ddr_sdram_mode_11);
1246 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1247 ddr->ddr_sdram_mode_13);
1248 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1249 ddr->ddr_sdram_mode_15);
1253 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1254 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1255 fsl_ddr_cfg_regs_t *ddr,
1256 const memctl_options_t *popts,
1257 const common_timing_params_t *common_dimm,
1258 const unsigned int unq_mrs_en)
1261 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
1262 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
1263 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1265 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1267 if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1268 esdmode6 |= 1 << 6; /* Range 2 */
1270 ddr->ddr_sdram_mode_10 = (0
1271 | ((esdmode6 & 0xffff) << 16)
1272 | ((esdmode7 & 0xffff) << 0)
1274 debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10);
1275 if (unq_mrs_en) { /* unique mode registers are supported */
1276 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1279 ddr->ddr_sdram_mode_12 = (0
1280 | ((esdmode6 & 0xFFFF) << 16)
1281 | ((esdmode7 & 0xFFFF) << 0)
1285 ddr->ddr_sdram_mode_14 = (0
1286 | ((esdmode6 & 0xFFFF) << 16)
1287 | ((esdmode7 & 0xFFFF) << 0)
1291 ddr->ddr_sdram_mode_16 = (0
1292 | ((esdmode6 & 0xFFFF) << 16)
1293 | ((esdmode7 & 0xFFFF) << 0)
1298 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1299 ddr->ddr_sdram_mode_12);
1300 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1301 ddr->ddr_sdram_mode_14);
1302 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1303 ddr->ddr_sdram_mode_16);
1309 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1310 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1311 fsl_ddr_cfg_regs_t *ddr,
1312 const memctl_options_t *popts,
1313 const common_timing_params_t *common_dimm)
1315 unsigned int refint; /* Refresh interval */
1316 unsigned int bstopre; /* Precharge interval */
1318 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1320 bstopre = popts->bstopre;
1322 /* refint field used 0x3FFF in earlier controllers */
1323 ddr->ddr_sdram_interval = (0
1324 | ((refint & 0xFFFF) << 16)
1325 | ((bstopre & 0x3FFF) << 0)
1327 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1330 #ifdef CONFIG_SYS_FSL_DDR4
1331 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1332 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1333 fsl_ddr_cfg_regs_t *ddr,
1334 const memctl_options_t *popts,
1335 const common_timing_params_t *common_dimm,
1336 unsigned int cas_latency,
1337 unsigned int additive_latency,
1338 const unsigned int unq_mrs_en)
1341 unsigned short esdmode; /* Extended SDRAM mode */
1342 unsigned short sdmode; /* SDRAM mode */
1344 /* Mode Register - MR1 */
1345 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1346 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1348 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1349 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1350 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1351 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
1352 0=Disable (Test/Debug) */
1354 /* Mode Register - MR0 */
1355 unsigned int wr = 0; /* Write Recovery */
1356 unsigned int dll_rst; /* DLL Reset */
1357 unsigned int mode; /* Normal=0 or Test=1 */
1358 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1359 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1361 unsigned int bl; /* BL: Burst Length */
1363 unsigned int wr_mclk;
1364 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1365 static const u8 wr_table[] = {
1366 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1367 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1368 static const u8 cas_latency_table[] = {
1369 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1370 9, 9, 10, 10, 11, 11};
1372 if (popts->rtt_override)
1373 rtt = popts->rtt_override_value;
1375 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1377 if (additive_latency == (cas_latency - 1))
1379 if (additive_latency == (cas_latency - 2))
1382 if (popts->quad_rank_present)
1383 dic = 1; /* output driver impedance 240/7 ohm */
1386 * The esdmode value will also be used for writing
1387 * MR1 during write leveling for DDR3, although the
1388 * bits specifically related to the write leveling
1389 * scheme will be handled automatically by the DDR
1390 * controller. so we set the wrlvl_en = 0 here.
1393 | ((qoff & 0x1) << 12)
1394 | ((tdqs_en & 0x1) << 11)
1395 | ((rtt & 0x7) << 8)
1396 | ((wrlvl_en & 0x1) << 7)
1398 | ((dic & 0x3) << 1) /* DIC field is split */
1399 | ((dll_en & 0x1) << 0)
1403 * DLL control for precharge PD
1404 * 0=slow exit DLL off (tXPDLL)
1405 * 1=fast exit DLL on (tXP)
1408 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1409 if (wr_mclk <= 24) {
1410 wr = wr_table[wr_mclk - 10];
1412 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1416 dll_rst = 0; /* dll no reset */
1417 mode = 0; /* normal mode */
1419 /* look up table to get the cas latency bits */
1420 if (cas_latency >= 9 && cas_latency <= 24)
1421 caslat = cas_latency_table[cas_latency - 9];
1423 printf("Error: unsupported cas latency for mode register\n");
1425 bt = 0; /* Nibble sequential */
1427 switch (popts->burst_length) {
1438 printf("Error: invalid burst length of %u specified. ",
1439 popts->burst_length);
1440 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1447 | ((dll_rst & 0x1) << 8)
1448 | ((mode & 0x1) << 7)
1449 | (((caslat >> 1) & 0x7) << 4)
1451 | ((caslat & 1) << 2)
1455 ddr->ddr_sdram_mode = (0
1456 | ((esdmode & 0xFFFF) << 16)
1457 | ((sdmode & 0xFFFF) << 0)
1460 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1462 if (unq_mrs_en) { /* unique mode registers are supported */
1463 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1464 if (popts->rtt_override)
1465 rtt = popts->rtt_override_value;
1467 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1469 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
1470 esdmode |= (rtt & 0x7) << 8;
1473 ddr->ddr_sdram_mode_3 = (0
1474 | ((esdmode & 0xFFFF) << 16)
1475 | ((sdmode & 0xFFFF) << 0)
1479 ddr->ddr_sdram_mode_5 = (0
1480 | ((esdmode & 0xFFFF) << 16)
1481 | ((sdmode & 0xFFFF) << 0)
1485 ddr->ddr_sdram_mode_7 = (0
1486 | ((esdmode & 0xFFFF) << 16)
1487 | ((sdmode & 0xFFFF) << 0)
1492 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1493 ddr->ddr_sdram_mode_3);
1494 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1495 ddr->ddr_sdram_mode_5);
1496 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1497 ddr->ddr_sdram_mode_5);
1501 #elif defined(CONFIG_SYS_FSL_DDR3)
1502 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1503 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1504 fsl_ddr_cfg_regs_t *ddr,
1505 const memctl_options_t *popts,
1506 const common_timing_params_t *common_dimm,
1507 unsigned int cas_latency,
1508 unsigned int additive_latency,
1509 const unsigned int unq_mrs_en)
1512 unsigned short esdmode; /* Extended SDRAM mode */
1513 unsigned short sdmode; /* SDRAM mode */
1515 /* Mode Register - MR1 */
1516 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1517 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1519 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1520 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1521 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1522 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1523 1=Disable (Test/Debug) */
1525 /* Mode Register - MR0 */
1526 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
1527 unsigned int wr = 0; /* Write Recovery */
1528 unsigned int dll_rst; /* DLL Reset */
1529 unsigned int mode; /* Normal=0 or Test=1 */
1530 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1531 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1533 unsigned int bl; /* BL: Burst Length */
1535 unsigned int wr_mclk;
1537 * DDR_SDRAM_MODE doesn't support 9,11,13,15
1538 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1541 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1543 if (popts->rtt_override)
1544 rtt = popts->rtt_override_value;
1546 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1548 if (additive_latency == (cas_latency - 1))
1550 if (additive_latency == (cas_latency - 2))
1553 if (popts->quad_rank_present)
1554 dic = 1; /* output driver impedance 240/7 ohm */
1557 * The esdmode value will also be used for writing
1558 * MR1 during write leveling for DDR3, although the
1559 * bits specifically related to the write leveling
1560 * scheme will be handled automatically by the DDR
1561 * controller. so we set the wrlvl_en = 0 here.
1564 | ((qoff & 0x1) << 12)
1565 | ((tdqs_en & 0x1) << 11)
1566 | ((rtt & 0x4) << 7) /* rtt field is split */
1567 | ((wrlvl_en & 0x1) << 7)
1568 | ((rtt & 0x2) << 5) /* rtt field is split */
1569 | ((dic & 0x2) << 4) /* DIC field is split */
1571 | ((rtt & 0x1) << 2) /* rtt field is split */
1572 | ((dic & 0x1) << 1) /* DIC field is split */
1573 | ((dll_en & 0x1) << 0)
1577 * DLL control for precharge PD
1578 * 0=slow exit DLL off (tXPDLL)
1579 * 1=fast exit DLL on (tXP)
1583 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1584 if (wr_mclk <= 16) {
1585 wr = wr_table[wr_mclk - 5];
1587 printf("Error: unsupported write recovery for mode register "
1588 "wr_mclk = %d\n", wr_mclk);
1591 dll_rst = 0; /* dll no reset */
1592 mode = 0; /* normal mode */
1594 /* look up table to get the cas latency bits */
1595 if (cas_latency >= 5 && cas_latency <= 16) {
1596 unsigned char cas_latency_table[] = {
1602 0xc, /* 10 clocks */
1603 0xe, /* 11 clocks */
1604 0x1, /* 12 clocks */
1605 0x3, /* 13 clocks */
1606 0x5, /* 14 clocks */
1607 0x7, /* 15 clocks */
1608 0x9, /* 16 clocks */
1610 caslat = cas_latency_table[cas_latency - 5];
1612 printf("Error: unsupported cas latency for mode register\n");
1615 bt = 0; /* Nibble sequential */
1617 switch (popts->burst_length) {
1628 printf("Error: invalid burst length of %u specified. "
1629 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1630 popts->burst_length);
1636 | ((dll_on & 0x1) << 12)
1638 | ((dll_rst & 0x1) << 8)
1639 | ((mode & 0x1) << 7)
1640 | (((caslat >> 1) & 0x7) << 4)
1642 | ((caslat & 1) << 2)
1646 ddr->ddr_sdram_mode = (0
1647 | ((esdmode & 0xFFFF) << 16)
1648 | ((sdmode & 0xFFFF) << 0)
1651 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1653 if (unq_mrs_en) { /* unique mode registers are supported */
1654 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1655 if (popts->rtt_override)
1656 rtt = popts->rtt_override_value;
1658 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1660 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1662 | ((rtt & 0x4) << 7) /* rtt field is split */
1663 | ((rtt & 0x2) << 5) /* rtt field is split */
1664 | ((rtt & 0x1) << 2) /* rtt field is split */
1668 ddr->ddr_sdram_mode_3 = (0
1669 | ((esdmode & 0xFFFF) << 16)
1670 | ((sdmode & 0xFFFF) << 0)
1674 ddr->ddr_sdram_mode_5 = (0
1675 | ((esdmode & 0xFFFF) << 16)
1676 | ((sdmode & 0xFFFF) << 0)
1680 ddr->ddr_sdram_mode_7 = (0
1681 | ((esdmode & 0xFFFF) << 16)
1682 | ((sdmode & 0xFFFF) << 0)
1687 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1688 ddr->ddr_sdram_mode_3);
1689 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1690 ddr->ddr_sdram_mode_5);
1691 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1692 ddr->ddr_sdram_mode_5);
1696 #else /* !CONFIG_SYS_FSL_DDR3 */
1698 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1699 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1700 fsl_ddr_cfg_regs_t *ddr,
1701 const memctl_options_t *popts,
1702 const common_timing_params_t *common_dimm,
1703 unsigned int cas_latency,
1704 unsigned int additive_latency,
1705 const unsigned int unq_mrs_en)
1707 unsigned short esdmode; /* Extended SDRAM mode */
1708 unsigned short sdmode; /* SDRAM mode */
1711 * FIXME: This ought to be pre-calculated in a
1712 * technology-specific routine,
1713 * e.g. compute_DDR2_mode_register(), and then the
1714 * sdmode and esdmode passed in as part of common_dimm.
1717 /* Extended Mode Register */
1718 unsigned int mrs = 0; /* Mode Register Set */
1719 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1720 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1721 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1722 unsigned int ocd = 0; /* 0x0=OCD not supported,
1723 0x7=OCD default state */
1725 unsigned int al; /* Posted CAS# additive latency (AL) */
1726 unsigned int ods = 0; /* Output Drive Strength:
1727 0 = Full strength (18ohm)
1728 1 = Reduced strength (4ohm) */
1729 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1730 1=Disable (Test/Debug) */
1732 /* Mode Register (MR) */
1733 unsigned int mr; /* Mode Register Definition */
1734 unsigned int pd; /* Power-Down Mode */
1735 unsigned int wr; /* Write Recovery */
1736 unsigned int dll_res; /* DLL Reset */
1737 unsigned int mode; /* Normal=0 or Test=1 */
1738 unsigned int caslat = 0;/* CAS# latency */
1739 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1741 unsigned int bl; /* BL: Burst Length */
1743 dqs_en = !popts->dqs_config;
1744 rtt = fsl_ddr_get_rtt();
1746 al = additive_latency;
1749 | ((mrs & 0x3) << 14)
1750 | ((outputs & 0x1) << 12)
1751 | ((rdqs_en & 0x1) << 11)
1752 | ((dqs_en & 0x1) << 10)
1753 | ((ocd & 0x7) << 7)
1754 | ((rtt & 0x2) << 5) /* rtt field is split */
1756 | ((rtt & 0x1) << 2) /* rtt field is split */
1757 | ((ods & 0x1) << 1)
1758 | ((dll_en & 0x1) << 0)
1761 mr = 0; /* FIXME: CHECKME */
1764 * 0 = Fast Exit (Normal)
1765 * 1 = Slow Exit (Low Power)
1769 #if defined(CONFIG_SYS_FSL_DDR1)
1770 wr = 0; /* Historical */
1771 #elif defined(CONFIG_SYS_FSL_DDR2)
1772 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1777 #if defined(CONFIG_SYS_FSL_DDR1)
1778 if (1 <= cas_latency && cas_latency <= 4) {
1779 unsigned char mode_caslat_table[4] = {
1780 0x5, /* 1.5 clocks */
1781 0x2, /* 2.0 clocks */
1782 0x6, /* 2.5 clocks */
1783 0x3 /* 3.0 clocks */
1785 caslat = mode_caslat_table[cas_latency - 1];
1787 printf("Warning: unknown cas_latency %d\n", cas_latency);
1789 #elif defined(CONFIG_SYS_FSL_DDR2)
1790 caslat = cas_latency;
1794 switch (popts->burst_length) {
1802 printf("Error: invalid burst length of %u specified. "
1803 " Defaulting to 4 beats.\n",
1804 popts->burst_length);
1810 | ((mr & 0x3) << 14)
1811 | ((pd & 0x1) << 12)
1813 | ((dll_res & 0x1) << 8)
1814 | ((mode & 0x1) << 7)
1815 | ((caslat & 0x7) << 4)
1820 ddr->ddr_sdram_mode = (0
1821 | ((esdmode & 0xFFFF) << 16)
1822 | ((sdmode & 0xFFFF) << 0)
1824 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1828 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1829 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1831 unsigned int init_value; /* Initialization value */
1833 #ifdef CONFIG_MEM_INIT_VALUE
1834 init_value = CONFIG_MEM_INIT_VALUE;
1836 init_value = 0xDEADBEEF;
1838 ddr->ddr_data_init = init_value;
1842 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1843 * The old controller on the 8540/60 doesn't have this register.
1844 * Hope it's OK to set it (to 0) anyway.
1846 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1847 const memctl_options_t *popts)
1849 unsigned int clk_adjust; /* Clock adjust */
1850 unsigned int ss_en = 0; /* Source synchronous enable */
1852 #if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
1853 /* Per FSL Application Note: AN2805 */
1856 if (fsl_ddr_get_version(0) >= 0x40701) {
1857 /* clk_adjust in 5-bits on T-series and LS-series */
1858 clk_adjust = (popts->clk_adjust & 0x1F) << 22;
1860 /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
1861 clk_adjust = (popts->clk_adjust & 0xF) << 23;
1864 ddr->ddr_sdram_clk_cntl = (0
1865 | ((ss_en & 0x1) << 31)
1868 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1871 /* DDR Initialization Address (DDR_INIT_ADDR) */
1872 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1874 unsigned int init_addr = 0; /* Initialization address */
1876 ddr->ddr_init_addr = init_addr;
1879 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1880 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1882 unsigned int uia = 0; /* Use initialization address */
1883 unsigned int init_ext_addr = 0; /* Initialization address */
1885 ddr->ddr_init_ext_addr = (0
1886 | ((uia & 0x1) << 31)
1887 | (init_ext_addr & 0xF)
1891 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1892 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1893 const memctl_options_t *popts)
1895 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1896 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1897 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1898 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1899 unsigned int trwt_mclk = 0; /* ext_rwt */
1900 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1902 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1903 if (popts->burst_length == DDR_BL8) {
1904 /* We set BL/2 for fixed BL8 */
1905 rrt = 0; /* BL/2 clocks */
1906 wwt = 0; /* BL/2 clocks */
1908 /* We need to set BL/2 + 2 to BC4 and OTF */
1909 rrt = 2; /* BL/2 + 2 clocks */
1910 wwt = 2; /* BL/2 + 2 clocks */
1913 #ifdef CONFIG_SYS_FSL_DDR4
1914 dll_lock = 2; /* tDLLK = 1024 clocks */
1915 #elif defined(CONFIG_SYS_FSL_DDR3)
1916 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1919 if (popts->trwt_override)
1920 trwt_mclk = popts->trwt;
1922 ddr->timing_cfg_4 = (0
1923 | ((rwt & 0xf) << 28)
1924 | ((wrt & 0xf) << 24)
1925 | ((rrt & 0xf) << 20)
1926 | ((wwt & 0xf) << 16)
1927 | ((trwt_mclk & 0xc) << 12)
1930 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1933 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1934 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1936 unsigned int rodt_on = 0; /* Read to ODT on */
1937 unsigned int rodt_off = 0; /* Read to ODT off */
1938 unsigned int wodt_on = 0; /* Write to ODT on */
1939 unsigned int wodt_off = 0; /* Write to ODT off */
1941 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1942 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1943 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1944 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1945 if (cas_latency >= wr_lat)
1946 rodt_on = cas_latency - wr_lat + 1;
1947 rodt_off = 4; /* 4 clocks */
1948 wodt_on = 1; /* 1 clocks */
1949 wodt_off = 4; /* 4 clocks */
1952 ddr->timing_cfg_5 = (0
1953 | ((rodt_on & 0x1f) << 24)
1954 | ((rodt_off & 0x7) << 20)
1955 | ((wodt_on & 0x1f) << 12)
1956 | ((wodt_off & 0x7) << 8)
1958 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1961 #ifdef CONFIG_SYS_FSL_DDR4
1962 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1964 unsigned int hs_caslat = 0;
1965 unsigned int hs_wrlat = 0;
1966 unsigned int hs_wrrec = 0;
1967 unsigned int hs_clkadj = 0;
1968 unsigned int hs_wrlvl_start = 0;
1970 ddr->timing_cfg_6 = (0
1971 | ((hs_caslat & 0x1f) << 24)
1972 | ((hs_wrlat & 0x1f) << 19)
1973 | ((hs_wrrec & 0x1f) << 12)
1974 | ((hs_clkadj & 0x1f) << 6)
1975 | ((hs_wrlvl_start & 0x1f) << 0)
1977 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1980 static void set_timing_cfg_7(const unsigned int ctrl_num,
1981 fsl_ddr_cfg_regs_t *ddr,
1982 const memctl_options_t *popts,
1983 const common_timing_params_t *common_dimm)
1985 unsigned int txpr, tcksre, tcksrx;
1986 unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
1987 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
1989 txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
1990 tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
1991 tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
1993 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN &&
1994 CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
1996 par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1;
1997 debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps);
2004 else if (txpr <= 256)
2006 else if (txpr <= 512)
2021 ddr->timing_cfg_7 = (0
2022 | ((cke_rst & 0x3) << 28)
2023 | ((cksre & 0xf) << 24)
2024 | ((cksrx & 0xf) << 20)
2025 | ((par_lat & 0xf) << 16)
2026 | ((cs_to_cmd & 0xf) << 4)
2028 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
2031 static void set_timing_cfg_8(const unsigned int ctrl_num,
2032 fsl_ddr_cfg_regs_t *ddr,
2033 const memctl_options_t *popts,
2034 const common_timing_params_t *common_dimm,
2035 unsigned int cas_latency)
2037 int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
2038 unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
2039 int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
2040 int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
2041 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
2043 rwt_bg = cas_latency + 2 + 4 - wr_lat;
2045 rwt_bg = tccdl - rwt_bg;
2049 wrt_bg = wr_lat + 4 + 1 - cas_latency;
2051 wrt_bg = tccdl - wrt_bg;
2055 if (popts->burst_length == DDR_BL8) {
2063 acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
2064 wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
2065 if (popts->otf_burst_chop_en)
2070 ddr->timing_cfg_8 = (0
2071 | ((rwt_bg & 0xf) << 28)
2072 | ((wrt_bg & 0xf) << 24)
2073 | ((rrt_bg & 0xf) << 20)
2074 | ((wwt_bg & 0xf) << 16)
2075 | ((acttoact_bg & 0xf) << 12)
2076 | ((wrtord_bg & 0xf) << 8)
2077 | ((pre_all_rec & 0x1f) << 0)
2080 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
2083 static void set_timing_cfg_9(const unsigned int ctrl_num,
2084 fsl_ddr_cfg_regs_t *ddr,
2085 const memctl_options_t *popts,
2086 const common_timing_params_t *common_dimm)
2088 unsigned int refrec_cid_mclk = 0;
2089 unsigned int acttoact_cid_mclk = 0;
2091 if (popts->package_3ds) {
2093 picos_to_mclk(ctrl_num, common_dimm->trfc_slr_ps);
2094 acttoact_cid_mclk = 4U; /* tRRDS_slr */
2097 ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16 |
2098 (acttoact_cid_mclk & 0xf) << 8;
2100 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
2103 /* This function needs to be called after set_ddr_sdram_cfg() is called */
2104 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
2105 const dimm_params_t *dimm_params)
2107 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
2110 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
2111 if (dimm_params[i].n_ranks)
2114 if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
2115 puts("DDR error: no DIMM found!\n");
2119 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2120 ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2121 ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2122 ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2123 ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
2125 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2126 ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2127 ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2128 ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2129 ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
2131 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2132 ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2133 ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2134 ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2135 ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
2137 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
2138 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2139 ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
2141 (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2142 dimm_params[i].dq_mapping_ors;
2144 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2145 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2146 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2147 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2149 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2150 const memctl_options_t *popts)
2154 rd_pre = popts->quad_rank_present ? 1 : 0;
2156 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2157 /* Disable MRS on parity error for RDIMMs */
2158 ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0;
2160 if (popts->package_3ds) { /* only 2,4,8 are supported */
2161 if ((popts->package_3ds + 1) & 0x1) {
2162 printf("Error: Unsupported 3DS DIMM with %d die\n",
2163 popts->package_3ds + 1);
2165 ddr->ddr_sdram_cfg_3 |= ((popts->package_3ds + 1) >> 1)
2170 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2172 #endif /* CONFIG_SYS_FSL_DDR4 */
2174 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2175 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2177 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2178 /* Normal Operation Full Calibration Time (tZQoper) */
2179 unsigned int zqoper = 0;
2180 /* Normal Operation Short Calibration Time (tZQCS) */
2181 unsigned int zqcs = 0;
2182 #ifdef CONFIG_SYS_FSL_DDR4
2183 unsigned int zqcs_init;
2187 #ifdef CONFIG_SYS_FSL_DDR4
2188 zqinit = 10; /* 1024 clocks */
2189 zqoper = 9; /* 512 clocks */
2190 zqcs = 7; /* 128 clocks */
2191 zqcs_init = 5; /* 1024 refresh sequences */
2193 zqinit = 9; /* 512 clocks */
2194 zqoper = 8; /* 256 clocks */
2195 zqcs = 6; /* 64 clocks */
2199 ddr->ddr_zq_cntl = (0
2200 | ((zq_en & 0x1) << 31)
2201 | ((zqinit & 0xF) << 24)
2202 | ((zqoper & 0xF) << 16)
2203 | ((zqcs & 0xF) << 8)
2204 #ifdef CONFIG_SYS_FSL_DDR4
2205 | ((zqcs_init & 0xF) << 0)
2208 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2211 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2212 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2213 const memctl_options_t *popts)
2216 * First DQS pulse rising edge after margining mode
2217 * is programmed (tWL_MRD)
2219 unsigned int wrlvl_mrd = 0;
2220 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2221 unsigned int wrlvl_odten = 0;
2222 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2223 unsigned int wrlvl_dqsen = 0;
2224 /* WRLVL_SMPL: Write leveling sample time */
2225 unsigned int wrlvl_smpl = 0;
2226 /* WRLVL_WLR: Write leveling repeition time */
2227 unsigned int wrlvl_wlr = 0;
2228 /* WRLVL_START: Write leveling start time */
2229 unsigned int wrlvl_start = 0;
2231 /* suggest enable write leveling for DDR3 due to fly-by topology */
2233 /* tWL_MRD min = 40 nCK, we set it 64 */
2237 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2240 * Write leveling sample time at least need 6 clocks
2241 * higher than tWLO to allow enough time for progagation
2242 * delay and sampling the prime data bits.
2246 * Write leveling repetition time
2247 * at least tWLO + 6 clocks clocks
2252 * Write leveling start time
2253 * The value use for the DQS_ADJUST for the first sample
2254 * when write leveling is enabled. It probably needs to be
2255 * overridden per platform.
2259 * Override the write leveling sample and start time
2260 * according to specific board
2262 if (popts->wrlvl_override) {
2263 wrlvl_smpl = popts->wrlvl_sample;
2264 wrlvl_start = popts->wrlvl_start;
2268 ddr->ddr_wrlvl_cntl = (0
2269 | ((wrlvl_en & 0x1) << 31)
2270 | ((wrlvl_mrd & 0x7) << 24)
2271 | ((wrlvl_odten & 0x7) << 20)
2272 | ((wrlvl_dqsen & 0x7) << 16)
2273 | ((wrlvl_smpl & 0xf) << 12)
2274 | ((wrlvl_wlr & 0x7) << 8)
2275 | ((wrlvl_start & 0x1F) << 0)
2277 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2278 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2279 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2280 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2281 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2285 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2286 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2288 /* Self Refresh Idle Threshold */
2289 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2292 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2294 if (popts->addr_hash) {
2295 ddr->ddr_eor = 0x40000000; /* address hash enable */
2296 puts("Address hashing enabled.\n");
2300 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2302 ddr->ddr_cdr1 = popts->ddr_cdr1;
2303 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2306 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2308 ddr->ddr_cdr2 = popts->ddr_cdr2;
2309 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2313 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2315 unsigned int res = 0;
2318 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2319 * not set at the same time.
2321 if (ddr->ddr_sdram_cfg & 0x10000000
2322 && ddr->ddr_sdram_cfg & 0x00008000) {
2323 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2324 " should not be set at the same time.\n");
2332 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2333 const memctl_options_t *popts,
2334 fsl_ddr_cfg_regs_t *ddr,
2335 const common_timing_params_t *common_dimm,
2336 const dimm_params_t *dimm_params,
2337 unsigned int dbw_cap_adj,
2338 unsigned int size_only)
2341 unsigned int cas_latency;
2342 unsigned int additive_latency;
2345 unsigned int wrlvl_en;
2346 unsigned int ip_rev = 0;
2347 unsigned int unq_mrs_en = 0;
2349 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2350 unsigned int ddr_freq;
2352 #if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
2353 defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
2354 defined(CONFIG_SYS_FSL_ERRATUM_A009942)
2355 struct ccsr_ddr __iomem *ddrc;
2359 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
2361 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
2363 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
2366 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
2368 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
2371 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
2373 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
2377 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
2382 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2384 if (common_dimm == NULL) {
2385 printf("Error: subset DIMM params struct null pointer\n");
2390 * Process overrides first.
2392 * FIXME: somehow add dereated caslat to this
2394 cas_latency = (popts->cas_latency_override)
2395 ? popts->cas_latency_override_value
2396 : common_dimm->lowest_common_spd_caslat;
2398 additive_latency = (popts->additive_latency_override)
2399 ? popts->additive_latency_override_value
2400 : common_dimm->additive_latency;
2402 sr_it = (popts->auto_self_refresh_en)
2405 /* ZQ calibration */
2406 zq_en = (popts->zq_en) ? 1 : 0;
2407 /* write leveling */
2408 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2410 /* Chip Select Memory Bounds (CSn_BNDS) */
2411 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2412 unsigned long long ea, sa;
2413 unsigned int cs_per_dimm
2414 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2415 unsigned int dimm_number
2417 unsigned long long rank_density
2418 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2420 if (dimm_params[dimm_number].n_ranks == 0) {
2421 debug("Skipping setup of CS%u "
2422 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2425 if (popts->memctl_interleaving) {
2426 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2427 case FSL_DDR_CS0_CS1_CS2_CS3:
2429 case FSL_DDR_CS0_CS1:
2430 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2434 case FSL_DDR_CS2_CS3:
2440 sa = common_dimm->base_address;
2441 ea = sa + common_dimm->total_mem - 1;
2442 } else if (!popts->memctl_interleaving) {
2444 * If memory interleaving between controllers is NOT
2445 * enabled, the starting address for each memory
2446 * controller is distinct. However, because rank
2447 * interleaving is enabled, the starting and ending
2448 * addresses of the total memory on that memory
2449 * controller needs to be programmed into its
2450 * respective CS0_BNDS.
2452 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2453 case FSL_DDR_CS0_CS1_CS2_CS3:
2454 sa = common_dimm->base_address;
2455 ea = sa + common_dimm->total_mem - 1;
2457 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2458 if ((i >= 2) && (dimm_number == 0)) {
2459 sa = dimm_params[dimm_number].base_address +
2461 ea = sa + 2 * rank_density - 1;
2463 sa = dimm_params[dimm_number].base_address;
2464 ea = sa + 2 * rank_density - 1;
2467 case FSL_DDR_CS0_CS1:
2468 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2469 sa = dimm_params[dimm_number].base_address;
2470 ea = sa + rank_density - 1;
2472 sa += (i % cs_per_dimm) * rank_density;
2473 ea += (i % cs_per_dimm) * rank_density;
2481 case FSL_DDR_CS2_CS3:
2482 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2483 sa = dimm_params[dimm_number].base_address;
2484 ea = sa + rank_density - 1;
2486 sa += (i % cs_per_dimm) * rank_density;
2487 ea += (i % cs_per_dimm) * rank_density;
2493 ea += (rank_density >> dbw_cap_adj);
2495 default: /* No bank(chip-select) interleaving */
2496 sa = dimm_params[dimm_number].base_address;
2497 ea = sa + rank_density - 1;
2498 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2499 sa += (i % cs_per_dimm) * rank_density;
2500 ea += (i % cs_per_dimm) * rank_density;
2513 ddr->cs[i].bnds = (0
2514 | ((sa & 0xffff) << 16) /* starting address */
2515 | ((ea & 0xffff) << 0) /* ending address */
2518 /* setting bnds to 0xffffffff for inactive CS */
2519 ddr->cs[i].bnds = 0xffffffff;
2522 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2523 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2524 set_csn_config_2(i, ddr);
2528 * In the case we only need to compute the ddr sdram size, we only need
2529 * to set csn registers, so return from here.
2534 set_ddr_eor(ddr, popts);
2536 #if !defined(CONFIG_SYS_FSL_DDR1)
2537 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2540 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2542 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2543 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2544 cas_latency, additive_latency);
2546 set_ddr_cdr1(ddr, popts);
2547 set_ddr_cdr2(ddr, popts);
2548 set_ddr_sdram_cfg(ddr, popts, common_dimm);
2549 ip_rev = fsl_ddr_get_version(ctrl_num);
2550 if (ip_rev > 0x40400)
2553 if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2554 ddr->debug[18] = popts->cswl_override;
2556 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2557 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2558 cas_latency, additive_latency, unq_mrs_en);
2559 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2560 #ifdef CONFIG_SYS_FSL_DDR4
2561 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2562 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2564 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2565 set_ddr_data_init(ddr);
2566 set_ddr_sdram_clk_cntl(ddr, popts);
2567 set_ddr_init_addr(ddr);
2568 set_ddr_init_ext_addr(ddr);
2569 set_timing_cfg_4(ddr, popts);
2570 set_timing_cfg_5(ddr, cas_latency);
2571 #ifdef CONFIG_SYS_FSL_DDR4
2572 set_ddr_sdram_cfg_3(ddr, popts);
2573 set_timing_cfg_6(ddr);
2574 set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm);
2575 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2576 set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm);
2577 set_ddr_dq_mapping(ddr, dimm_params);
2580 set_ddr_zq_cntl(ddr, zq_en);
2581 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2583 set_ddr_sr_cntr(ddr, sr_it);
2585 set_ddr_sdram_rcw(ddr, popts, common_dimm);
2587 #ifdef CONFIG_SYS_FSL_DDR_EMU
2588 /* disble DDR training for emulator */
2589 ddr->debug[2] = 0x00000400;
2590 ddr->debug[4] = 0xff800800;
2591 ddr->debug[5] = 0x08000800;
2592 ddr->debug[6] = 0x08000800;
2593 ddr->debug[7] = 0x08000800;
2594 ddr->debug[8] = 0x08000800;
2596 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2597 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2598 ddr->debug[2] |= 0x00000200; /* set bit 22 */
2601 #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
2602 /* Erratum applies when accumulated ECC is used, or DBI is enabled */
2603 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
2604 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
2605 if (has_erratum_a008378()) {
2606 if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
2607 IS_DBI(ddr->ddr_sdram_cfg_3)) {
2608 ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
2609 ddr->debug[28] |= (0x9 << 20);
2614 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2615 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
2616 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
2617 ddr->debug[28] &= 0xff0fff00;
2618 if (ddr_freq <= 1333)
2619 ddr->debug[28] |= 0x0080006a;
2620 else if (ddr_freq <= 1600)
2621 ddr->debug[28] |= 0x0070006f;
2622 else if (ddr_freq <= 1867)
2623 ddr->debug[28] |= 0x00700076;
2624 else if (ddr_freq <= 2133)
2625 ddr->debug[28] |= 0x0060007b;
2626 if (popts->cpo_sample)
2627 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
2631 return check_fsl_memctl_config_regs(ddr);
2634 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2636 * This additional workaround of A009942 checks the condition to determine if
2637 * the CPO value set by the existing A009942 workaround needs to be updated.
2638 * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
2639 * expected optimal value, the optimal value is highly board dependent.
2641 void erratum_a009942_check_cpo(void)
2643 struct ccsr_ddr __iomem *ddr =
2644 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
2645 u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
2646 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
2647 u32 cpo_max = cpo_min;
2648 u32 sdram_cfg, i, tmp, lanes, ddr_type;
2649 bool update_cpo = false, has_ecc = false;
2651 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
2652 if (sdram_cfg & SDRAM_CFG_32_BE)
2654 else if (sdram_cfg & SDRAM_CFG_16_BE)
2659 if (sdram_cfg & SDRAM_CFG_ECC_EN)
2662 /* determine the maximum and minimum CPO values */
2663 for (i = 9; i < 9 + lanes / 2; i++) {
2664 cpo = ddr_in32(&ddr->debug[i]);
2666 cpo_o = (cpo >> 8) & 0xff;
2667 tmp = min(cpo_e, cpo_o);
2670 tmp = max(cpo_e, cpo_o);
2676 cpo = ddr_in32(&ddr->debug[13]);
2684 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
2685 cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
2686 debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
2688 debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
2690 ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
2691 SDRAM_CFG_SDRAM_TYPE_SHIFT;
2692 if (ddr_type == SDRAM_TYPE_DDR4)
2693 update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
2694 else if (ddr_type == SDRAM_TYPE_DDR3)
2695 update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
2698 printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
2699 printf("in <board>/ddr.c to optimize cpo\n");