git.sur5r.net Git - u-boot/blob - drivers/ddr/fsl/interactive.c

   1 /*
   2  * Copyright 2010-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  *         York Sun [at freescale.com]
  12  */
  13
  14 #include <common.h>
  15 #include <cli.h>
  16 #include <linux/ctype.h>
  17 #include <asm/types.h>
  18 #include <asm/io.h>
  19
  20 #include <fsl_ddr_sdram.h>
  21 #include <fsl_ddr.h>
  22
  23 /* Option parameter Structures */
  24 struct options_string {
  25         const char *option_name;
  26         size_t offset;
  27         unsigned int size;
  28         const char printhex;
  29 };
  30
  31 static unsigned int picos_to_mhz(unsigned int picos)
  32 {
  33         return 1000000 / picos;
  34 }
  35
  36 static void print_option_table(const struct options_string *table,
  37                          int table_size,
  38                          const void *base)
  39 {
  40         unsigned int i;
  41         unsigned int *ptr;
  42         unsigned long long *ptr_l;
  43
  44         for (i = 0; i < table_size; i++) {
  45                 switch (table[i].size) {
  46                 case 4:
  47                         ptr = (unsigned int *) (base + table[i].offset);
  48                         if (table[i].printhex) {
  49                                 printf("%s = 0x%08X\n",
  50                                         table[i].option_name, *ptr);
  51                         } else {
  52                                 printf("%s = %u\n",
  53                                         table[i].option_name, *ptr);
  54                         }
  55                         break;
  56                 case 8:
  57                         ptr_l = (unsigned long long *) (base + table[i].offset);
  58                         printf("%s = %llu\n",
  59                                 table[i].option_name, *ptr_l);
  60                         break;
  61                 default:
  62                         printf("Unrecognized size!\n");
  63                         break;
  64                 }
  65         }
  66 }
  67
  68 static int handle_option_table(const struct options_string *table,
  69                          int table_size,
  70                          void *base,
  71                          const char *opt,
  72                          const char *val)
  73 {
  74         unsigned int i;
  75         unsigned int value, *ptr;
  76         unsigned long long value_l, *ptr_l;
  77
  78         for (i = 0; i < table_size; i++) {
  79                 if (strcmp(table[i].option_name, opt) != 0)
  80                         continue;
  81                 switch (table[i].size) {
  82                 case 4:
  83                         value = simple_strtoul(val, NULL, 0);
  84                         ptr = base + table[i].offset;
  85                         *ptr = value;
  86                         break;
  87                 case 8:
  88                         value_l = simple_strtoull(val, NULL, 0);
  89                         ptr_l = base + table[i].offset;
  90                         *ptr_l = value_l;
  91                         break;
  92                 default:
  93                         printf("Unrecognized size!\n");
  94                         break;
  95                 }
  96                 return 1;
  97         }
  98
  99         return 0;
 100 }
 101
 102 static void fsl_ddr_generic_edit(void *pdata,
 103                            void *pend,
 104                            unsigned int element_size,
 105                            unsigned int element_num,
 106                            unsigned int value)
 107 {
 108         char *pcdata = (char *)pdata;           /* BIG ENDIAN ONLY */
 109
 110         pcdata += element_num * element_size;
 111         if ((pcdata + element_size) > (char *) pend) {
 112                 printf("trying to write past end of data\n");
 113                 return;
 114         }
 115
 116         switch (element_size) {
 117         case 1:
 118                 __raw_writeb(value, pcdata);
 119                 break;
 120         case 2:
 121                 __raw_writew(value, pcdata);
 122                 break;
 123         case 4:
 124                 __raw_writel(value, pcdata);
 125                 break;
 126         default:
 127                 printf("unexpected element size %u\n", element_size);
 128                 break;
 129         }
 130 }
 131
 132 static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
 133                        unsigned int ctrl_num,
 134                        unsigned int dimm_num,
 135                        unsigned int element_num,
 136                        unsigned int value)
 137 {
 138         generic_spd_eeprom_t *pspd;
 139
 140         pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
 141         fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
 142 }
 143
 144 #define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
 145         sizeof((common_timing_params_t *)0)->x, 0}
 146
 147 static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 148                                         unsigned int ctrl_num,
 149                                         const char *optname_str,
 150                                         const char *value_str)
 151 {
 152         common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
 153
 154         static const struct options_string options[] = {
 155                 COMMON_TIMING(tckmin_x_ps),
 156                 COMMON_TIMING(tckmax_ps),
 157                 COMMON_TIMING(taamin_ps),
 158                 COMMON_TIMING(trcd_ps),
 159                 COMMON_TIMING(trp_ps),
 160                 COMMON_TIMING(tras_ps),
 161
 162 #ifdef CONFIG_SYS_FSL_DDR4
 163                 COMMON_TIMING(trfc1_ps),
 164                 COMMON_TIMING(trfc2_ps),
 165                 COMMON_TIMING(trfc4_ps),
 166                 COMMON_TIMING(trrds_ps),
 167                 COMMON_TIMING(trrdl_ps),
 168                 COMMON_TIMING(tccdl_ps),
 169 #else
 170                 COMMON_TIMING(twtr_ps),
 171                 COMMON_TIMING(trfc_ps),
 172                 COMMON_TIMING(trrd_ps),
 173                 COMMON_TIMING(trtp_ps),
 174 #endif
 175                 COMMON_TIMING(twr_ps),
 176                 COMMON_TIMING(trc_ps),
 177                 COMMON_TIMING(refresh_rate_ps),
 178                 COMMON_TIMING(extended_op_srt),
 179 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 180                 COMMON_TIMING(tis_ps),
 181                 COMMON_TIMING(tih_ps),
 182                 COMMON_TIMING(tds_ps),
 183                 COMMON_TIMING(tdh_ps),
 184                 COMMON_TIMING(tdqsq_max_ps),
 185                 COMMON_TIMING(tqhs_ps),
 186 #endif
 187                 COMMON_TIMING(ndimms_present),
 188                 COMMON_TIMING(lowest_common_spd_caslat),
 189                 COMMON_TIMING(highest_common_derated_caslat),
 190                 COMMON_TIMING(additive_latency),
 191                 COMMON_TIMING(all_dimms_burst_lengths_bitmask),
 192                 COMMON_TIMING(all_dimms_registered),
 193                 COMMON_TIMING(all_dimms_unbuffered),
 194                 COMMON_TIMING(all_dimms_ecc_capable),
 195                 COMMON_TIMING(total_mem),
 196                 COMMON_TIMING(base_address),
 197         };
 198         static const unsigned int n_opts = ARRAY_SIZE(options);
 199
 200         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 201                 return;
 202
 203         printf("Error: couldn't find option string %s\n", optname_str);
 204 }
 205
 206 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
 207         sizeof((dimm_params_t *)0)->x, 0}
 208 #define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \
 209         sizeof((dimm_params_t *)0)->x, 1}
 210
 211 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 212                                    unsigned int ctrl_num,
 213                                    unsigned int dimm_num,
 214                                    const char *optname_str,
 215                                    const char *value_str)
 216 {
 217         dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
 218
 219         static const struct options_string options[] = {
 220                 DIMM_PARM(n_ranks),
 221                 DIMM_PARM(data_width),
 222                 DIMM_PARM(primary_sdram_width),
 223                 DIMM_PARM(ec_sdram_width),
 224                 DIMM_PARM(registered_dimm),
 225                 DIMM_PARM(mirrored_dimm),
 226                 DIMM_PARM(device_width),
 227
 228                 DIMM_PARM(n_row_addr),
 229                 DIMM_PARM(n_col_addr),
 230                 DIMM_PARM(edc_config),
 231 #ifdef CONFIG_SYS_FSL_DDR4
 232                 DIMM_PARM(bank_addr_bits),
 233                 DIMM_PARM(bank_group_bits),
 234 #else
 235                 DIMM_PARM(n_banks_per_sdram_device),
 236 #endif
 237                 DIMM_PARM(burst_lengths_bitmask),
 238                 DIMM_PARM(row_density),
 239
 240                 DIMM_PARM(tckmin_x_ps),
 241                 DIMM_PARM(tckmin_x_minus_1_ps),
 242                 DIMM_PARM(tckmin_x_minus_2_ps),
 243                 DIMM_PARM(tckmax_ps),
 244
 245                 DIMM_PARM(caslat_x),
 246                 DIMM_PARM(caslat_x_minus_1),
 247                 DIMM_PARM(caslat_x_minus_2),
 248
 249                 DIMM_PARM(caslat_lowest_derated),
 250
 251                 DIMM_PARM(trcd_ps),
 252                 DIMM_PARM(trp_ps),
 253                 DIMM_PARM(tras_ps),
 254 #ifdef CONFIG_SYS_FSL_DDR4
 255                 DIMM_PARM(trfc1_ps),
 256                 DIMM_PARM(trfc2_ps),
 257                 DIMM_PARM(trfc4_ps),
 258                 DIMM_PARM(trrds_ps),
 259                 DIMM_PARM(trrdl_ps),
 260                 DIMM_PARM(tccdl_ps),
 261 #else
 262                 DIMM_PARM(twr_ps),
 263                 DIMM_PARM(twtr_ps),
 264                 DIMM_PARM(trfc_ps),
 265                 DIMM_PARM(trrd_ps),
 266                 DIMM_PARM(trtp_ps),
 267 #endif
 268                 DIMM_PARM(trc_ps),
 269                 DIMM_PARM(refresh_rate_ps),
 270                 DIMM_PARM(extended_op_srt),
 271
 272 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 273                 DIMM_PARM(tis_ps),
 274                 DIMM_PARM(tih_ps),
 275                 DIMM_PARM(tds_ps),
 276                 DIMM_PARM(tdh_ps),
 277                 DIMM_PARM(tdqsq_max_ps),
 278                 DIMM_PARM(tqhs_ps),
 279 #endif
 280 #ifdef CONFIG_SYS_FSL_DDR4
 281                 DIMM_PARM_HEX(dq_mapping[0]),
 282                 DIMM_PARM_HEX(dq_mapping[1]),
 283                 DIMM_PARM_HEX(dq_mapping[2]),
 284                 DIMM_PARM_HEX(dq_mapping[3]),
 285                 DIMM_PARM_HEX(dq_mapping[4]),
 286                 DIMM_PARM_HEX(dq_mapping[5]),
 287                 DIMM_PARM_HEX(dq_mapping[6]),
 288                 DIMM_PARM_HEX(dq_mapping[7]),
 289                 DIMM_PARM_HEX(dq_mapping[8]),
 290                 DIMM_PARM_HEX(dq_mapping[9]),
 291                 DIMM_PARM_HEX(dq_mapping[10]),
 292                 DIMM_PARM_HEX(dq_mapping[11]),
 293                 DIMM_PARM_HEX(dq_mapping[12]),
 294                 DIMM_PARM_HEX(dq_mapping[13]),
 295                 DIMM_PARM_HEX(dq_mapping[14]),
 296                 DIMM_PARM_HEX(dq_mapping[15]),
 297                 DIMM_PARM_HEX(dq_mapping[16]),
 298                 DIMM_PARM_HEX(dq_mapping[17]),
 299                 DIMM_PARM(dq_mapping_ors),
 300 #endif
 301                 DIMM_PARM(rank_density),
 302                 DIMM_PARM(capacity),
 303                 DIMM_PARM(base_address),
 304         };
 305
 306         static const unsigned int n_opts = ARRAY_SIZE(options);
 307
 308         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 309                 return;
 310
 311         printf("couldn't find option string %s\n", optname_str);
 312 }
 313
 314 static void print_dimm_parameters(const dimm_params_t *pdimm)
 315 {
 316         static const struct options_string options[] = {
 317                 DIMM_PARM(n_ranks),
 318                 DIMM_PARM(data_width),
 319                 DIMM_PARM(primary_sdram_width),
 320                 DIMM_PARM(ec_sdram_width),
 321                 DIMM_PARM(registered_dimm),
 322                 DIMM_PARM(mirrored_dimm),
 323                 DIMM_PARM(device_width),
 324
 325                 DIMM_PARM(n_row_addr),
 326                 DIMM_PARM(n_col_addr),
 327                 DIMM_PARM(edc_config),
 328 #ifdef CONFIG_SYS_FSL_DDR4
 329                 DIMM_PARM(bank_addr_bits),
 330                 DIMM_PARM(bank_group_bits),
 331 #else
 332                 DIMM_PARM(n_banks_per_sdram_device),
 333 #endif
 334
 335                 DIMM_PARM(tckmin_x_ps),
 336                 DIMM_PARM(tckmin_x_minus_1_ps),
 337                 DIMM_PARM(tckmin_x_minus_2_ps),
 338                 DIMM_PARM(tckmax_ps),
 339
 340                 DIMM_PARM(caslat_x),
 341                 DIMM_PARM_HEX(caslat_x),
 342                 DIMM_PARM(taa_ps),
 343                 DIMM_PARM(caslat_x_minus_1),
 344                 DIMM_PARM(caslat_x_minus_2),
 345                 DIMM_PARM(caslat_lowest_derated),
 346
 347                 DIMM_PARM(trcd_ps),
 348                 DIMM_PARM(trp_ps),
 349                 DIMM_PARM(tras_ps),
 350 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 351                 DIMM_PARM(tfaw_ps),
 352 #endif
 353 #ifdef CONFIG_SYS_FSL_DDR4
 354                 DIMM_PARM(trfc1_ps),
 355                 DIMM_PARM(trfc2_ps),
 356                 DIMM_PARM(trfc4_ps),
 357                 DIMM_PARM(trrds_ps),
 358                 DIMM_PARM(trrdl_ps),
 359                 DIMM_PARM(tccdl_ps),
 360 #else
 361                 DIMM_PARM(twr_ps),
 362                 DIMM_PARM(twtr_ps),
 363                 DIMM_PARM(trfc_ps),
 364                 DIMM_PARM(trrd_ps),
 365                 DIMM_PARM(trtp_ps),
 366 #endif
 367                 DIMM_PARM(trc_ps),
 368                 DIMM_PARM(refresh_rate_ps),
 369
 370 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 371                 DIMM_PARM(tis_ps),
 372                 DIMM_PARM(tih_ps),
 373                 DIMM_PARM(tds_ps),
 374                 DIMM_PARM(tdh_ps),
 375                 DIMM_PARM(tdqsq_max_ps),
 376                 DIMM_PARM(tqhs_ps),
 377 #endif
 378 #ifdef CONFIG_SYS_FSL_DDR4
 379                 DIMM_PARM_HEX(dq_mapping[0]),
 380                 DIMM_PARM_HEX(dq_mapping[1]),
 381                 DIMM_PARM_HEX(dq_mapping[2]),
 382                 DIMM_PARM_HEX(dq_mapping[3]),
 383                 DIMM_PARM_HEX(dq_mapping[4]),
 384                 DIMM_PARM_HEX(dq_mapping[5]),
 385                 DIMM_PARM_HEX(dq_mapping[6]),
 386                 DIMM_PARM_HEX(dq_mapping[7]),
 387                 DIMM_PARM_HEX(dq_mapping[8]),
 388                 DIMM_PARM_HEX(dq_mapping[9]),
 389                 DIMM_PARM_HEX(dq_mapping[10]),
 390                 DIMM_PARM_HEX(dq_mapping[11]),
 391                 DIMM_PARM_HEX(dq_mapping[12]),
 392                 DIMM_PARM_HEX(dq_mapping[13]),
 393                 DIMM_PARM_HEX(dq_mapping[14]),
 394                 DIMM_PARM_HEX(dq_mapping[15]),
 395                 DIMM_PARM_HEX(dq_mapping[16]),
 396                 DIMM_PARM_HEX(dq_mapping[17]),
 397                 DIMM_PARM(dq_mapping_ors),
 398 #endif
 399         };
 400         static const unsigned int n_opts = ARRAY_SIZE(options);
 401
 402         if (pdimm->n_ranks == 0) {
 403                 printf("DIMM not present\n");
 404                 return;
 405         }
 406         printf("DIMM organization parameters:\n");
 407         printf("module part name = %s\n", pdimm->mpart);
 408         printf("rank_density = %llu bytes (%llu megabytes)\n",
 409                pdimm->rank_density, pdimm->rank_density / 0x100000);
 410         printf("capacity = %llu bytes (%llu megabytes)\n",
 411                pdimm->capacity, pdimm->capacity / 0x100000);
 412         printf("burst_lengths_bitmask = %02X\n",
 413                pdimm->burst_lengths_bitmask);
 414         printf("base_addresss = %llu (%08llX %08llX)\n",
 415                pdimm->base_address,
 416                (pdimm->base_address >> 32),
 417                pdimm->base_address & 0xFFFFFFFF);
 418         print_option_table(options, n_opts, pdimm);
 419 }
 420
 421 static void print_lowest_common_dimm_parameters(
 422                 const common_timing_params_t *plcd_dimm_params)
 423 {
 424         static const struct options_string options[] = {
 425                 COMMON_TIMING(taamin_ps),
 426                 COMMON_TIMING(trcd_ps),
 427                 COMMON_TIMING(trp_ps),
 428                 COMMON_TIMING(tras_ps),
 429 #ifdef CONFIG_SYS_FSL_DDR4
 430                 COMMON_TIMING(trfc1_ps),
 431                 COMMON_TIMING(trfc2_ps),
 432                 COMMON_TIMING(trfc4_ps),
 433                 COMMON_TIMING(trrds_ps),
 434                 COMMON_TIMING(trrdl_ps),
 435                 COMMON_TIMING(tccdl_ps),
 436 #else
 437                 COMMON_TIMING(twtr_ps),
 438                 COMMON_TIMING(trfc_ps),
 439                 COMMON_TIMING(trrd_ps),
 440                 COMMON_TIMING(trtp_ps),
 441 #endif
 442                 COMMON_TIMING(twr_ps),
 443                 COMMON_TIMING(trc_ps),
 444                 COMMON_TIMING(refresh_rate_ps),
 445                 COMMON_TIMING(extended_op_srt),
 446 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 447                 COMMON_TIMING(tis_ps),
 448                 COMMON_TIMING(tih_ps),
 449                 COMMON_TIMING(tds_ps),
 450                 COMMON_TIMING(tdh_ps),
 451                 COMMON_TIMING(tdqsq_max_ps),
 452                 COMMON_TIMING(tqhs_ps),
 453 #endif
 454                 COMMON_TIMING(lowest_common_spd_caslat),
 455                 COMMON_TIMING(highest_common_derated_caslat),
 456                 COMMON_TIMING(additive_latency),
 457                 COMMON_TIMING(ndimms_present),
 458                 COMMON_TIMING(all_dimms_registered),
 459                 COMMON_TIMING(all_dimms_unbuffered),
 460                 COMMON_TIMING(all_dimms_ecc_capable),
 461         };
 462         static const unsigned int n_opts = ARRAY_SIZE(options);
 463
 464         /* Clock frequencies */
 465         printf("tckmin_x_ps = %u (%u MHz)\n",
 466                plcd_dimm_params->tckmin_x_ps,
 467                picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
 468         printf("tckmax_ps = %u (%u MHz)\n",
 469                plcd_dimm_params->tckmax_ps,
 470                picos_to_mhz(plcd_dimm_params->tckmax_ps));
 471         printf("all_dimms_burst_lengths_bitmask = %02X\n",
 472                plcd_dimm_params->all_dimms_burst_lengths_bitmask);
 473
 474         print_option_table(options, n_opts, plcd_dimm_params);
 475
 476         printf("total_mem = %llu (%llu megabytes)\n",
 477                plcd_dimm_params->total_mem,
 478                plcd_dimm_params->total_mem / 0x100000);
 479         printf("base_address = %llu (%llu megabytes)\n",
 480                plcd_dimm_params->base_address,
 481                plcd_dimm_params->base_address / 0x100000);
 482 }
 483
 484 #define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
 485         sizeof((memctl_options_t *)0)->x, 0}
 486 #define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
 487         offsetof(memctl_options_t, cs_local_opts[x].y), \
 488         sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
 489
 490 static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 491                            unsigned int ctl_num,
 492                            const char *optname_str,
 493                            const char *value_str)
 494 {
 495         memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
 496         /*
 497          * This array all on the stack and *computed* each time this
 498          * function is rung.
 499          */
 500         static const struct options_string options[] = {
 501                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 502                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 503 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 504                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 505                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 506 #endif
 507 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 508                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 509                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 510 #endif
 511 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 512                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 513                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 514 #endif
 515 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 516                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 517                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 518 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 519                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 520                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 521 #endif
 522 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 523                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 524                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 525 #endif
 526 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 527                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 528                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 529 #endif
 530 #endif
 531                 CTRL_OPTIONS(memctl_interleaving),
 532                 CTRL_OPTIONS(memctl_interleaving_mode),
 533                 CTRL_OPTIONS(ba_intlv_ctl),
 534                 CTRL_OPTIONS(ecc_mode),
 535                 CTRL_OPTIONS(ecc_init_using_memctl),
 536                 CTRL_OPTIONS(dqs_config),
 537                 CTRL_OPTIONS(self_refresh_in_sleep),
 538                 CTRL_OPTIONS(dynamic_power),
 539                 CTRL_OPTIONS(data_bus_width),
 540                 CTRL_OPTIONS(burst_length),
 541                 CTRL_OPTIONS(cas_latency_override),
 542                 CTRL_OPTIONS(cas_latency_override_value),
 543                 CTRL_OPTIONS(use_derated_caslat),
 544                 CTRL_OPTIONS(additive_latency_override),
 545                 CTRL_OPTIONS(additive_latency_override_value),
 546                 CTRL_OPTIONS(clk_adjust),
 547                 CTRL_OPTIONS(cpo_override),
 548                 CTRL_OPTIONS(write_data_delay),
 549                 CTRL_OPTIONS(half_strength_driver_enable),
 550
 551                 /*
 552                  * These can probably be changed to 2T_EN and 3T_EN
 553                  * (using a leading numerical character) without problem
 554                  */
 555                 CTRL_OPTIONS(twot_en),
 556                 CTRL_OPTIONS(threet_en),
 557                 CTRL_OPTIONS(ap_en),
 558                 CTRL_OPTIONS(x4_en),
 559                 CTRL_OPTIONS(bstopre),
 560                 CTRL_OPTIONS(wrlvl_override),
 561                 CTRL_OPTIONS(wrlvl_sample),
 562                 CTRL_OPTIONS(wrlvl_start),
 563                 CTRL_OPTIONS(cswl_override),
 564                 CTRL_OPTIONS(rcw_override),
 565                 CTRL_OPTIONS(rcw_1),
 566                 CTRL_OPTIONS(rcw_2),
 567                 CTRL_OPTIONS(ddr_cdr1),
 568                 CTRL_OPTIONS(ddr_cdr2),
 569                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 570                 CTRL_OPTIONS(trwt_override),
 571                 CTRL_OPTIONS(trwt),
 572                 CTRL_OPTIONS(rtt_override),
 573                 CTRL_OPTIONS(rtt_override_value),
 574                 CTRL_OPTIONS(rtt_wr_override_value),
 575         };
 576
 577         static const unsigned int n_opts = ARRAY_SIZE(options);
 578
 579         if (handle_option_table(options, n_opts, p,
 580                                         optname_str, value_str))
 581                 return;
 582
 583         printf("couldn't find option string %s\n", optname_str);
 584 }
 585
 586 #define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
 587         sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
 588 #define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
 589         offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
 590         sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
 591
 592 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 593 {
 594         unsigned int i;
 595         static const struct options_string options[] = {
 596                 CFG_REGS_CS(0, bnds),
 597                 CFG_REGS_CS(0, config),
 598                 CFG_REGS_CS(0, config_2),
 599 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 600                 CFG_REGS_CS(1, bnds),
 601                 CFG_REGS_CS(1, config),
 602                 CFG_REGS_CS(1, config_2),
 603 #endif
 604 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 605                 CFG_REGS_CS(2, bnds),
 606                 CFG_REGS_CS(2, config),
 607                 CFG_REGS_CS(2, config_2),
 608 #endif
 609 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 610                 CFG_REGS_CS(3, bnds),
 611                 CFG_REGS_CS(3, config),
 612                 CFG_REGS_CS(3, config_2),
 613 #endif
 614                 CFG_REGS(timing_cfg_3),
 615                 CFG_REGS(timing_cfg_0),
 616                 CFG_REGS(timing_cfg_1),
 617                 CFG_REGS(timing_cfg_2),
 618                 CFG_REGS(ddr_sdram_cfg),
 619                 CFG_REGS(ddr_sdram_cfg_2),
 620                 CFG_REGS(ddr_sdram_cfg_3),
 621                 CFG_REGS(ddr_sdram_mode),
 622                 CFG_REGS(ddr_sdram_mode_2),
 623                 CFG_REGS(ddr_sdram_mode_3),
 624                 CFG_REGS(ddr_sdram_mode_4),
 625                 CFG_REGS(ddr_sdram_mode_5),
 626                 CFG_REGS(ddr_sdram_mode_6),
 627                 CFG_REGS(ddr_sdram_mode_7),
 628                 CFG_REGS(ddr_sdram_mode_8),
 629 #ifdef CONFIG_SYS_FSL_DDR4
 630                 CFG_REGS(ddr_sdram_mode_9),
 631                 CFG_REGS(ddr_sdram_mode_10),
 632                 CFG_REGS(ddr_sdram_mode_11),
 633                 CFG_REGS(ddr_sdram_mode_12),
 634                 CFG_REGS(ddr_sdram_mode_13),
 635                 CFG_REGS(ddr_sdram_mode_14),
 636                 CFG_REGS(ddr_sdram_mode_15),
 637                 CFG_REGS(ddr_sdram_mode_16),
 638 #endif
 639                 CFG_REGS(ddr_sdram_interval),
 640                 CFG_REGS(ddr_data_init),
 641                 CFG_REGS(ddr_sdram_clk_cntl),
 642                 CFG_REGS(ddr_init_addr),
 643                 CFG_REGS(ddr_init_ext_addr),
 644                 CFG_REGS(timing_cfg_4),
 645                 CFG_REGS(timing_cfg_5),
 646 #ifdef CONFIG_SYS_FSL_DDR4
 647                 CFG_REGS(timing_cfg_6),
 648                 CFG_REGS(timing_cfg_7),
 649                 CFG_REGS(timing_cfg_8),
 650                 CFG_REGS(timing_cfg_9),
 651 #endif
 652                 CFG_REGS(ddr_zq_cntl),
 653                 CFG_REGS(ddr_wrlvl_cntl),
 654                 CFG_REGS(ddr_wrlvl_cntl_2),
 655                 CFG_REGS(ddr_wrlvl_cntl_3),
 656                 CFG_REGS(ddr_sr_cntr),
 657                 CFG_REGS(ddr_sdram_rcw_1),
 658                 CFG_REGS(ddr_sdram_rcw_2),
 659                 CFG_REGS(ddr_cdr1),
 660                 CFG_REGS(ddr_cdr2),
 661                 CFG_REGS(dq_map_0),
 662                 CFG_REGS(dq_map_1),
 663                 CFG_REGS(dq_map_2),
 664                 CFG_REGS(dq_map_3),
 665                 CFG_REGS(err_disable),
 666                 CFG_REGS(err_int_en),
 667                 CFG_REGS(ddr_eor),
 668         };
 669         static const unsigned int n_opts = ARRAY_SIZE(options);
 670
 671         print_option_table(options, n_opts, ddr);
 672
 673         for (i = 0; i < 64; i++)
 674                 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
 675 }
 676
 677 static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 678                         unsigned int ctrl_num,
 679                         const char *regname,
 680                         const char *value_str)
 681 {
 682         unsigned int i;
 683         fsl_ddr_cfg_regs_t *ddr;
 684         char buf[20];
 685         static const struct options_string options[] = {
 686                 CFG_REGS_CS(0, bnds),
 687                 CFG_REGS_CS(0, config),
 688                 CFG_REGS_CS(0, config_2),
 689 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 690                 CFG_REGS_CS(1, bnds),
 691                 CFG_REGS_CS(1, config),
 692                 CFG_REGS_CS(1, config_2),
 693 #endif
 694 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 695                 CFG_REGS_CS(2, bnds),
 696                 CFG_REGS_CS(2, config),
 697                 CFG_REGS_CS(2, config_2),
 698 #endif
 699 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 700                 CFG_REGS_CS(3, bnds),
 701                 CFG_REGS_CS(3, config),
 702                 CFG_REGS_CS(3, config_2),
 703 #endif
 704                 CFG_REGS(timing_cfg_3),
 705                 CFG_REGS(timing_cfg_0),
 706                 CFG_REGS(timing_cfg_1),
 707                 CFG_REGS(timing_cfg_2),
 708                 CFG_REGS(ddr_sdram_cfg),
 709                 CFG_REGS(ddr_sdram_cfg_2),
 710                 CFG_REGS(ddr_sdram_cfg_3),
 711                 CFG_REGS(ddr_sdram_mode),
 712                 CFG_REGS(ddr_sdram_mode_2),
 713                 CFG_REGS(ddr_sdram_mode_3),
 714                 CFG_REGS(ddr_sdram_mode_4),
 715                 CFG_REGS(ddr_sdram_mode_5),
 716                 CFG_REGS(ddr_sdram_mode_6),
 717                 CFG_REGS(ddr_sdram_mode_7),
 718                 CFG_REGS(ddr_sdram_mode_8),
 719 #ifdef CONFIG_SYS_FSL_DDR4
 720                 CFG_REGS(ddr_sdram_mode_9),
 721                 CFG_REGS(ddr_sdram_mode_10),
 722                 CFG_REGS(ddr_sdram_mode_11),
 723                 CFG_REGS(ddr_sdram_mode_12),
 724                 CFG_REGS(ddr_sdram_mode_13),
 725                 CFG_REGS(ddr_sdram_mode_14),
 726                 CFG_REGS(ddr_sdram_mode_15),
 727                 CFG_REGS(ddr_sdram_mode_16),
 728 #endif
 729                 CFG_REGS(ddr_sdram_interval),
 730                 CFG_REGS(ddr_data_init),
 731                 CFG_REGS(ddr_sdram_clk_cntl),
 732                 CFG_REGS(ddr_init_addr),
 733                 CFG_REGS(ddr_init_ext_addr),
 734                 CFG_REGS(timing_cfg_4),
 735                 CFG_REGS(timing_cfg_5),
 736 #ifdef CONFIG_SYS_FSL_DDR4
 737                 CFG_REGS(timing_cfg_6),
 738                 CFG_REGS(timing_cfg_7),
 739                 CFG_REGS(timing_cfg_8),
 740                 CFG_REGS(timing_cfg_9),
 741 #endif
 742                 CFG_REGS(ddr_zq_cntl),
 743                 CFG_REGS(ddr_wrlvl_cntl),
 744                 CFG_REGS(ddr_wrlvl_cntl_2),
 745                 CFG_REGS(ddr_wrlvl_cntl_3),
 746                 CFG_REGS(ddr_sr_cntr),
 747                 CFG_REGS(ddr_sdram_rcw_1),
 748                 CFG_REGS(ddr_sdram_rcw_2),
 749                 CFG_REGS(ddr_cdr1),
 750                 CFG_REGS(ddr_cdr2),
 751                 CFG_REGS(dq_map_0),
 752                 CFG_REGS(dq_map_1),
 753                 CFG_REGS(dq_map_2),
 754                 CFG_REGS(dq_map_3),
 755                 CFG_REGS(err_disable),
 756                 CFG_REGS(err_int_en),
 757                 CFG_REGS(ddr_sdram_rcw_2),
 758                 CFG_REGS(ddr_sdram_rcw_2),
 759                 CFG_REGS(ddr_eor),
 760         };
 761         static const unsigned int n_opts = ARRAY_SIZE(options);
 762
 763         debug("fsl_ddr_regs_edit: ctrl_num = %u, "
 764                 "regname = %s, value = %s\n",
 765                 ctrl_num, regname, value_str);
 766         if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
 767                 return;
 768
 769         ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
 770
 771         if (handle_option_table(options, n_opts, ddr, regname, value_str))
 772                 return;
 773
 774         for (i = 0; i < 64; i++) {
 775                 unsigned int value = simple_strtoul(value_str, NULL, 0);
 776                 sprintf(buf, "debug_%u", i + 1);
 777                 if (strcmp(buf, regname) == 0) {
 778                         ddr->debug[i] = value;
 779                         return;
 780                 }
 781         }
 782         printf("Error: couldn't find register string %s\n", regname);
 783 }
 784
 785 #define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
 786         sizeof((memctl_options_t *)0)->x, 1}
 787
 788 static void print_memctl_options(const memctl_options_t *popts)
 789 {
 790         static const struct options_string options[] = {
 791                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 792                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 793 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 794                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 795                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 796 #endif
 797 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 798                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 799                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 800 #endif
 801 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 802                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 803                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 804 #endif
 805 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 806                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 807                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 808 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 809                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 810                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 811 #endif
 812 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 813                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 814                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 815 #endif
 816 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 817                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 818                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 819 #endif
 820 #endif
 821                 CTRL_OPTIONS(memctl_interleaving),
 822                 CTRL_OPTIONS(memctl_interleaving_mode),
 823                 CTRL_OPTIONS_HEX(ba_intlv_ctl),
 824                 CTRL_OPTIONS(ecc_mode),
 825                 CTRL_OPTIONS(ecc_init_using_memctl),
 826                 CTRL_OPTIONS(dqs_config),
 827                 CTRL_OPTIONS(self_refresh_in_sleep),
 828                 CTRL_OPTIONS(dynamic_power),
 829                 CTRL_OPTIONS(data_bus_width),
 830                 CTRL_OPTIONS(burst_length),
 831                 CTRL_OPTIONS(cas_latency_override),
 832                 CTRL_OPTIONS(cas_latency_override_value),
 833                 CTRL_OPTIONS(use_derated_caslat),
 834                 CTRL_OPTIONS(additive_latency_override),
 835                 CTRL_OPTIONS(additive_latency_override_value),
 836                 CTRL_OPTIONS(clk_adjust),
 837                 CTRL_OPTIONS(cpo_override),
 838                 CTRL_OPTIONS(write_data_delay),
 839                 CTRL_OPTIONS(half_strength_driver_enable),
 840                 /*
 841                  * These can probably be changed to 2T_EN and 3T_EN
 842                  * (using a leading numerical character) without problem
 843                  */
 844                 CTRL_OPTIONS(twot_en),
 845                 CTRL_OPTIONS(threet_en),
 846                 CTRL_OPTIONS(registered_dimm_en),
 847                 CTRL_OPTIONS(mirrored_dimm),
 848                 CTRL_OPTIONS(ap_en),
 849                 CTRL_OPTIONS(x4_en),
 850                 CTRL_OPTIONS(bstopre),
 851                 CTRL_OPTIONS(wrlvl_override),
 852                 CTRL_OPTIONS(wrlvl_sample),
 853                 CTRL_OPTIONS(wrlvl_start),
 854                 CTRL_OPTIONS_HEX(cswl_override),
 855                 CTRL_OPTIONS(rcw_override),
 856                 CTRL_OPTIONS(rcw_1),
 857                 CTRL_OPTIONS(rcw_2),
 858                 CTRL_OPTIONS_HEX(ddr_cdr1),
 859                 CTRL_OPTIONS_HEX(ddr_cdr2),
 860                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 861                 CTRL_OPTIONS(trwt_override),
 862                 CTRL_OPTIONS(trwt),
 863                 CTRL_OPTIONS(rtt_override),
 864                 CTRL_OPTIONS(rtt_override_value),
 865                 CTRL_OPTIONS(rtt_wr_override_value),
 866         };
 867         static const unsigned int n_opts = ARRAY_SIZE(options);
 868
 869         print_option_table(options, n_opts, popts);
 870 }
 871
 872 #ifdef CONFIG_SYS_FSL_DDR1
 873 void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
 874 {
 875         unsigned int i;
 876
 877         printf("%-3d    : %02x %s\n", 0, spd->info_size,
 878                " spd->info_size,   *  0 # bytes written into serial memory *");
 879         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
 880                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
 881         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
 882                " spd->mem_type,    *  2 Fundamental memory type *");
 883         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
 884                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
 885         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
 886                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
 887         printf("%-3d    : %02x %s\n", 5, spd->nrows,
 888                " spd->nrows        *  5 # of DIMM Banks *");
 889         printf("%-3d    : %02x %s\n", 6, spd->dataw_lsb,
 890                " spd->dataw_lsb,   *  6 Data Width lsb of this assembly *");
 891         printf("%-3d    : %02x %s\n", 7, spd->dataw_msb,
 892                " spd->dataw_msb,   *  7 Data Width msb of this assembly *");
 893         printf("%-3d    : %02x %s\n", 8, spd->voltage,
 894                " spd->voltage,     *  8 Voltage intf std of this assembly *");
 895         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
 896                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
 897         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
 898                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
 899         printf("%-3d    : %02x %s\n", 11, spd->config,
 900                " spd->config,      * 11 DIMM Configuration type *");
 901         printf("%-3d    : %02x %s\n", 12, spd->refresh,
 902                " spd->refresh,     * 12 Refresh Rate/Type *");
 903         printf("%-3d    : %02x %s\n", 13, spd->primw,
 904                " spd->primw,       * 13 Primary SDRAM Width *");
 905         printf("%-3d    : %02x %s\n", 14, spd->ecw,
 906                " spd->ecw,         * 14 Error Checking SDRAM width *");
 907         printf("%-3d    : %02x %s\n", 15, spd->min_delay,
 908                " spd->min_delay,   * 15 Back to Back Random Access *");
 909         printf("%-3d    : %02x %s\n", 16, spd->burstl,
 910                " spd->burstl,      * 16 Burst Lengths Supported *");
 911         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
 912                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
 913         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
 914                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
 915         printf("%-3d    : %02x %s\n", 19, spd->cs_lat,
 916                " spd->cs_lat,      * 19 Chip Select Latency *");
 917         printf("%-3d    : %02x %s\n", 20, spd->write_lat,
 918                " spd->write_lat,   * 20 Write Latency/Recovery *");
 919         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
 920                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
 921         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
 922                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
 923         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
 924                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
 925         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
 926                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
 927         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
 928                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
 929         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
 930                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
 931         printf("%-3d    : %02x %s\n", 27, spd->trp,
 932                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
 933         printf("%-3d    : %02x %s\n", 28, spd->trrd,
 934                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
 935         printf("%-3d    : %02x %s\n", 29, spd->trcd,
 936                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
 937         printf("%-3d    : %02x %s\n", 30, spd->tras,
 938                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
 939         printf("%-3d    : %02x %s\n", 31, spd->bank_dens,
 940                " spd->bank_dens,   * 31 Density of each bank on module *");
 941         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
 942                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
 943         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
 944                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
 945         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
 946                " spd->data_setup,  * 34 Data signal input setup time *");
 947         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
 948                " spd->data_hold,   * 35 Data signal input hold time *");
 949         printf("%-3d    : %02x %s\n", 36, spd->res_36_40[0],
 950                " spd->res_36_40[0], * 36 Reserved / tWR *");
 951         printf("%-3d    : %02x %s\n", 37, spd->res_36_40[1],
 952                " spd->res_36_40[1], * 37 Reserved / tWTR *");
 953         printf("%-3d    : %02x %s\n", 38, spd->res_36_40[2],
 954                " spd->res_36_40[2], * 38 Reserved / tRTP *");
 955         printf("%-3d    : %02x %s\n", 39, spd->res_36_40[3],
 956                " spd->res_36_40[3], * 39 Reserved / mem_probe *");
 957         printf("%-3d    : %02x %s\n", 40, spd->res_36_40[4],
 958                " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
 959         printf("%-3d    : %02x %s\n", 41, spd->trc,
 960                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
 961         printf("%-3d    : %02x %s\n", 42, spd->trfc,
 962                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
 963         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
 964                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
 965         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
 966                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
 967         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
 968                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
 969         printf("%-3d    : %02x %s\n", 46, spd->res_46,
 970                " spd->res_46,  * 46 Reserved/ PLL Relock time *");
 971         printf("%-3d    : %02x %s\n", 47, spd->dimm_height,
 972                " spd->dimm_height  * 47 SDRAM DIMM Height *");
 973
 974         printf("%-3d-%3d: ",  48, 61);
 975
 976         for (i = 0; i < 14; i++)
 977                 printf("%02x", spd->res_48_61[i]);
 978
 979         printf(" * 48-61 IDD in SPD and Reserved space *\n");
 980
 981         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
 982                " spd->spd_rev,     * 62 SPD Data Revision Code *");
 983         printf("%-3d    : %02x %s\n", 63, spd->cksum,
 984                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
 985         printf("%-3d-%3d: ",  64, 71);
 986
 987         for (i = 0; i < 8; i++)
 988                 printf("%02x", spd->mid[i]);
 989
 990         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
 991         printf("%-3d    : %02x %s\n", 72, spd->mloc,
 992                " spd->mloc,        * 72 Manufacturing Location *");
 993
 994         printf("%-3d-%3d: >>",  73, 90);
 995
 996         for (i = 0; i < 18; i++)
 997                 printf("%c", spd->mpart[i]);
 998
 999         printf("<<* 73 Manufacturer's Part Number *\n");
1000
1001         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1002                "* 91 Revision Code *");
1003         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1004                "* 93 Manufacturing Date *");
1005         printf("%-3d-%3d: ", 95, 98);
1006
1007         for (i = 0; i < 4; i++)
1008                 printf("%02x", spd->sernum[i]);
1009
1010         printf("* 95 Assembly Serial Number *\n");
1011
1012         printf("%-3d-%3d: ", 99, 127);
1013
1014         for (i = 0; i < 27; i++)
1015                 printf("%02x", spd->mspec[i]);
1016
1017         printf("* 99 Manufacturer Specific Data *\n");
1018 }
1019 #endif
1020
1021 #ifdef CONFIG_SYS_FSL_DDR2
1022 void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
1023 {
1024         unsigned int i;
1025
1026         printf("%-3d    : %02x %s\n", 0, spd->info_size,
1027                " spd->info_size,   *  0 # bytes written into serial memory *");
1028         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
1029                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
1030         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
1031                " spd->mem_type,    *  2 Fundamental memory type *");
1032         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
1033                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
1034         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
1035                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
1036         printf("%-3d    : %02x %s\n", 5, spd->mod_ranks,
1037                " spd->mod_ranks    *  5 # of Module Rows on this assembly *");
1038         printf("%-3d    : %02x %s\n", 6, spd->dataw,
1039                " spd->dataw,       *  6 Data Width of this assembly *");
1040         printf("%-3d    : %02x %s\n", 7, spd->res_7,
1041                " spd->res_7,       *  7 Reserved *");
1042         printf("%-3d    : %02x %s\n", 8, spd->voltage,
1043                " spd->voltage,     *  8 Voltage intf std of this assembly *");
1044         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
1045                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
1046         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
1047                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
1048         printf("%-3d    : %02x %s\n", 11, spd->config,
1049                " spd->config,      * 11 DIMM Configuration type *");
1050         printf("%-3d    : %02x %s\n", 12, spd->refresh,
1051                " spd->refresh,     * 12 Refresh Rate/Type *");
1052         printf("%-3d    : %02x %s\n", 13, spd->primw,
1053                " spd->primw,       * 13 Primary SDRAM Width *");
1054         printf("%-3d    : %02x %s\n", 14, spd->ecw,
1055                " spd->ecw,         * 14 Error Checking SDRAM width *");
1056         printf("%-3d    : %02x %s\n", 15, spd->res_15,
1057                " spd->res_15,      * 15 Reserved *");
1058         printf("%-3d    : %02x %s\n", 16, spd->burstl,
1059                " spd->burstl,      * 16 Burst Lengths Supported *");
1060         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
1061                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
1062         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
1063                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
1064         printf("%-3d    : %02x %s\n", 19, spd->mech_char,
1065                " spd->mech_char,   * 19 Mechanical Characteristics *");
1066         printf("%-3d    : %02x %s\n", 20, spd->dimm_type,
1067                " spd->dimm_type,   * 20 DIMM type *");
1068         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
1069                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
1070         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
1071                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
1072         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
1073                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
1074         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
1075                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
1076         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
1077                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
1078         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
1079                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
1080         printf("%-3d    : %02x %s\n", 27, spd->trp,
1081                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
1082         printf("%-3d    : %02x %s\n", 28, spd->trrd,
1083                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
1084         printf("%-3d    : %02x %s\n", 29, spd->trcd,
1085                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
1086         printf("%-3d    : %02x %s\n", 30, spd->tras,
1087                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
1088         printf("%-3d    : %02x %s\n", 31, spd->rank_dens,
1089                " spd->rank_dens,   * 31 Density of each rank on module *");
1090         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
1091                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
1092         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
1093                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
1094         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
1095                " spd->data_setup,  * 34 Data signal input setup time *");
1096         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
1097                " spd->data_hold,   * 35 Data signal input hold time *");
1098         printf("%-3d    : %02x %s\n", 36, spd->twr,
1099                " spd->twr,         * 36 Write Recovery time tWR *");
1100         printf("%-3d    : %02x %s\n", 37, spd->twtr,
1101                " spd->twtr,        * 37 Int write to read delay tWTR *");
1102         printf("%-3d    : %02x %s\n", 38, spd->trtp,
1103                " spd->trtp,        * 38 Int read to precharge delay tRTP *");
1104         printf("%-3d    : %02x %s\n", 39, spd->mem_probe,
1105                " spd->mem_probe,   * 39 Mem analysis probe characteristics *");
1106         printf("%-3d    : %02x %s\n", 40, spd->trctrfc_ext,
1107                " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
1108         printf("%-3d    : %02x %s\n", 41, spd->trc,
1109                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
1110         printf("%-3d    : %02x %s\n", 42, spd->trfc,
1111                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
1112         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
1113                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
1114         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
1115                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
1116         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
1117                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
1118         printf("%-3d    : %02x %s\n", 46, spd->pll_relock,
1119                " spd->pll_relock,  * 46 PLL Relock time *");
1120         printf("%-3d    : %02x %s\n", 47, spd->t_casemax,
1121                " spd->t_casemax,    * 47 t_casemax *");
1122         printf("%-3d    : %02x %s\n", 48, spd->psi_ta_dram,
1123                " spd->psi_ta_dram,   * 48 Thermal Resistance of DRAM Package "
1124                "from Top (Case) to Ambient (Psi T-A DRAM) *");
1125         printf("%-3d    : %02x %s\n", 49, spd->dt0_mode,
1126                " spd->dt0_mode,    * 49 DRAM Case Temperature Rise from "
1127                "Ambient due to Activate-Precharge/Mode Bits "
1128                "(DT0/Mode Bits) *)");
1129         printf("%-3d    : %02x %s\n", 50, spd->dt2n_dt2q,
1130                " spd->dt2n_dt2q,   * 50 DRAM Case Temperature Rise from "
1131                "Ambient due to Precharge/Quiet Standby "
1132                "(DT2N/DT2Q) *");
1133         printf("%-3d    : %02x %s\n", 51, spd->dt2p,
1134                " spd->dt2p,        * 51 DRAM Case Temperature Rise from "
1135                "Ambient due to Precharge Power-Down (DT2P) *");
1136         printf("%-3d    : %02x %s\n", 52, spd->dt3n,
1137                " spd->dt3n,        * 52 DRAM Case Temperature Rise from "
1138                "Ambient due to Active Standby (DT3N) *");
1139         printf("%-3d    : %02x %s\n", 53, spd->dt3pfast,
1140                " spd->dt3pfast,    * 53 DRAM Case Temperature Rise from "
1141                "Ambient due to Active Power-Down with Fast PDN Exit "
1142                "(DT3Pfast) *");
1143         printf("%-3d    : %02x %s\n", 54, spd->dt3pslow,
1144                " spd->dt3pslow,    * 54 DRAM Case Temperature Rise from "
1145                "Ambient due to Active Power-Down with Slow PDN Exit "
1146                "(DT3Pslow) *");
1147         printf("%-3d    : %02x %s\n", 55, spd->dt4r_dt4r4w,
1148                " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
1149                "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
1150                "(DT4R/DT4R4W Mode Bit) *");
1151         printf("%-3d    : %02x %s\n", 56, spd->dt5b,
1152                " spd->dt5b,        * 56 DRAM Case Temperature Rise from "
1153                "Ambient due to Burst Refresh (DT5B) *");
1154         printf("%-3d    : %02x %s\n", 57, spd->dt7,
1155                " spd->dt7,         * 57 DRAM Case Temperature Rise from "
1156                "Ambient due to Bank Interleave Reads with "
1157                "Auto-Precharge (DT7) *");
1158         printf("%-3d    : %02x %s\n", 58, spd->psi_ta_pll,
1159                " spd->psi_ta_pll,    * 58 Thermal Resistance of PLL Package form"
1160                " Top (Case) to Ambient (Psi T-A PLL) *");
1161         printf("%-3d    : %02x %s\n", 59, spd->psi_ta_reg,
1162                " spd->psi_ta_reg,    * 59 Thermal Reisitance of Register Package"
1163                " from Top (Case) to Ambient (Psi T-A Register) *");
1164         printf("%-3d    : %02x %s\n", 60, spd->dtpllactive,
1165                " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1166                "Ambient due to PLL Active (DT PLL Active) *");
1167         printf("%-3d    : %02x %s\n", 61, spd->dtregact,
1168                " spd->dtregact,    "
1169                "* 61 Register Case Temperature Rise from Ambient due to "
1170                "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1171         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
1172                " spd->spd_rev,     * 62 SPD Data Revision Code *");
1173         printf("%-3d    : %02x %s\n", 63, spd->cksum,
1174                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
1175
1176         printf("%-3d-%3d: ",  64, 71);
1177
1178         for (i = 0; i < 8; i++)
1179                 printf("%02x", spd->mid[i]);
1180
1181         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1182
1183         printf("%-3d    : %02x %s\n", 72, spd->mloc,
1184                " spd->mloc,        * 72 Manufacturing Location *");
1185
1186         printf("%-3d-%3d: >>",  73, 90);
1187         for (i = 0; i < 18; i++)
1188                 printf("%c", spd->mpart[i]);
1189
1190
1191         printf("<<* 73 Manufacturer's Part Number *\n");
1192
1193         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1194                "* 91 Revision Code *");
1195         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1196                "* 93 Manufacturing Date *");
1197         printf("%-3d-%3d: ", 95, 98);
1198
1199         for (i = 0; i < 4; i++)
1200                 printf("%02x", spd->sernum[i]);
1201
1202         printf("* 95 Assembly Serial Number *\n");
1203
1204         printf("%-3d-%3d: ", 99, 127);
1205         for (i = 0; i < 27; i++)
1206                 printf("%02x", spd->mspec[i]);
1207
1208
1209         printf("* 99 Manufacturer Specific Data *\n");
1210 }
1211 #endif
1212
1213 #ifdef CONFIG_SYS_FSL_DDR3
1214 void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1215 {
1216         unsigned int i;
1217
1218         /* General Section: Bytes 0-59 */
1219
1220 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1221 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1222         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1223
1224         PRINT_NXS(0, spd->info_size_crc,
1225                 "info_size_crc  bytes written into serial memory, "
1226                 "CRC coverage");
1227         PRINT_NXS(1, spd->spd_rev,
1228                 "spd_rev        SPD Revision");
1229         PRINT_NXS(2, spd->mem_type,
1230                 "mem_type       Key Byte / DRAM Device Type");
1231         PRINT_NXS(3, spd->module_type,
1232                 "module_type    Key Byte / Module Type");
1233         PRINT_NXS(4, spd->density_banks,
1234                 "density_banks  SDRAM Density and Banks");
1235         PRINT_NXS(5, spd->addressing,
1236                 "addressing     SDRAM Addressing");
1237         PRINT_NXS(6, spd->module_vdd,
1238                 "module_vdd     Module Nominal Voltage, VDD");
1239         PRINT_NXS(7, spd->organization,
1240                 "organization   Module Organization");
1241         PRINT_NXS(8, spd->bus_width,
1242                 "bus_width      Module Memory Bus Width");
1243         PRINT_NXS(9, spd->ftb_div,
1244                 "ftb_div        Fine Timebase (FTB) Dividend / Divisor");
1245         PRINT_NXS(10, spd->mtb_dividend,
1246                 "mtb_dividend   Medium Timebase (MTB) Dividend");
1247         PRINT_NXS(11, spd->mtb_divisor,
1248                 "mtb_divisor    Medium Timebase (MTB) Divisor");
1249         PRINT_NXS(12, spd->tck_min,
1250                   "tck_min        SDRAM Minimum Cycle Time");
1251         PRINT_NXS(13, spd->res_13,
1252                 "res_13         Reserved");
1253         PRINT_NXS(14, spd->caslat_lsb,
1254                 "caslat_lsb     CAS Latencies Supported, LSB");
1255         PRINT_NXS(15, spd->caslat_msb,
1256                 "caslat_msb     CAS Latencies Supported, MSB");
1257         PRINT_NXS(16, spd->taa_min,
1258                   "taa_min        Min CAS Latency Time");
1259         PRINT_NXS(17, spd->twr_min,
1260                   "twr_min        Min Write REcovery Time");
1261         PRINT_NXS(18, spd->trcd_min,
1262                   "trcd_min       Min RAS# to CAS# Delay Time");
1263         PRINT_NXS(19, spd->trrd_min,
1264                   "trrd_min       Min Row Active to Row Active Delay Time");
1265         PRINT_NXS(20, spd->trp_min,
1266                   "trp_min        Min Row Precharge Delay Time");
1267         PRINT_NXS(21, spd->tras_trc_ext,
1268                   "tras_trc_ext   Upper Nibbles for tRAS and tRC");
1269         PRINT_NXS(22, spd->tras_min_lsb,
1270                   "tras_min_lsb   Min Active to Precharge Delay Time, LSB");
1271         PRINT_NXS(23, spd->trc_min_lsb,
1272                   "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1273         PRINT_NXS(24, spd->trfc_min_lsb,
1274                   "trfc_min_lsb   Min Refresh Recovery Delay Time LSB");
1275         PRINT_NXS(25, spd->trfc_min_msb,
1276                   "trfc_min_msb   Min Refresh Recovery Delay Time MSB");
1277         PRINT_NXS(26, spd->twtr_min,
1278                   "twtr_min Min Internal Write to Read Command Delay Time");
1279         PRINT_NXS(27, spd->trtp_min,
1280                   "trtp_min "
1281                   "Min Internal Read to Precharge Command Delay Time");
1282         PRINT_NXS(28, spd->tfaw_msb,
1283                   "tfaw_msb       Upper Nibble for tFAW");
1284         PRINT_NXS(29, spd->tfaw_min,
1285                   "tfaw_min       Min Four Activate Window Delay Time");
1286         PRINT_NXS(30, spd->opt_features,
1287                 "opt_features   SDRAM Optional Features");
1288         PRINT_NXS(31, spd->therm_ref_opt,
1289                 "therm_ref_opt  SDRAM Thermal and Refresh Opts");
1290         PRINT_NXS(32, spd->therm_sensor,
1291                 "therm_sensor  SDRAM Thermal Sensor");
1292         PRINT_NXS(33, spd->device_type,
1293                 "device_type  SDRAM Device Type");
1294         PRINT_NXS(34, spd->fine_tck_min,
1295                   "fine_tck_min  Fine offset for tCKmin");
1296         PRINT_NXS(35, spd->fine_taa_min,
1297                   "fine_taa_min  Fine offset for tAAmin");
1298         PRINT_NXS(36, spd->fine_trcd_min,
1299                   "fine_trcd_min Fine offset for tRCDmin");
1300         PRINT_NXS(37, spd->fine_trp_min,
1301                   "fine_trp_min  Fine offset for tRPmin");
1302         PRINT_NXS(38, spd->fine_trc_min,
1303                   "fine_trc_min  Fine offset for tRCmin");
1304
1305         printf("%-3d-%3d: ",  39, 59);  /* Reserved, General Section */
1306
1307         for (i = 39; i <= 59; i++)
1308                 printf("%02x ", spd->res_39_59[i - 39]);
1309
1310         puts("\n");
1311
1312         switch (spd->module_type) {
1313         case 0x02:  /* UDIMM */
1314         case 0x03:  /* SO-DIMM */
1315         case 0x04:  /* Micro-DIMM */
1316         case 0x06:  /* Mini-UDIMM */
1317                 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1318                         "mod_height    (Unbuffered) Module Nominal Height");
1319                 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1320                         "mod_thickness (Unbuffered) Module Maximum Thickness");
1321                 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1322                         "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1323                 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1324                         "addr_mapping  (Unbuffered) Address mapping from "
1325                         "Edge Connector to DRAM");
1326                 break;
1327         case 0x01:  /* RDIMM */
1328         case 0x05:  /* Mini-RDIMM */
1329                 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1330                         "mod_height    (Registered) Module Nominal Height");
1331                 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1332                         "mod_thickness (Registered) Module Maximum Thickness");
1333                 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1334                         "ref_raw_card  (Registered) Reference Raw Card Used");
1335                 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1336                         "modu_attr     (Registered) DIMM Module Attributes");
1337                 PRINT_NXS(64, spd->mod_section.registered.thermal,
1338                         "thermal       (Registered) Thermal Heat "
1339                         "Spreader Solution");
1340                 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1341                         "reg_id_lo     (Registered) Register Manufacturer ID "
1342                         "Code, LSB");
1343                 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1344                         "reg_id_hi     (Registered) Register Manufacturer ID "
1345                         "Code, MSB");
1346                 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1347                         "reg_rev       (Registered) Register "
1348                         "Revision Number");
1349                 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1350                         "reg_type      (Registered) Register Type");
1351                 for (i = 69; i <= 76; i++) {
1352                         printf("%-3d    : %02x rcw[%d]\n", i,
1353                                 spd->mod_section.registered.rcw[i-69], i-69);
1354                 }
1355                 break;
1356         default:
1357                 /* Module-specific Section, Unsupported Module Type */
1358                 printf("%-3d-%3d: ", 60, 116);
1359
1360                 for (i = 60; i <= 116; i++)
1361                         printf("%02x", spd->mod_section.uc[i - 60]);
1362
1363                 break;
1364         }
1365
1366         /* Unique Module ID: Bytes 117-125 */
1367         PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1368         PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1369         PRINT_NXS(119, spd->mloc,     "Mfg Location");
1370         PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1371
1372         printf("%-3d-%3d: ", 122, 125);
1373
1374         for (i = 122; i <= 125; i++)
1375                 printf("%02x ", spd->sernum[i - 122]);
1376         printf("   Module Serial Number\n");
1377
1378         /* CRC: Bytes 126-127 */
1379         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1380
1381         /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1382         printf("%-3d-%3d: ", 128, 145);
1383         for (i = 128; i <= 145; i++)
1384                 printf("%02x ", spd->mpart[i - 128]);
1385         printf("   Mfg's Module Part Number\n");
1386
1387         PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1388                 "Module Revision code");
1389
1390         PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1391         PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1392
1393         printf("%-3d-%3d: ", 150, 175);
1394         for (i = 150; i <= 175; i++)
1395                 printf("%02x ", spd->msd[i - 150]);
1396         printf("   Mfg's Specific Data\n");
1397
1398         printf("%-3d-%3d: ", 176, 255);
1399         for (i = 176; i <= 255; i++)
1400                 printf("%02x", spd->cust[i - 176]);
1401         printf("   Mfg's Specific Data\n");
1402
1403 }
1404 #endif
1405
1406 #ifdef CONFIG_SYS_FSL_DDR4
1407 void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
1408 {
1409         unsigned int i;
1410
1411         /* General Section: Bytes 0-127 */
1412
1413 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1414 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1415         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1416
1417         PRINT_NXS(0, spd->info_size_crc,
1418                   "info_size_crc  bytes written into serial memory, CRC coverage");
1419         PRINT_NXS(1, spd->spd_rev,
1420                   "spd_rev        SPD Revision");
1421         PRINT_NXS(2, spd->mem_type,
1422                   "mem_type       Key Byte / DRAM Device Type");
1423         PRINT_NXS(3, spd->module_type,
1424                   "module_type    Key Byte / Module Type");
1425         PRINT_NXS(4, spd->density_banks,
1426                   "density_banks  SDRAM Density and Banks");
1427         PRINT_NXS(5, spd->addressing,
1428                   "addressing     SDRAM Addressing");
1429         PRINT_NXS(6, spd->package_type,
1430                   "package_type   Package type");
1431         PRINT_NXS(7, spd->opt_feature,
1432                   "opt_feature    Optional features");
1433         PRINT_NXS(8, spd->thermal_ref,
1434                   "thermal_ref    Thermal and Refresh options");
1435         PRINT_NXS(9, spd->oth_opt_features,
1436                   "oth_opt_features Other SDRAM optional features");
1437         PRINT_NXS(10, spd->res_10,
1438                   "res_10         Reserved");
1439         PRINT_NXS(11, spd->module_vdd,
1440                   "module_vdd     Module Nominal Voltage, VDD");
1441         PRINT_NXS(12, spd->organization,
1442                   "organization Module Organization");
1443         PRINT_NXS(13, spd->bus_width,
1444                   "bus_width      Module Memory Bus Width");
1445         PRINT_NXS(14, spd->therm_sensor,
1446                   "therm_sensor   Module Thermal Sensor");
1447         PRINT_NXS(15, spd->ext_type,
1448                   "ext_type       Extended module type");
1449         PRINT_NXS(16, spd->res_16,
1450                   "res_16       Reserved");
1451         PRINT_NXS(17, spd->timebases,
1452                   "timebases    MTb and FTB");
1453         PRINT_NXS(18, spd->tck_min,
1454                   "tck_min      tCKAVGmin");
1455         PRINT_NXS(19, spd->tck_max,
1456                   "tck_max      TCKAVGmax");
1457         PRINT_NXS(20, spd->caslat_b1,
1458                   "caslat_b1    CAS latencies, 1st byte");
1459         PRINT_NXS(21, spd->caslat_b2,
1460                   "caslat_b2    CAS latencies, 2nd byte");
1461         PRINT_NXS(22, spd->caslat_b3,
1462                   "caslat_b3    CAS latencies, 3rd byte ");
1463         PRINT_NXS(23, spd->caslat_b4,
1464                   "caslat_b4    CAS latencies, 4th byte");
1465         PRINT_NXS(24, spd->taa_min,
1466                   "taa_min      Min CAS Latency Time");
1467         PRINT_NXS(25, spd->trcd_min,
1468                   "trcd_min     Min RAS# to CAS# Delay Time");
1469         PRINT_NXS(26, spd->trp_min,
1470                   "trp_min      Min Row Precharge Delay Time");
1471         PRINT_NXS(27, spd->tras_trc_ext,
1472                   "tras_trc_ext Upper Nibbles for tRAS and tRC");
1473         PRINT_NXS(28, spd->tras_min_lsb,
1474                   "tras_min_lsb tRASmin, lsb");
1475         PRINT_NXS(29, spd->trc_min_lsb,
1476                   "trc_min_lsb  tRCmin, lsb");
1477         PRINT_NXS(30, spd->trfc1_min_lsb,
1478                   "trfc1_min_lsb  Min Refresh Recovery Delay Time, LSB");
1479         PRINT_NXS(31, spd->trfc1_min_msb,
1480                   "trfc1_min_msb  Min Refresh Recovery Delay Time, MSB ");
1481         PRINT_NXS(32, spd->trfc2_min_lsb,
1482                   "trfc2_min_lsb  Min Refresh Recovery Delay Time, LSB");
1483         PRINT_NXS(33, spd->trfc2_min_msb,
1484                   "trfc2_min_msb  Min Refresh Recovery Delay Time, MSB");
1485         PRINT_NXS(34, spd->trfc4_min_lsb,
1486                   "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
1487         PRINT_NXS(35, spd->trfc4_min_msb,
1488                   "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
1489         PRINT_NXS(36, spd->tfaw_msb,
1490                   "tfaw_msb      Upper Nibble for tFAW");
1491         PRINT_NXS(37, spd->tfaw_min,
1492                   "tfaw_min      tFAW, lsb");
1493         PRINT_NXS(38, spd->trrds_min,
1494                   "trrds_min     tRRD_Smin, MTB");
1495         PRINT_NXS(39, spd->trrdl_min,
1496                   "trrdl_min     tRRD_Lmin, MTB");
1497         PRINT_NXS(40, spd->tccdl_min,
1498                   "tccdl_min     tCCS_Lmin, MTB");
1499
1500         printf("%-3d-%3d: ", 41, 59);  /* Reserved, General Section */
1501         for (i = 41; i <= 59; i++)
1502                 printf("%02x ", spd->res_41[i - 41]);
1503
1504         puts("\n");
1505         printf("%-3d-%3d: ", 60, 77);
1506         for (i = 60; i <= 77; i++)
1507                 printf("%02x ", spd->mapping[i - 60]);
1508         puts("   mapping[] Connector to SDRAM bit map\n");
1509
1510         PRINT_NXS(117, spd->fine_tccdl_min,
1511                   "fine_tccdl_min Fine offset for tCCD_Lmin");
1512         PRINT_NXS(118, spd->fine_trrdl_min,
1513                   "fine_trrdl_min Fine offset for tRRD_Lmin");
1514         PRINT_NXS(119, spd->fine_trrds_min,
1515                   "fine_trrds_min Fine offset for tRRD_Smin");
1516         PRINT_NXS(120, spd->fine_trc_min,
1517                   "fine_trc_min   Fine offset for tRCmin");
1518         PRINT_NXS(121, spd->fine_trp_min,
1519                   "fine_trp_min   Fine offset for tRPmin");
1520         PRINT_NXS(122, spd->fine_trcd_min,
1521                   "fine_trcd_min  Fine offset for tRCDmin");
1522         PRINT_NXS(123, spd->fine_taa_min,
1523                   "fine_taa_min   Fine offset for tAAmin");
1524         PRINT_NXS(124, spd->fine_tck_max,
1525                   "fine_tck_max   Fine offset for tCKAVGmax");
1526         PRINT_NXS(125, spd->fine_tck_min,
1527                   "fine_tck_min   Fine offset for tCKAVGmin");
1528
1529         /* CRC: Bytes 126-127 */
1530         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1531
1532         switch (spd->module_type) {
1533         case 0x02:  /* UDIMM */
1534         case 0x03:  /* SO-DIMM */
1535                 PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
1536                           "mod_height    (Unbuffered) Module Nominal Height");
1537                 PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
1538                           "mod_thickness (Unbuffered) Module Maximum Thickness");
1539                 PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
1540                           "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1541                 PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
1542                           "addr_mapping  (Unbuffered) Address mapping from Edge Connector to DRAM");
1543                 PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
1544                             spd->mod_section.unbuffered.crc[1], "  Module CRC");
1545                 break;
1546         case 0x01:  /* RDIMM */
1547                 PRINT_NXS(128, spd->mod_section.registered.mod_height,
1548                           "mod_height    (Registered) Module Nominal Height");
1549                 PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
1550                           "mod_thickness (Registered) Module Maximum Thickness");
1551                 PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
1552                           "ref_raw_card  (Registered) Reference Raw Card Used");
1553                 PRINT_NXS(131, spd->mod_section.registered.modu_attr,
1554                           "modu_attr     (Registered) DIMM Module Attributes");
1555                 PRINT_NXS(132, spd->mod_section.registered.thermal,
1556                           "thermal       (Registered) Thermal Heat Spreader Solution");
1557                 PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
1558                           "reg_id_lo     (Registered) Register Manufacturer ID Code, LSB");
1559                 PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
1560                           "reg_id_hi     (Registered) Register Manufacturer ID Code, MSB");
1561                 PRINT_NXS(135, spd->mod_section.registered.reg_rev,
1562                           "reg_rev       (Registered) Register Revision Number");
1563                 PRINT_NXS(136, spd->mod_section.registered.reg_map,
1564                           "reg_map       (Registered) Address mapping");
1565                 PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
1566                             spd->mod_section.registered.crc[1], "  Module CRC");
1567                 break;
1568         case 0x04:  /* LRDIMM */
1569                 PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
1570                           "mod_height    (Loadreduced) Module Nominal Height");
1571                 PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
1572                           "mod_thickness (Loadreduced) Module Maximum Thickness");
1573                 PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
1574                           "ref_raw_card  (Loadreduced) Reference Raw Card Used");
1575                 PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
1576                           "modu_attr     (Loadreduced) DIMM Module Attributes");
1577                 PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
1578                           "thermal       (Loadreduced) Thermal Heat Spreader Solution");
1579                 PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
1580                           "reg_id_lo     (Loadreduced) Register Manufacturer ID Code, LSB");
1581                 PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
1582                           "reg_id_hi     (Loadreduced) Register Manufacturer ID Code, MSB");
1583                 PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
1584                           "reg_rev       (Loadreduced) Register Revision Number");
1585                 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
1586                           "reg_map       (Loadreduced) Address mapping");
1587                 PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
1588                           "reg_drv       (Loadreduced) Reg output drive strength");
1589                 PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
1590                           "reg_drv_ck    (Loadreduced) Reg output drive strength for CK");
1591                 PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
1592                           "data_buf_rev  (Loadreduced) Data Buffer Revision Numbe");
1593                 PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
1594                           "vrefqe_r0     (Loadreduced) DRAM VrefDQ for Package Rank 0");
1595                 PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
1596                           "vrefqe_r1     (Loadreduced) DRAM VrefDQ for Package Rank 1");
1597                 PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
1598                           "vrefqe_r2     (Loadreduced) DRAM VrefDQ for Package Rank 2");
1599                 PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
1600                           "vrefqe_r3     (Loadreduced) DRAM VrefDQ for Package Rank 3");
1601                 PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
1602                           "data_intf     (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
1603                 PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
1604                           "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1605                 PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
1606                           "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1607                 PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
1608                           "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1609                 PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
1610                           "dram_drv      (Loadreduced) DRAM Drive Strength");
1611                 PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
1612                           "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1613                 PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
1614                           "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1615                 PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
1616                           "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1617                 PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
1618                           "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
1619                 PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
1620                           "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
1621                 PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
1622                           "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
1623                 PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
1624                             spd->mod_section.loadreduced.crc[1],
1625                             "  Module CRC");
1626                 break;
1627         default:
1628                 /* Module-specific Section, Unsupported Module Type */
1629                 printf("%-3d-%3d: ", 128, 255);
1630
1631                 for (i = 128; i <= 255; i++)
1632                         printf("%02x", spd->mod_section.uc[i - 128]);
1633
1634                 break;
1635         }
1636
1637         /* Unique Module ID: Bytes 320-383 */
1638         PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1639         PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1640         PRINT_NXS(322, spd->mloc,     "Mfg Location");
1641         PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
1642
1643         printf("%-3d-%3d: ", 325, 328);
1644
1645         for (i = 325; i <= 328; i++)
1646                 printf("%02x ", spd->sernum[i - 325]);
1647         printf("   Module Serial Number\n");
1648
1649         printf("%-3d-%3d: ", 329, 348);
1650         for (i = 329; i <= 348; i++)
1651                 printf("%02x ", spd->mpart[i - 329]);
1652         printf("   Mfg's Module Part Number\n");
1653
1654         PRINT_NXS(349, spd->mrev, "Module Revision code");
1655         PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1656         PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1657         PRINT_NXS(352, spd->stepping, "DRAM stepping");
1658
1659         printf("%-3d-%3d: ", 353, 381);
1660         for (i = 353; i <= 381; i++)
1661                 printf("%02x ", spd->msd[i - 353]);
1662         printf("   Mfg's Specific Data\n");
1663 }
1664 #endif
1665
1666 static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1667 {
1668 #if defined(CONFIG_SYS_FSL_DDR1)
1669         ddr1_spd_dump(spd);
1670 #elif defined(CONFIG_SYS_FSL_DDR2)
1671         ddr2_spd_dump(spd);
1672 #elif defined(CONFIG_SYS_FSL_DDR3)
1673         ddr3_spd_dump(spd);
1674 #elif defined(CONFIG_SYS_FSL_DDR4)
1675         ddr4_spd_dump(spd);
1676 #endif
1677 }
1678
1679 static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1680                         unsigned int ctrl_mask,
1681                         unsigned int dimm_mask,
1682                         unsigned int do_mask)
1683 {
1684         unsigned int i, j, retval;
1685
1686         /* STEP 1:  DIMM SPD data */
1687         if (do_mask & STEP_GET_SPD) {
1688                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1689                         if (!(ctrl_mask & (1 << i)))
1690                                 continue;
1691
1692                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1693                                 if (!(dimm_mask & (1 << j)))
1694                                         continue;
1695
1696                                 printf("SPD info:  Controller=%u "
1697                                                 "DIMM=%u\n", i, j);
1698                                 generic_spd_dump(
1699                                         &(pinfo->spd_installed_dimms[i][j]));
1700                                 printf("\n");
1701                         }
1702                         printf("\n");
1703                 }
1704                 printf("\n");
1705         }
1706
1707         /* STEP 2:  DIMM Parameters */
1708         if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1709                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1710                         if (!(ctrl_mask & (1 << i)))
1711                                 continue;
1712                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1713                                 if (!(dimm_mask & (1 << j)))
1714                                         continue;
1715                                 printf("DIMM parameters:  Controller=%u "
1716                                                 "DIMM=%u\n", i, j);
1717                                 print_dimm_parameters(
1718                                         &(pinfo->dimm_params[i][j]));
1719                                 printf("\n");
1720                         }
1721                         printf("\n");
1722                 }
1723                 printf("\n");
1724         }
1725
1726         /* STEP 3:  Common Parameters */
1727         if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1728                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1729                         if (!(ctrl_mask & (1 << i)))
1730                                 continue;
1731                         printf("\"lowest common\" DIMM parameters:  "
1732                                         "Controller=%u\n", i);
1733                         print_lowest_common_dimm_parameters(
1734                                 &pinfo->common_timing_params[i]);
1735                         printf("\n");
1736                 }
1737                 printf("\n");
1738         }
1739
1740         /* STEP 4:  User Configuration Options */
1741         if (do_mask & STEP_GATHER_OPTS) {
1742                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1743                         if (!(ctrl_mask & (1 << i)))
1744                                 continue;
1745                         printf("User Config Options: Controller=%u\n", i);
1746                         print_memctl_options(&pinfo->memctl_opts[i]);
1747                         printf("\n");
1748                 }
1749                 printf("\n");
1750         }
1751
1752         /* STEP 5:  Address assignment */
1753         if (do_mask & STEP_ASSIGN_ADDRESSES) {
1754                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1755                         if (!(ctrl_mask & (1 << i)))
1756                                 continue;
1757                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1758                                 printf("Address Assignment: Controller=%u "
1759                                                 "DIMM=%u\n", i, j);
1760                                 printf("Don't have this functionality yet\n");
1761                         }
1762                         printf("\n");
1763                 }
1764                 printf("\n");
1765         }
1766
1767         /* STEP 6:  computed controller register values */
1768         if (do_mask & STEP_COMPUTE_REGS) {
1769                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1770                         if (!(ctrl_mask & (1 << i)))
1771                                 continue;
1772                         printf("Computed Register Values: Controller=%u\n", i);
1773                         print_fsl_memctl_config_regs(
1774                                 &pinfo->fsl_ddr_config_reg[i]);
1775                         retval = check_fsl_memctl_config_regs(
1776                                 &pinfo->fsl_ddr_config_reg[i]);
1777                         if (retval) {
1778                                 printf("check_fsl_memctl_config_regs "
1779                                         "result = %u\n", retval);
1780                         }
1781                         printf("\n");
1782                 }
1783                 printf("\n");
1784         }
1785 }
1786
1787 struct data_strings {
1788         const char *data_name;
1789         unsigned int step_mask;
1790         unsigned int dimm_number_required;
1791 };
1792
1793 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1794
1795 static unsigned int fsl_ddr_parse_interactive_cmd(
1796         char **argv,
1797         int argc,
1798         unsigned int *pstep_mask,
1799         unsigned int *pctlr_mask,
1800         unsigned int *pdimm_mask,
1801         unsigned int *pdimm_number_required
1802          ) {
1803
1804         static const struct data_strings options[] = {
1805                 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1806                 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1807                 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1808                 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1809                 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1810                 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1811         };
1812         static const unsigned int n_opts = ARRAY_SIZE(options);
1813
1814         unsigned int i, j;
1815         unsigned int error = 0;
1816
1817         for (i = 1; i < argc; i++) {
1818                 unsigned int matched = 0;
1819
1820                 for (j = 0; j < n_opts; j++) {
1821                         if (strcmp(options[j].data_name, argv[i]) != 0)
1822                                 continue;
1823                         *pstep_mask |= options[j].step_mask;
1824                         *pdimm_number_required =
1825                                 options[j].dimm_number_required;
1826                         matched = 1;
1827                         break;
1828                 }
1829
1830                 if (matched)
1831                         continue;
1832
1833                 if (argv[i][0] == 'c') {
1834                         char c = argv[i][1];
1835                         if (isdigit(c))
1836                                 *pctlr_mask |= 1 << (c - '0');
1837                         continue;
1838                 }
1839
1840                 if (argv[i][0] == 'd') {
1841                         char c = argv[i][1];
1842                         if (isdigit(c))
1843                                 *pdimm_mask |= 1 << (c - '0');
1844                         continue;
1845                 }
1846
1847                 printf("unknown arg %s\n", argv[i]);
1848                 *pstep_mask = 0;
1849                 error = 1;
1850                 break;
1851         }
1852
1853         return error;
1854 }
1855
1856 int fsl_ddr_interactive_env_var_exists(void)
1857 {
1858         char buffer[CONFIG_SYS_CBSIZE];
1859
1860         if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
1861                 return 1;
1862
1863         return 0;
1864 }
1865
1866 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
1867 {
1868         unsigned long long ddrsize;
1869         const char *prompt = "FSL DDR>";
1870         char buffer[CONFIG_SYS_CBSIZE];
1871         char buffer2[CONFIG_SYS_CBSIZE];
1872         char *p = NULL;
1873         char *argv[CONFIG_SYS_MAXARGS + 1];     /* NULL terminated */
1874         int argc;
1875         unsigned int next_step = STEP_GET_SPD;
1876         const char *usage = {
1877                 "commands:\n"
1878                 "print      print SPD and intermediate computed data\n"
1879                 "reset      reboot machine\n"
1880                 "recompute  reload SPD and options to default and recompute regs\n"
1881                 "edit       modify spd, parameter, or option\n"
1882                 "compute    recompute registers from current next_step to end\n"
1883                 "copy       copy parameters\n"
1884                 "next_step  shows current next_step\n"
1885                 "help       this message\n"
1886                 "go         program the memory controller and continue with u-boot\n"
1887         };
1888
1889         if (var_is_set) {
1890                 if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
1891                         p = buffer2;
1892                 } else {
1893                         var_is_set = 0;
1894                 }
1895         }
1896
1897         /*
1898          * The strategy for next_step is that it points to the next
1899          * step in the computation process that needs to be done.
1900          */
1901         while (1) {
1902                 if (var_is_set) {
1903                         char *pend = strchr(p, ';');
1904                         if (pend) {
1905                                 /* found command separator, copy sub-command */
1906                                 *pend = '\0';
1907                                 strcpy(buffer, p);
1908                                 p = pend + 1;
1909                         } else {
1910                                 /* separator not found, copy whole string */
1911                                 strcpy(buffer, p);
1912                                 p = NULL;
1913                                 var_is_set = 0;
1914                         }
1915                 } else {
1916                         /*
1917                          * No need to worry for buffer overflow here in
1918                          * this function;  cli_readline() maxes out at
1919                          * CFG_CBSIZE
1920                          */
1921                         cli_readline_into_buffer(prompt, buffer, 0);
1922                 }
1923                 argc = cli_simple_parse_line(buffer, argv);
1924                 if (argc == 0)
1925                         continue;
1926
1927
1928                 if (strcmp(argv[0], "help") == 0) {
1929                         puts(usage);
1930                         continue;
1931                 }
1932
1933                 if (strcmp(argv[0], "next_step") == 0) {
1934                         printf("next_step = 0x%02X (%s)\n",
1935                                next_step,
1936                                step_to_string(next_step));
1937                         continue;
1938                 }
1939
1940                 if (strcmp(argv[0], "copy") == 0) {
1941                         unsigned int error = 0;
1942                         unsigned int step_mask = 0;
1943                         unsigned int src_ctlr_mask = 0;
1944                         unsigned int src_dimm_mask = 0;
1945                         unsigned int dimm_number_required = 0;
1946                         unsigned int src_ctlr_num = 0;
1947                         unsigned int src_dimm_num = 0;
1948                         unsigned int dst_ctlr_num = -1;
1949                         unsigned int dst_dimm_num = -1;
1950                         unsigned int i, num_dest_parms;
1951
1952                         if (argc == 1) {
1953                                 printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
1954                                 continue;
1955                         }
1956
1957                         error = fsl_ddr_parse_interactive_cmd(
1958                                 argv, argc,
1959                                 &step_mask,
1960                                 &src_ctlr_mask,
1961                                 &src_dimm_mask,
1962                                 &dimm_number_required
1963                         );
1964
1965                         /* XXX: only dimm_number_required and step_mask will
1966                            be used by this function.  Parse the controller and
1967                            DIMM number separately because it is easier.  */
1968
1969                         if (error)
1970                                 continue;
1971
1972                         /* parse source destination controller / DIMM */
1973
1974                         num_dest_parms = dimm_number_required ? 2 : 1;
1975
1976                         for (i = 0; i < argc; i++) {
1977                                 if (argv[i][0] == 'c') {
1978                                         char c = argv[i][1];
1979                                         if (isdigit(c)) {
1980                                                 src_ctlr_num = (c - '0');
1981                                                 break;
1982                                         }
1983                                 }
1984                         }
1985
1986                         for (i = 0; i < argc; i++) {
1987                                 if (argv[i][0] == 'd') {
1988                                         char c = argv[i][1];
1989                                         if (isdigit(c)) {
1990                                                 src_dimm_num = (c - '0');
1991                                                 break;
1992                                         }
1993                                 }
1994                         }
1995
1996                         /* parse destination controller / DIMM */
1997
1998                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
1999                                 if (argv[i][0] == 'c') {
2000                                         char c = argv[i][1];
2001                                         if (isdigit(c)) {
2002                                                 dst_ctlr_num = (c - '0');
2003                                                 break;
2004                                         }
2005                                 }
2006                         }
2007
2008                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
2009                                 if (argv[i][0] == 'd') {
2010                                         char c = argv[i][1];
2011                                         if (isdigit(c)) {
2012                                                 dst_dimm_num = (c - '0');
2013                                                 break;
2014                                         }
2015                                 }
2016                         }
2017
2018                         /* TODO: validate inputs */
2019
2020                         debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
2021                                 src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
2022
2023
2024                         switch (step_mask) {
2025
2026                         case STEP_GET_SPD:
2027                                 memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
2028                                         &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
2029                                         sizeof(pinfo->spd_installed_dimms[0][0]));
2030                                 break;
2031
2032                         case STEP_COMPUTE_DIMM_PARMS:
2033                                 memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
2034                                         &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
2035                                         sizeof(pinfo->dimm_params[0][0]));
2036                                 break;
2037
2038                         case STEP_COMPUTE_COMMON_PARMS:
2039                                 memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
2040                                         &(pinfo->common_timing_params[src_ctlr_num]),
2041                                         sizeof(pinfo->common_timing_params[0]));
2042                                 break;
2043
2044                         case STEP_GATHER_OPTS:
2045                                 memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
2046                                         &(pinfo->memctl_opts[src_ctlr_num]),
2047                                         sizeof(pinfo->memctl_opts[0]));
2048                                 break;
2049
2050                         /* someday be able to have addresses to copy addresses... */
2051
2052                         case STEP_COMPUTE_REGS:
2053                                 memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
2054                                         &(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
2055                                         sizeof(pinfo->memctl_opts[0]));
2056                                 break;
2057
2058                         default:
2059                                 printf("unexpected step_mask value\n");
2060                         }
2061
2062                         continue;
2063
2064                 }
2065
2066                 if (strcmp(argv[0], "edit") == 0) {
2067                         unsigned int error = 0;
2068                         unsigned int step_mask = 0;
2069                         unsigned int ctlr_mask = 0;
2070                         unsigned int dimm_mask = 0;
2071                         char *p_element = NULL;
2072                         char *p_value = NULL;
2073                         unsigned int dimm_number_required = 0;
2074                         unsigned int ctrl_num;
2075                         unsigned int dimm_num;
2076
2077                         if (argc == 1) {
2078                                 /* Only the element and value must be last */
2079                                 printf("edit <c#> <d#> "
2080                                         "<spd|dimmparms|commonparms|opts|"
2081                                         "addresses|regs> <element> <value>\n");
2082                                 printf("for spd, specify byte number for "
2083                                         "element\n");
2084                                 continue;
2085                         }
2086
2087                         error = fsl_ddr_parse_interactive_cmd(
2088                                 argv, argc - 2,
2089                                 &step_mask,
2090                                 &ctlr_mask,
2091                                 &dimm_mask,
2092                                 &dimm_number_required
2093                         );
2094
2095                         if (error)
2096                                 continue;
2097
2098
2099                         /* Check arguments */
2100
2101                         /* ERROR: If no steps were found */
2102                         if (step_mask == 0) {
2103                                 printf("Error: No valid steps were specified "
2104                                                 "in argument.\n");
2105                                 continue;
2106                         }
2107
2108                         /* ERROR: If multiple steps were found */
2109                         if (step_mask & (step_mask - 1)) {
2110                                 printf("Error: Multiple steps specified in "
2111                                                 "argument.\n");
2112                                 continue;
2113                         }
2114
2115                         /* ERROR: Controller not specified */
2116                         if (ctlr_mask == 0) {
2117                                 printf("Error: controller number not "
2118                                         "specified or no element and "
2119                                         "value specified\n");
2120                                 continue;
2121                         }
2122
2123                         if (ctlr_mask & (ctlr_mask - 1)) {
2124                                 printf("Error: multiple controllers "
2125                                                 "specified, %X\n", ctlr_mask);
2126                                 continue;
2127                         }
2128
2129                         /* ERROR: DIMM number not specified */
2130                         if (dimm_number_required && dimm_mask == 0) {
2131                                 printf("Error: DIMM number number not "
2132                                         "specified or no element and "
2133                                         "value specified\n");
2134                                 continue;
2135                         }
2136
2137                         if (dimm_mask & (dimm_mask - 1)) {
2138                                 printf("Error: multipled DIMMs specified\n");
2139                                 continue;
2140                         }
2141
2142                         p_element = argv[argc - 2];
2143                         p_value = argv[argc - 1];
2144
2145                         ctrl_num = __ilog2(ctlr_mask);
2146                         dimm_num = __ilog2(dimm_mask);
2147
2148                         switch (step_mask) {
2149                         case STEP_GET_SPD:
2150                                 {
2151                                         unsigned int element_num;
2152                                         unsigned int value;
2153
2154                                         element_num = simple_strtoul(p_element,
2155                                                                      NULL, 0);
2156                                         value = simple_strtoul(p_value,
2157                                                                NULL, 0);
2158                                         fsl_ddr_spd_edit(pinfo,
2159                                                                ctrl_num,
2160                                                                dimm_num,
2161                                                                element_num,
2162                                                                value);
2163                                         next_step = STEP_COMPUTE_DIMM_PARMS;
2164                                 }
2165                                 break;
2166
2167                         case STEP_COMPUTE_DIMM_PARMS:
2168                                 fsl_ddr_dimm_parameters_edit(
2169                                                  pinfo, ctrl_num, dimm_num,
2170                                                  p_element, p_value);
2171                                 next_step = STEP_COMPUTE_COMMON_PARMS;
2172                                 break;
2173
2174                         case STEP_COMPUTE_COMMON_PARMS:
2175                                 lowest_common_dimm_parameters_edit(pinfo,
2176                                                 ctrl_num, p_element, p_value);
2177                                 next_step = STEP_GATHER_OPTS;
2178                                 break;
2179
2180                         case STEP_GATHER_OPTS:
2181                                 fsl_ddr_options_edit(pinfo, ctrl_num,
2182                                                            p_element, p_value);
2183                                 next_step = STEP_ASSIGN_ADDRESSES;
2184                                 break;
2185
2186                         case STEP_ASSIGN_ADDRESSES:
2187                                 printf("editing of address assignment "
2188                                                 "not yet implemented\n");
2189                                 break;
2190
2191                         case STEP_COMPUTE_REGS:
2192                                 {
2193                                         fsl_ddr_regs_edit(pinfo,
2194                                                                 ctrl_num,
2195                                                                 p_element,
2196                                                                 p_value);
2197                                         next_step = STEP_PROGRAM_REGS;
2198                                 }
2199                                 break;
2200
2201                         default:
2202                                 printf("programming error\n");
2203                                 while (1)
2204                                         ;
2205                                 break;
2206                         }
2207                         continue;
2208                 }
2209
2210                 if (strcmp(argv[0], "reset") == 0) {
2211                         /*
2212                          * Reboot machine.
2213                          * Args don't seem to matter because this
2214                          * doesn't return
2215                          */
2216                         do_reset(NULL, 0, 0, NULL);
2217                         printf("Reset didn't work\n");
2218                 }
2219
2220                 if (strcmp(argv[0], "recompute") == 0) {
2221                         /*
2222                          * Recalculate everything, starting with
2223                          * loading SPD EEPROM from DIMMs
2224                          */
2225                         next_step = STEP_GET_SPD;
2226                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2227                         continue;
2228                 }
2229
2230                 if (strcmp(argv[0], "compute") == 0) {
2231                         /*
2232                          * Compute rest of steps starting at
2233                          * the current next_step/
2234                          */
2235                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2236                         continue;
2237                 }
2238
2239                 if (strcmp(argv[0], "print") == 0) {
2240                         unsigned int error = 0;
2241                         unsigned int step_mask = 0;
2242                         unsigned int ctlr_mask = 0;
2243                         unsigned int dimm_mask = 0;
2244                         unsigned int dimm_number_required = 0;
2245
2246                         if (argc == 1) {
2247                                 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
2248                                   "[commonparms] [opts] [addresses] [regs]\n");
2249                                 continue;
2250                         }
2251
2252                         error = fsl_ddr_parse_interactive_cmd(
2253                                 argv, argc,
2254                                 &step_mask,
2255                                 &ctlr_mask,
2256                                 &dimm_mask,
2257                                 &dimm_number_required
2258                         );
2259
2260                         if (error)
2261                                 continue;
2262
2263                         /* If no particular controller was found, print all */
2264                         if (ctlr_mask == 0)
2265                                 ctlr_mask = 0xFF;
2266
2267                         /* If no particular dimm was found, print all dimms. */
2268                         if (dimm_mask == 0)
2269                                 dimm_mask = 0xFF;
2270
2271                         /* If no steps were found, print all steps. */
2272                         if (step_mask == 0)
2273                                 step_mask = STEP_ALL;
2274
2275                         fsl_ddr_printinfo(pinfo, ctlr_mask,
2276                                                 dimm_mask, step_mask);
2277                         continue;
2278                 }
2279
2280                 if (strcmp(argv[0], "go") == 0) {
2281                         if (next_step)
2282                                 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2283                         break;
2284                 }
2285
2286                 printf("unknown command %s\n", argv[0]);
2287         }
2288
2289         debug("end of memory = %llu\n", (u64)ddrsize);
2290
2291         return ddrsize;
2292 }