git.sur5r.net Git - u-boot/blob - drivers/ddr/fsl/interactive.c

   1 /*
   2  * Copyright 2010-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  *         York Sun [at freescale.com]
  12  */
  13
  14 #include <common.h>
  15 #include <linux/ctype.h>
  16 #include <asm/types.h>
  17 #include <asm/io.h>
  18
  19 #include <fsl_ddr_sdram.h>
  20 #include <fsl_ddr.h>
  21
  22 /* Option parameter Structures */
  23 struct options_string {
  24         const char *option_name;
  25         size_t offset;
  26         unsigned int size;
  27         const char printhex;
  28 };
  29
  30 static unsigned int picos_to_mhz(unsigned int picos)
  31 {
  32         return 1000000 / picos;
  33 }
  34
  35 static void print_option_table(const struct options_string *table,
  36                          int table_size,
  37                          const void *base)
  38 {
  39         unsigned int i;
  40         unsigned int *ptr;
  41         unsigned long long *ptr_l;
  42
  43         for (i = 0; i < table_size; i++) {
  44                 switch (table[i].size) {
  45                 case 4:
  46                         ptr = (unsigned int *) (base + table[i].offset);
  47                         if (table[i].printhex) {
  48                                 printf("%s = 0x%08X\n",
  49                                         table[i].option_name, *ptr);
  50                         } else {
  51                                 printf("%s = %u\n",
  52                                         table[i].option_name, *ptr);
  53                         }
  54                         break;
  55                 case 8:
  56                         ptr_l = (unsigned long long *) (base + table[i].offset);
  57                         printf("%s = %llu\n",
  58                                 table[i].option_name, *ptr_l);
  59                         break;
  60                 default:
  61                         printf("Unrecognized size!\n");
  62                         break;
  63                 }
  64         }
  65 }
  66
  67 static int handle_option_table(const struct options_string *table,
  68                          int table_size,
  69                          void *base,
  70                          const char *opt,
  71                          const char *val)
  72 {
  73         unsigned int i;
  74         unsigned int value, *ptr;
  75         unsigned long long value_l, *ptr_l;
  76
  77         for (i = 0; i < table_size; i++) {
  78                 if (strcmp(table[i].option_name, opt) != 0)
  79                         continue;
  80                 switch (table[i].size) {
  81                 case 4:
  82                         value = simple_strtoul(val, NULL, 0);
  83                         ptr = base + table[i].offset;
  84                         *ptr = value;
  85                         break;
  86                 case 8:
  87                         value_l = simple_strtoull(val, NULL, 0);
  88                         ptr_l = base + table[i].offset;
  89                         *ptr_l = value_l;
  90                         break;
  91                 default:
  92                         printf("Unrecognized size!\n");
  93                         break;
  94                 }
  95                 return 1;
  96         }
  97
  98         return 0;
  99 }
 100
 101 static void fsl_ddr_generic_edit(void *pdata,
 102                            void *pend,
 103                            unsigned int element_size,
 104                            unsigned int element_num,
 105                            unsigned int value)
 106 {
 107         char *pcdata = (char *)pdata;           /* BIG ENDIAN ONLY */
 108
 109         pcdata += element_num * element_size;
 110         if ((pcdata + element_size) > (char *) pend) {
 111                 printf("trying to write past end of data\n");
 112                 return;
 113         }
 114
 115         switch (element_size) {
 116         case 1:
 117                 __raw_writeb(value, pcdata);
 118                 break;
 119         case 2:
 120                 __raw_writew(value, pcdata);
 121                 break;
 122         case 4:
 123                 __raw_writel(value, pcdata);
 124                 break;
 125         default:
 126                 printf("unexpected element size %u\n", element_size);
 127                 break;
 128         }
 129 }
 130
 131 static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
 132                        unsigned int ctrl_num,
 133                        unsigned int dimm_num,
 134                        unsigned int element_num,
 135                        unsigned int value)
 136 {
 137         generic_spd_eeprom_t *pspd;
 138
 139         pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
 140         fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
 141 }
 142
 143 #define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
 144         sizeof((common_timing_params_t *)0)->x, 0}
 145
 146 static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 147                                         unsigned int ctrl_num,
 148                                         const char *optname_str,
 149                                         const char *value_str)
 150 {
 151         common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
 152
 153         static const struct options_string options[] = {
 154                 COMMON_TIMING(tckmin_x_ps),
 155                 COMMON_TIMING(tckmax_ps),
 156                 COMMON_TIMING(taamin_ps),
 157                 COMMON_TIMING(trcd_ps),
 158                 COMMON_TIMING(trp_ps),
 159                 COMMON_TIMING(tras_ps),
 160
 161 #ifdef CONFIG_SYS_FSL_DDR4
 162                 COMMON_TIMING(trfc1_ps),
 163                 COMMON_TIMING(trfc2_ps),
 164                 COMMON_TIMING(trfc4_ps),
 165                 COMMON_TIMING(trrds_ps),
 166                 COMMON_TIMING(trrdl_ps),
 167                 COMMON_TIMING(tccdl_ps),
 168 #else
 169                 COMMON_TIMING(twtr_ps),
 170                 COMMON_TIMING(trfc_ps),
 171                 COMMON_TIMING(trrd_ps),
 172                 COMMON_TIMING(trtp_ps),
 173 #endif
 174                 COMMON_TIMING(twr_ps),
 175                 COMMON_TIMING(trc_ps),
 176                 COMMON_TIMING(refresh_rate_ps),
 177                 COMMON_TIMING(extended_op_srt),
 178 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 179                 COMMON_TIMING(tis_ps),
 180                 COMMON_TIMING(tih_ps),
 181                 COMMON_TIMING(tds_ps),
 182                 COMMON_TIMING(tdh_ps),
 183                 COMMON_TIMING(tdqsq_max_ps),
 184                 COMMON_TIMING(tqhs_ps),
 185 #endif
 186                 COMMON_TIMING(ndimms_present),
 187                 COMMON_TIMING(lowest_common_spd_caslat),
 188                 COMMON_TIMING(highest_common_derated_caslat),
 189                 COMMON_TIMING(additive_latency),
 190                 COMMON_TIMING(all_dimms_burst_lengths_bitmask),
 191                 COMMON_TIMING(all_dimms_registered),
 192                 COMMON_TIMING(all_dimms_unbuffered),
 193                 COMMON_TIMING(all_dimms_ecc_capable),
 194                 COMMON_TIMING(total_mem),
 195                 COMMON_TIMING(base_address),
 196         };
 197         static const unsigned int n_opts = ARRAY_SIZE(options);
 198
 199         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 200                 return;
 201
 202         printf("Error: couldn't find option string %s\n", optname_str);
 203 }
 204
 205 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
 206         sizeof((dimm_params_t *)0)->x, 0}
 207
 208 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 209                                    unsigned int ctrl_num,
 210                                    unsigned int dimm_num,
 211                                    const char *optname_str,
 212                                    const char *value_str)
 213 {
 214         dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
 215
 216         static const struct options_string options[] = {
 217                 DIMM_PARM(n_ranks),
 218                 DIMM_PARM(data_width),
 219                 DIMM_PARM(primary_sdram_width),
 220                 DIMM_PARM(ec_sdram_width),
 221                 DIMM_PARM(registered_dimm),
 222                 DIMM_PARM(device_width),
 223
 224                 DIMM_PARM(n_row_addr),
 225                 DIMM_PARM(n_col_addr),
 226                 DIMM_PARM(edc_config),
 227 #ifdef CONFIG_SYS_FSL_DDR4
 228                 DIMM_PARM(bank_addr_bits),
 229                 DIMM_PARM(bank_group_bits),
 230 #else
 231                 DIMM_PARM(n_banks_per_sdram_device),
 232 #endif
 233                 DIMM_PARM(burst_lengths_bitmask),
 234                 DIMM_PARM(row_density),
 235
 236                 DIMM_PARM(tckmin_x_ps),
 237                 DIMM_PARM(tckmin_x_minus_1_ps),
 238                 DIMM_PARM(tckmin_x_minus_2_ps),
 239                 DIMM_PARM(tckmax_ps),
 240
 241                 DIMM_PARM(caslat_x),
 242                 DIMM_PARM(caslat_x_minus_1),
 243                 DIMM_PARM(caslat_x_minus_2),
 244
 245                 DIMM_PARM(caslat_lowest_derated),
 246
 247                 DIMM_PARM(trcd_ps),
 248                 DIMM_PARM(trp_ps),
 249                 DIMM_PARM(tras_ps),
 250 #ifdef CONFIG_SYS_FSL_DDR4
 251                 DIMM_PARM(trfc1_ps),
 252                 DIMM_PARM(trfc2_ps),
 253                 DIMM_PARM(trfc4_ps),
 254                 DIMM_PARM(trrds_ps),
 255                 DIMM_PARM(trrdl_ps),
 256                 DIMM_PARM(tccdl_ps),
 257 #else
 258                 DIMM_PARM(twr_ps),
 259                 DIMM_PARM(twtr_ps),
 260                 DIMM_PARM(trfc_ps),
 261                 DIMM_PARM(trrd_ps),
 262                 DIMM_PARM(trtp_ps),
 263 #endif
 264                 DIMM_PARM(trc_ps),
 265                 DIMM_PARM(refresh_rate_ps),
 266                 DIMM_PARM(extended_op_srt),
 267
 268 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 269                 DIMM_PARM(tis_ps),
 270                 DIMM_PARM(tih_ps),
 271                 DIMM_PARM(tds_ps),
 272                 DIMM_PARM(tdh_ps),
 273                 DIMM_PARM(tdqsq_max_ps),
 274                 DIMM_PARM(tqhs_ps),
 275 #endif
 276
 277                 DIMM_PARM(rank_density),
 278                 DIMM_PARM(capacity),
 279                 DIMM_PARM(base_address),
 280         };
 281
 282         static const unsigned int n_opts = ARRAY_SIZE(options);
 283
 284         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 285                 return;
 286
 287         printf("couldn't find option string %s\n", optname_str);
 288 }
 289
 290 static void print_dimm_parameters(const dimm_params_t *pdimm)
 291 {
 292         static const struct options_string options[] = {
 293                 DIMM_PARM(n_ranks),
 294                 DIMM_PARM(data_width),
 295                 DIMM_PARM(primary_sdram_width),
 296                 DIMM_PARM(ec_sdram_width),
 297                 DIMM_PARM(registered_dimm),
 298                 DIMM_PARM(device_width),
 299
 300                 DIMM_PARM(n_row_addr),
 301                 DIMM_PARM(n_col_addr),
 302                 DIMM_PARM(edc_config),
 303 #ifdef CONFIG_SYS_FSL_DDR4
 304                 DIMM_PARM(bank_addr_bits),
 305                 DIMM_PARM(bank_group_bits),
 306 #else
 307                 DIMM_PARM(n_banks_per_sdram_device),
 308 #endif
 309
 310                 DIMM_PARM(tckmin_x_ps),
 311                 DIMM_PARM(tckmin_x_minus_1_ps),
 312                 DIMM_PARM(tckmin_x_minus_2_ps),
 313                 DIMM_PARM(tckmax_ps),
 314
 315                 DIMM_PARM(caslat_x),
 316                 DIMM_PARM(taa_ps),
 317                 DIMM_PARM(caslat_x_minus_1),
 318                 DIMM_PARM(caslat_x_minus_2),
 319                 DIMM_PARM(caslat_lowest_derated),
 320
 321                 DIMM_PARM(trcd_ps),
 322                 DIMM_PARM(trp_ps),
 323                 DIMM_PARM(tras_ps),
 324 #ifdef CONFIG_SYS_FSL_DDR4
 325                 DIMM_PARM(trfc1_ps),
 326                 DIMM_PARM(trfc2_ps),
 327                 DIMM_PARM(trfc4_ps),
 328                 DIMM_PARM(trrds_ps),
 329                 DIMM_PARM(trrdl_ps),
 330                 DIMM_PARM(tccdl_ps),
 331 #else
 332                 DIMM_PARM(twr_ps),
 333                 DIMM_PARM(twtr_ps),
 334                 DIMM_PARM(trfc_ps),
 335                 DIMM_PARM(trrd_ps),
 336                 DIMM_PARM(trtp_ps),
 337 #endif
 338                 DIMM_PARM(trc_ps),
 339                 DIMM_PARM(refresh_rate_ps),
 340
 341 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 342                 DIMM_PARM(tis_ps),
 343                 DIMM_PARM(tih_ps),
 344                 DIMM_PARM(tds_ps),
 345                 DIMM_PARM(tdh_ps),
 346                 DIMM_PARM(tdqsq_max_ps),
 347                 DIMM_PARM(tqhs_ps),
 348 #endif
 349         };
 350         static const unsigned int n_opts = ARRAY_SIZE(options);
 351
 352         if (pdimm->n_ranks == 0) {
 353                 printf("DIMM not present\n");
 354                 return;
 355         }
 356         printf("DIMM organization parameters:\n");
 357         printf("module part name = %s\n", pdimm->mpart);
 358         printf("rank_density = %llu bytes (%llu megabytes)\n",
 359                pdimm->rank_density, pdimm->rank_density / 0x100000);
 360         printf("capacity = %llu bytes (%llu megabytes)\n",
 361                pdimm->capacity, pdimm->capacity / 0x100000);
 362         printf("burst_lengths_bitmask = %02X\n",
 363                pdimm->burst_lengths_bitmask);
 364         printf("base_addresss = %llu (%08llX %08llX)\n",
 365                pdimm->base_address,
 366                (pdimm->base_address >> 32),
 367                pdimm->base_address & 0xFFFFFFFF);
 368         print_option_table(options, n_opts, pdimm);
 369 }
 370
 371 static void print_lowest_common_dimm_parameters(
 372                 const common_timing_params_t *plcd_dimm_params)
 373 {
 374         static const struct options_string options[] = {
 375                 COMMON_TIMING(taamin_ps),
 376                 COMMON_TIMING(trcd_ps),
 377                 COMMON_TIMING(trp_ps),
 378                 COMMON_TIMING(tras_ps),
 379 #ifdef CONFIG_SYS_FSL_DDR4
 380                 COMMON_TIMING(trfc1_ps),
 381                 COMMON_TIMING(trfc2_ps),
 382                 COMMON_TIMING(trfc4_ps),
 383                 COMMON_TIMING(trrds_ps),
 384                 COMMON_TIMING(trrdl_ps),
 385                 COMMON_TIMING(tccdl_ps),
 386 #else
 387                 COMMON_TIMING(twtr_ps),
 388                 COMMON_TIMING(trfc_ps),
 389                 COMMON_TIMING(trrd_ps),
 390                 COMMON_TIMING(trtp_ps),
 391 #endif
 392                 COMMON_TIMING(twr_ps),
 393                 COMMON_TIMING(trc_ps),
 394                 COMMON_TIMING(refresh_rate_ps),
 395                 COMMON_TIMING(extended_op_srt),
 396 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 397                 COMMON_TIMING(tis_ps),
 398                 COMMON_TIMING(tih_ps),
 399                 COMMON_TIMING(tds_ps),
 400                 COMMON_TIMING(tdh_ps),
 401                 COMMON_TIMING(tdqsq_max_ps),
 402                 COMMON_TIMING(tqhs_ps),
 403 #endif
 404                 COMMON_TIMING(lowest_common_spd_caslat),
 405                 COMMON_TIMING(highest_common_derated_caslat),
 406                 COMMON_TIMING(additive_latency),
 407                 COMMON_TIMING(ndimms_present),
 408                 COMMON_TIMING(all_dimms_registered),
 409                 COMMON_TIMING(all_dimms_unbuffered),
 410                 COMMON_TIMING(all_dimms_ecc_capable),
 411         };
 412         static const unsigned int n_opts = ARRAY_SIZE(options);
 413
 414         /* Clock frequencies */
 415         printf("tckmin_x_ps = %u (%u MHz)\n",
 416                plcd_dimm_params->tckmin_x_ps,
 417                picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
 418         printf("tckmax_ps = %u (%u MHz)\n",
 419                plcd_dimm_params->tckmax_ps,
 420                picos_to_mhz(plcd_dimm_params->tckmax_ps));
 421         printf("all_dimms_burst_lengths_bitmask = %02X\n",
 422                plcd_dimm_params->all_dimms_burst_lengths_bitmask);
 423
 424         print_option_table(options, n_opts, plcd_dimm_params);
 425
 426         printf("total_mem = %llu (%llu megabytes)\n",
 427                plcd_dimm_params->total_mem,
 428                plcd_dimm_params->total_mem / 0x100000);
 429         printf("base_address = %llu (%llu megabytes)\n",
 430                plcd_dimm_params->base_address,
 431                plcd_dimm_params->base_address / 0x100000);
 432 }
 433
 434 #define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
 435         sizeof((memctl_options_t *)0)->x, 0}
 436 #define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
 437         offsetof(memctl_options_t, cs_local_opts[x].y), \
 438         sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
 439
 440 static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 441                            unsigned int ctl_num,
 442                            const char *optname_str,
 443                            const char *value_str)
 444 {
 445         memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
 446         /*
 447          * This array all on the stack and *computed* each time this
 448          * function is rung.
 449          */
 450         static const struct options_string options[] = {
 451                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 452                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 453 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 454                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 455                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 456 #endif
 457 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 458                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 459                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 460 #endif
 461 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 462                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 463                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 464 #endif
 465 #if defined(CONFIG_SYS_FSL_DDR3)
 466                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 467                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 468 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 469                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 470                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 471 #endif
 472 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 473                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 474                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 475 #endif
 476 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 477                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 478                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 479 #endif
 480 #endif
 481                 CTRL_OPTIONS(memctl_interleaving),
 482                 CTRL_OPTIONS(memctl_interleaving_mode),
 483                 CTRL_OPTIONS(ba_intlv_ctl),
 484                 CTRL_OPTIONS(ecc_mode),
 485                 CTRL_OPTIONS(ecc_init_using_memctl),
 486                 CTRL_OPTIONS(dqs_config),
 487                 CTRL_OPTIONS(self_refresh_in_sleep),
 488                 CTRL_OPTIONS(dynamic_power),
 489                 CTRL_OPTIONS(data_bus_width),
 490                 CTRL_OPTIONS(burst_length),
 491                 CTRL_OPTIONS(cas_latency_override),
 492                 CTRL_OPTIONS(cas_latency_override_value),
 493                 CTRL_OPTIONS(use_derated_caslat),
 494                 CTRL_OPTIONS(additive_latency_override),
 495                 CTRL_OPTIONS(additive_latency_override_value),
 496                 CTRL_OPTIONS(clk_adjust),
 497                 CTRL_OPTIONS(cpo_override),
 498                 CTRL_OPTIONS(write_data_delay),
 499                 CTRL_OPTIONS(half_strength_driver_enable),
 500
 501                 /*
 502                  * These can probably be changed to 2T_EN and 3T_EN
 503                  * (using a leading numerical character) without problem
 504                  */
 505                 CTRL_OPTIONS(twot_en),
 506                 CTRL_OPTIONS(threet_en),
 507                 CTRL_OPTIONS(ap_en),
 508                 CTRL_OPTIONS(x4_en),
 509                 CTRL_OPTIONS(bstopre),
 510                 CTRL_OPTIONS(wrlvl_override),
 511                 CTRL_OPTIONS(wrlvl_sample),
 512                 CTRL_OPTIONS(wrlvl_start),
 513                 CTRL_OPTIONS(rcw_override),
 514                 CTRL_OPTIONS(rcw_1),
 515                 CTRL_OPTIONS(rcw_2),
 516                 CTRL_OPTIONS(ddr_cdr1),
 517                 CTRL_OPTIONS(ddr_cdr2),
 518                 CTRL_OPTIONS(tcke_clock_pulse_width_ps),
 519                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 520                 CTRL_OPTIONS(trwt_override),
 521                 CTRL_OPTIONS(trwt),
 522                 CTRL_OPTIONS(rtt_override),
 523                 CTRL_OPTIONS(rtt_override_value),
 524                 CTRL_OPTIONS(rtt_wr_override_value),
 525         };
 526
 527         static const unsigned int n_opts = ARRAY_SIZE(options);
 528
 529         if (handle_option_table(options, n_opts, p,
 530                                         optname_str, value_str))
 531                 return;
 532
 533         printf("couldn't find option string %s\n", optname_str);
 534 }
 535
 536 #define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
 537         sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
 538 #define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
 539         offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
 540         sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
 541
 542 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 543 {
 544         unsigned int i;
 545         static const struct options_string options[] = {
 546                 CFG_REGS_CS(0, bnds),
 547                 CFG_REGS_CS(0, config),
 548                 CFG_REGS_CS(0, config_2),
 549 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 550                 CFG_REGS_CS(1, bnds),
 551                 CFG_REGS_CS(1, config),
 552                 CFG_REGS_CS(1, config_2),
 553 #endif
 554 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 555                 CFG_REGS_CS(2, bnds),
 556                 CFG_REGS_CS(2, config),
 557                 CFG_REGS_CS(2, config_2),
 558 #endif
 559 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 560                 CFG_REGS_CS(3, bnds),
 561                 CFG_REGS_CS(3, config),
 562                 CFG_REGS_CS(3, config_2),
 563 #endif
 564                 CFG_REGS(timing_cfg_3),
 565                 CFG_REGS(timing_cfg_0),
 566                 CFG_REGS(timing_cfg_1),
 567                 CFG_REGS(timing_cfg_2),
 568                 CFG_REGS(ddr_sdram_cfg),
 569                 CFG_REGS(ddr_sdram_cfg_2),
 570                 CFG_REGS(ddr_sdram_cfg_3),
 571                 CFG_REGS(ddr_sdram_mode),
 572                 CFG_REGS(ddr_sdram_mode_2),
 573                 CFG_REGS(ddr_sdram_mode_3),
 574                 CFG_REGS(ddr_sdram_mode_4),
 575                 CFG_REGS(ddr_sdram_mode_5),
 576                 CFG_REGS(ddr_sdram_mode_6),
 577                 CFG_REGS(ddr_sdram_mode_7),
 578                 CFG_REGS(ddr_sdram_mode_8),
 579 #ifdef CONFIG_SYS_FSL_DDR4
 580                 CFG_REGS(ddr_sdram_mode_9),
 581                 CFG_REGS(ddr_sdram_mode_10),
 582                 CFG_REGS(ddr_sdram_mode_11),
 583                 CFG_REGS(ddr_sdram_mode_12),
 584                 CFG_REGS(ddr_sdram_mode_13),
 585                 CFG_REGS(ddr_sdram_mode_14),
 586                 CFG_REGS(ddr_sdram_mode_15),
 587                 CFG_REGS(ddr_sdram_mode_16),
 588 #endif
 589                 CFG_REGS(ddr_sdram_interval),
 590                 CFG_REGS(ddr_data_init),
 591                 CFG_REGS(ddr_sdram_clk_cntl),
 592                 CFG_REGS(ddr_init_addr),
 593                 CFG_REGS(ddr_init_ext_addr),
 594                 CFG_REGS(timing_cfg_4),
 595                 CFG_REGS(timing_cfg_5),
 596 #ifdef CONFIG_SYS_FSL_DDR4
 597                 CFG_REGS(timing_cfg_6),
 598                 CFG_REGS(timing_cfg_7),
 599                 CFG_REGS(timing_cfg_8),
 600                 CFG_REGS(timing_cfg_9),
 601 #endif
 602                 CFG_REGS(ddr_zq_cntl),
 603                 CFG_REGS(ddr_wrlvl_cntl),
 604                 CFG_REGS(ddr_wrlvl_cntl_2),
 605                 CFG_REGS(ddr_wrlvl_cntl_3),
 606                 CFG_REGS(ddr_sr_cntr),
 607                 CFG_REGS(ddr_sdram_rcw_1),
 608                 CFG_REGS(ddr_sdram_rcw_2),
 609                 CFG_REGS(ddr_cdr1),
 610                 CFG_REGS(ddr_cdr2),
 611                 CFG_REGS(dq_map_0),
 612                 CFG_REGS(dq_map_1),
 613                 CFG_REGS(dq_map_2),
 614                 CFG_REGS(dq_map_3),
 615                 CFG_REGS(err_disable),
 616                 CFG_REGS(err_int_en),
 617                 CFG_REGS(ddr_eor),
 618         };
 619         static const unsigned int n_opts = ARRAY_SIZE(options);
 620
 621         print_option_table(options, n_opts, ddr);
 622
 623         for (i = 0; i < 32; i++)
 624                 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
 625 }
 626
 627 static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 628                         unsigned int ctrl_num,
 629                         const char *regname,
 630                         const char *value_str)
 631 {
 632         unsigned int i;
 633         fsl_ddr_cfg_regs_t *ddr;
 634         char buf[20];
 635         static const struct options_string options[] = {
 636                 CFG_REGS_CS(0, bnds),
 637                 CFG_REGS_CS(0, config),
 638                 CFG_REGS_CS(0, config_2),
 639 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 640                 CFG_REGS_CS(1, bnds),
 641                 CFG_REGS_CS(1, config),
 642                 CFG_REGS_CS(1, config_2),
 643 #endif
 644 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 645                 CFG_REGS_CS(2, bnds),
 646                 CFG_REGS_CS(2, config),
 647                 CFG_REGS_CS(2, config_2),
 648 #endif
 649 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 650                 CFG_REGS_CS(3, bnds),
 651                 CFG_REGS_CS(3, config),
 652                 CFG_REGS_CS(3, config_2),
 653 #endif
 654                 CFG_REGS(timing_cfg_3),
 655                 CFG_REGS(timing_cfg_0),
 656                 CFG_REGS(timing_cfg_1),
 657                 CFG_REGS(timing_cfg_2),
 658                 CFG_REGS(ddr_sdram_cfg),
 659                 CFG_REGS(ddr_sdram_cfg_2),
 660                 CFG_REGS(ddr_sdram_cfg_3),
 661                 CFG_REGS(ddr_sdram_mode),
 662                 CFG_REGS(ddr_sdram_mode_2),
 663                 CFG_REGS(ddr_sdram_mode_3),
 664                 CFG_REGS(ddr_sdram_mode_4),
 665                 CFG_REGS(ddr_sdram_mode_5),
 666                 CFG_REGS(ddr_sdram_mode_6),
 667                 CFG_REGS(ddr_sdram_mode_7),
 668                 CFG_REGS(ddr_sdram_mode_8),
 669 #ifdef CONFIG_SYS_FSL_DDR4
 670                 CFG_REGS(ddr_sdram_mode_9),
 671                 CFG_REGS(ddr_sdram_mode_10),
 672                 CFG_REGS(ddr_sdram_mode_11),
 673                 CFG_REGS(ddr_sdram_mode_12),
 674                 CFG_REGS(ddr_sdram_mode_13),
 675                 CFG_REGS(ddr_sdram_mode_14),
 676                 CFG_REGS(ddr_sdram_mode_15),
 677                 CFG_REGS(ddr_sdram_mode_16),
 678 #endif
 679                 CFG_REGS(ddr_sdram_interval),
 680                 CFG_REGS(ddr_data_init),
 681                 CFG_REGS(ddr_sdram_clk_cntl),
 682                 CFG_REGS(ddr_init_addr),
 683                 CFG_REGS(ddr_init_ext_addr),
 684                 CFG_REGS(timing_cfg_4),
 685                 CFG_REGS(timing_cfg_5),
 686 #ifdef CONFIG_SYS_FSL_DDR4
 687                 CFG_REGS(timing_cfg_6),
 688                 CFG_REGS(timing_cfg_7),
 689                 CFG_REGS(timing_cfg_8),
 690                 CFG_REGS(timing_cfg_9),
 691 #endif
 692                 CFG_REGS(ddr_zq_cntl),
 693                 CFG_REGS(ddr_wrlvl_cntl),
 694                 CFG_REGS(ddr_wrlvl_cntl_2),
 695                 CFG_REGS(ddr_wrlvl_cntl_3),
 696                 CFG_REGS(ddr_sr_cntr),
 697                 CFG_REGS(ddr_sdram_rcw_1),
 698                 CFG_REGS(ddr_sdram_rcw_2),
 699                 CFG_REGS(ddr_cdr1),
 700                 CFG_REGS(ddr_cdr2),
 701                 CFG_REGS(dq_map_0),
 702                 CFG_REGS(dq_map_1),
 703                 CFG_REGS(dq_map_2),
 704                 CFG_REGS(dq_map_3),
 705                 CFG_REGS(err_disable),
 706                 CFG_REGS(err_int_en),
 707                 CFG_REGS(ddr_sdram_rcw_2),
 708                 CFG_REGS(ddr_sdram_rcw_2),
 709                 CFG_REGS(ddr_eor),
 710         };
 711         static const unsigned int n_opts = ARRAY_SIZE(options);
 712
 713         debug("fsl_ddr_regs_edit: ctrl_num = %u, "
 714                 "regname = %s, value = %s\n",
 715                 ctrl_num, regname, value_str);
 716         if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
 717                 return;
 718
 719         ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
 720
 721         if (handle_option_table(options, n_opts, ddr, regname, value_str))
 722                 return;
 723
 724         for (i = 0; i < 32; i++) {
 725                 unsigned int value = simple_strtoul(value_str, NULL, 0);
 726                 sprintf(buf, "debug_%u", i + 1);
 727                 if (strcmp(buf, regname) == 0) {
 728                         ddr->debug[i] = value;
 729                         return;
 730                 }
 731         }
 732         printf("Error: couldn't find register string %s\n", regname);
 733 }
 734
 735 #define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
 736         sizeof((memctl_options_t *)0)->x, 1}
 737
 738 static void print_memctl_options(const memctl_options_t *popts)
 739 {
 740         static const struct options_string options[] = {
 741                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 742                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 743 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 744                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 745                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 746 #endif
 747 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 748                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 749                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 750 #endif
 751 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 752                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 753                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 754 #endif
 755 #if defined(CONFIG_SYS_FSL_DDR3)
 756                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 757                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 758 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 759                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 760                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 761 #endif
 762 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 763                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 764                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 765 #endif
 766 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 767                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 768                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 769 #endif
 770 #endif
 771                 CTRL_OPTIONS(memctl_interleaving),
 772                 CTRL_OPTIONS(memctl_interleaving_mode),
 773                 CTRL_OPTIONS_HEX(ba_intlv_ctl),
 774                 CTRL_OPTIONS(ecc_mode),
 775                 CTRL_OPTIONS(ecc_init_using_memctl),
 776                 CTRL_OPTIONS(dqs_config),
 777                 CTRL_OPTIONS(self_refresh_in_sleep),
 778                 CTRL_OPTIONS(dynamic_power),
 779                 CTRL_OPTIONS(data_bus_width),
 780                 CTRL_OPTIONS(burst_length),
 781                 CTRL_OPTIONS(cas_latency_override),
 782                 CTRL_OPTIONS(cas_latency_override_value),
 783                 CTRL_OPTIONS(use_derated_caslat),
 784                 CTRL_OPTIONS(additive_latency_override),
 785                 CTRL_OPTIONS(additive_latency_override_value),
 786                 CTRL_OPTIONS(clk_adjust),
 787                 CTRL_OPTIONS(cpo_override),
 788                 CTRL_OPTIONS(write_data_delay),
 789                 CTRL_OPTIONS(half_strength_driver_enable),
 790                 /*
 791                  * These can probably be changed to 2T_EN and 3T_EN
 792                  * (using a leading numerical character) without problem
 793                  */
 794                 CTRL_OPTIONS(twot_en),
 795                 CTRL_OPTIONS(threet_en),
 796                 CTRL_OPTIONS(registered_dimm_en),
 797                 CTRL_OPTIONS(ap_en),
 798                 CTRL_OPTIONS(x4_en),
 799                 CTRL_OPTIONS(bstopre),
 800                 CTRL_OPTIONS(wrlvl_override),
 801                 CTRL_OPTIONS(wrlvl_sample),
 802                 CTRL_OPTIONS(wrlvl_start),
 803                 CTRL_OPTIONS(rcw_override),
 804                 CTRL_OPTIONS(rcw_1),
 805                 CTRL_OPTIONS(rcw_2),
 806                 CTRL_OPTIONS_HEX(ddr_cdr1),
 807                 CTRL_OPTIONS_HEX(ddr_cdr2),
 808                 CTRL_OPTIONS(tcke_clock_pulse_width_ps),
 809                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 810                 CTRL_OPTIONS(trwt_override),
 811                 CTRL_OPTIONS(trwt),
 812                 CTRL_OPTIONS(rtt_override),
 813                 CTRL_OPTIONS(rtt_override_value),
 814                 CTRL_OPTIONS(rtt_wr_override_value),
 815         };
 816         static const unsigned int n_opts = ARRAY_SIZE(options);
 817
 818         print_option_table(options, n_opts, popts);
 819 }
 820
 821 #ifdef CONFIG_SYS_FSL_DDR1
 822 void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
 823 {
 824         unsigned int i;
 825
 826         printf("%-3d    : %02x %s\n", 0, spd->info_size,
 827                " spd->info_size,   *  0 # bytes written into serial memory *");
 828         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
 829                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
 830         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
 831                " spd->mem_type,    *  2 Fundamental memory type *");
 832         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
 833                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
 834         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
 835                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
 836         printf("%-3d    : %02x %s\n", 5, spd->nrows,
 837                " spd->nrows        *  5 # of DIMM Banks *");
 838         printf("%-3d    : %02x %s\n", 6, spd->dataw_lsb,
 839                " spd->dataw_lsb,   *  6 Data Width lsb of this assembly *");
 840         printf("%-3d    : %02x %s\n", 7, spd->dataw_msb,
 841                " spd->dataw_msb,   *  7 Data Width msb of this assembly *");
 842         printf("%-3d    : %02x %s\n", 8, spd->voltage,
 843                " spd->voltage,     *  8 Voltage intf std of this assembly *");
 844         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
 845                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
 846         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
 847                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
 848         printf("%-3d    : %02x %s\n", 11, spd->config,
 849                " spd->config,      * 11 DIMM Configuration type *");
 850         printf("%-3d    : %02x %s\n", 12, spd->refresh,
 851                " spd->refresh,     * 12 Refresh Rate/Type *");
 852         printf("%-3d    : %02x %s\n", 13, spd->primw,
 853                " spd->primw,       * 13 Primary SDRAM Width *");
 854         printf("%-3d    : %02x %s\n", 14, spd->ecw,
 855                " spd->ecw,         * 14 Error Checking SDRAM width *");
 856         printf("%-3d    : %02x %s\n", 15, spd->min_delay,
 857                " spd->min_delay,   * 15 Back to Back Random Access *");
 858         printf("%-3d    : %02x %s\n", 16, spd->burstl,
 859                " spd->burstl,      * 16 Burst Lengths Supported *");
 860         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
 861                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
 862         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
 863                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
 864         printf("%-3d    : %02x %s\n", 19, spd->cs_lat,
 865                " spd->cs_lat,      * 19 Chip Select Latency *");
 866         printf("%-3d    : %02x %s\n", 20, spd->write_lat,
 867                " spd->write_lat,   * 20 Write Latency/Recovery *");
 868         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
 869                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
 870         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
 871                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
 872         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
 873                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
 874         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
 875                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
 876         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
 877                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
 878         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
 879                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
 880         printf("%-3d    : %02x %s\n", 27, spd->trp,
 881                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
 882         printf("%-3d    : %02x %s\n", 28, spd->trrd,
 883                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
 884         printf("%-3d    : %02x %s\n", 29, spd->trcd,
 885                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
 886         printf("%-3d    : %02x %s\n", 30, spd->tras,
 887                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
 888         printf("%-3d    : %02x %s\n", 31, spd->bank_dens,
 889                " spd->bank_dens,   * 31 Density of each bank on module *");
 890         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
 891                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
 892         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
 893                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
 894         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
 895                " spd->data_setup,  * 34 Data signal input setup time *");
 896         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
 897                " spd->data_hold,   * 35 Data signal input hold time *");
 898         printf("%-3d    : %02x %s\n", 36, spd->res_36_40[0],
 899                " spd->res_36_40[0], * 36 Reserved / tWR *");
 900         printf("%-3d    : %02x %s\n", 37, spd->res_36_40[1],
 901                " spd->res_36_40[1], * 37 Reserved / tWTR *");
 902         printf("%-3d    : %02x %s\n", 38, spd->res_36_40[2],
 903                " spd->res_36_40[2], * 38 Reserved / tRTP *");
 904         printf("%-3d    : %02x %s\n", 39, spd->res_36_40[3],
 905                " spd->res_36_40[3], * 39 Reserved / mem_probe *");
 906         printf("%-3d    : %02x %s\n", 40, spd->res_36_40[4],
 907                " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
 908         printf("%-3d    : %02x %s\n", 41, spd->trc,
 909                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
 910         printf("%-3d    : %02x %s\n", 42, spd->trfc,
 911                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
 912         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
 913                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
 914         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
 915                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
 916         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
 917                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
 918         printf("%-3d    : %02x %s\n", 46, spd->res_46,
 919                " spd->res_46,  * 46 Reserved/ PLL Relock time *");
 920         printf("%-3d    : %02x %s\n", 47, spd->dimm_height,
 921                " spd->dimm_height  * 47 SDRAM DIMM Height *");
 922
 923         printf("%-3d-%3d: ",  48, 61);
 924
 925         for (i = 0; i < 14; i++)
 926                 printf("%02x", spd->res_48_61[i]);
 927
 928         printf(" * 48-61 IDD in SPD and Reserved space *\n");
 929
 930         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
 931                " spd->spd_rev,     * 62 SPD Data Revision Code *");
 932         printf("%-3d    : %02x %s\n", 63, spd->cksum,
 933                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
 934         printf("%-3d-%3d: ",  64, 71);
 935
 936         for (i = 0; i < 8; i++)
 937                 printf("%02x", spd->mid[i]);
 938
 939         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
 940         printf("%-3d    : %02x %s\n", 72, spd->mloc,
 941                " spd->mloc,        * 72 Manufacturing Location *");
 942
 943         printf("%-3d-%3d: >>",  73, 90);
 944
 945         for (i = 0; i < 18; i++)
 946                 printf("%c", spd->mpart[i]);
 947
 948         printf("<<* 73 Manufacturer's Part Number *\n");
 949
 950         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
 951                "* 91 Revision Code *");
 952         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
 953                "* 93 Manufacturing Date *");
 954         printf("%-3d-%3d: ", 95, 98);
 955
 956         for (i = 0; i < 4; i++)
 957                 printf("%02x", spd->sernum[i]);
 958
 959         printf("* 95 Assembly Serial Number *\n");
 960
 961         printf("%-3d-%3d: ", 99, 127);
 962
 963         for (i = 0; i < 27; i++)
 964                 printf("%02x", spd->mspec[i]);
 965
 966         printf("* 99 Manufacturer Specific Data *\n");
 967 }
 968 #endif
 969
 970 #ifdef CONFIG_SYS_FSL_DDR2
 971 void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
 972 {
 973         unsigned int i;
 974
 975         printf("%-3d    : %02x %s\n", 0, spd->info_size,
 976                " spd->info_size,   *  0 # bytes written into serial memory *");
 977         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
 978                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
 979         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
 980                " spd->mem_type,    *  2 Fundamental memory type *");
 981         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
 982                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
 983         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
 984                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
 985         printf("%-3d    : %02x %s\n", 5, spd->mod_ranks,
 986                " spd->mod_ranks    *  5 # of Module Rows on this assembly *");
 987         printf("%-3d    : %02x %s\n", 6, spd->dataw,
 988                " spd->dataw,       *  6 Data Width of this assembly *");
 989         printf("%-3d    : %02x %s\n", 7, spd->res_7,
 990                " spd->res_7,       *  7 Reserved *");
 991         printf("%-3d    : %02x %s\n", 8, spd->voltage,
 992                " spd->voltage,     *  8 Voltage intf std of this assembly *");
 993         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
 994                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
 995         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
 996                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
 997         printf("%-3d    : %02x %s\n", 11, spd->config,
 998                " spd->config,      * 11 DIMM Configuration type *");
 999         printf("%-3d    : %02x %s\n", 12, spd->refresh,
1000                " spd->refresh,     * 12 Refresh Rate/Type *");
1001         printf("%-3d    : %02x %s\n", 13, spd->primw,
1002                " spd->primw,       * 13 Primary SDRAM Width *");
1003         printf("%-3d    : %02x %s\n", 14, spd->ecw,
1004                " spd->ecw,         * 14 Error Checking SDRAM width *");
1005         printf("%-3d    : %02x %s\n", 15, spd->res_15,
1006                " spd->res_15,      * 15 Reserved *");
1007         printf("%-3d    : %02x %s\n", 16, spd->burstl,
1008                " spd->burstl,      * 16 Burst Lengths Supported *");
1009         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
1010                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
1011         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
1012                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
1013         printf("%-3d    : %02x %s\n", 19, spd->mech_char,
1014                " spd->mech_char,   * 19 Mechanical Characteristics *");
1015         printf("%-3d    : %02x %s\n", 20, spd->dimm_type,
1016                " spd->dimm_type,   * 20 DIMM type *");
1017         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
1018                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
1019         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
1020                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
1021         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
1022                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
1023         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
1024                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
1025         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
1026                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
1027         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
1028                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
1029         printf("%-3d    : %02x %s\n", 27, spd->trp,
1030                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
1031         printf("%-3d    : %02x %s\n", 28, spd->trrd,
1032                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
1033         printf("%-3d    : %02x %s\n", 29, spd->trcd,
1034                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
1035         printf("%-3d    : %02x %s\n", 30, spd->tras,
1036                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
1037         printf("%-3d    : %02x %s\n", 31, spd->rank_dens,
1038                " spd->rank_dens,   * 31 Density of each rank on module *");
1039         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
1040                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
1041         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
1042                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
1043         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
1044                " spd->data_setup,  * 34 Data signal input setup time *");
1045         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
1046                " spd->data_hold,   * 35 Data signal input hold time *");
1047         printf("%-3d    : %02x %s\n", 36, spd->twr,
1048                " spd->twr,         * 36 Write Recovery time tWR *");
1049         printf("%-3d    : %02x %s\n", 37, spd->twtr,
1050                " spd->twtr,        * 37 Int write to read delay tWTR *");
1051         printf("%-3d    : %02x %s\n", 38, spd->trtp,
1052                " spd->trtp,        * 38 Int read to precharge delay tRTP *");
1053         printf("%-3d    : %02x %s\n", 39, spd->mem_probe,
1054                " spd->mem_probe,   * 39 Mem analysis probe characteristics *");
1055         printf("%-3d    : %02x %s\n", 40, spd->trctrfc_ext,
1056                " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
1057         printf("%-3d    : %02x %s\n", 41, spd->trc,
1058                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
1059         printf("%-3d    : %02x %s\n", 42, spd->trfc,
1060                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
1061         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
1062                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
1063         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
1064                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
1065         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
1066                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
1067         printf("%-3d    : %02x %s\n", 46, spd->pll_relock,
1068                " spd->pll_relock,  * 46 PLL Relock time *");
1069         printf("%-3d    : %02x %s\n", 47, spd->t_casemax,
1070                " spd->t_casemax,    * 47 t_casemax *");
1071         printf("%-3d    : %02x %s\n", 48, spd->psi_ta_dram,
1072                " spd->psi_ta_dram,   * 48 Thermal Resistance of DRAM Package "
1073                "from Top (Case) to Ambient (Psi T-A DRAM) *");
1074         printf("%-3d    : %02x %s\n", 49, spd->dt0_mode,
1075                " spd->dt0_mode,    * 49 DRAM Case Temperature Rise from "
1076                "Ambient due to Activate-Precharge/Mode Bits "
1077                "(DT0/Mode Bits) *)");
1078         printf("%-3d    : %02x %s\n", 50, spd->dt2n_dt2q,
1079                " spd->dt2n_dt2q,   * 50 DRAM Case Temperature Rise from "
1080                "Ambient due to Precharge/Quiet Standby "
1081                "(DT2N/DT2Q) *");
1082         printf("%-3d    : %02x %s\n", 51, spd->dt2p,
1083                " spd->dt2p,        * 51 DRAM Case Temperature Rise from "
1084                "Ambient due to Precharge Power-Down (DT2P) *");
1085         printf("%-3d    : %02x %s\n", 52, spd->dt3n,
1086                " spd->dt3n,        * 52 DRAM Case Temperature Rise from "
1087                "Ambient due to Active Standby (DT3N) *");
1088         printf("%-3d    : %02x %s\n", 53, spd->dt3pfast,
1089                " spd->dt3pfast,    * 53 DRAM Case Temperature Rise from "
1090                "Ambient due to Active Power-Down with Fast PDN Exit "
1091                "(DT3Pfast) *");
1092         printf("%-3d    : %02x %s\n", 54, spd->dt3pslow,
1093                " spd->dt3pslow,    * 54 DRAM Case Temperature Rise from "
1094                "Ambient due to Active Power-Down with Slow PDN Exit "
1095                "(DT3Pslow) *");
1096         printf("%-3d    : %02x %s\n", 55, spd->dt4r_dt4r4w,
1097                " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
1098                "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
1099                "(DT4R/DT4R4W Mode Bit) *");
1100         printf("%-3d    : %02x %s\n", 56, spd->dt5b,
1101                " spd->dt5b,        * 56 DRAM Case Temperature Rise from "
1102                "Ambient due to Burst Refresh (DT5B) *");
1103         printf("%-3d    : %02x %s\n", 57, spd->dt7,
1104                " spd->dt7,         * 57 DRAM Case Temperature Rise from "
1105                "Ambient due to Bank Interleave Reads with "
1106                "Auto-Precharge (DT7) *");
1107         printf("%-3d    : %02x %s\n", 58, spd->psi_ta_pll,
1108                " spd->psi_ta_pll,    * 58 Thermal Resistance of PLL Package form"
1109                " Top (Case) to Ambient (Psi T-A PLL) *");
1110         printf("%-3d    : %02x %s\n", 59, spd->psi_ta_reg,
1111                " spd->psi_ta_reg,    * 59 Thermal Reisitance of Register Package"
1112                " from Top (Case) to Ambient (Psi T-A Register) *");
1113         printf("%-3d    : %02x %s\n", 60, spd->dtpllactive,
1114                " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1115                "Ambient due to PLL Active (DT PLL Active) *");
1116         printf("%-3d    : %02x %s\n", 61, spd->dtregact,
1117                " spd->dtregact,    "
1118                "* 61 Register Case Temperature Rise from Ambient due to "
1119                "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1120         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
1121                " spd->spd_rev,     * 62 SPD Data Revision Code *");
1122         printf("%-3d    : %02x %s\n", 63, spd->cksum,
1123                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
1124
1125         printf("%-3d-%3d: ",  64, 71);
1126
1127         for (i = 0; i < 8; i++)
1128                 printf("%02x", spd->mid[i]);
1129
1130         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1131
1132         printf("%-3d    : %02x %s\n", 72, spd->mloc,
1133                " spd->mloc,        * 72 Manufacturing Location *");
1134
1135         printf("%-3d-%3d: >>",  73, 90);
1136         for (i = 0; i < 18; i++)
1137                 printf("%c", spd->mpart[i]);
1138
1139
1140         printf("<<* 73 Manufacturer's Part Number *\n");
1141
1142         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1143                "* 91 Revision Code *");
1144         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1145                "* 93 Manufacturing Date *");
1146         printf("%-3d-%3d: ", 95, 98);
1147
1148         for (i = 0; i < 4; i++)
1149                 printf("%02x", spd->sernum[i]);
1150
1151         printf("* 95 Assembly Serial Number *\n");
1152
1153         printf("%-3d-%3d: ", 99, 127);
1154         for (i = 0; i < 27; i++)
1155                 printf("%02x", spd->mspec[i]);
1156
1157
1158         printf("* 99 Manufacturer Specific Data *\n");
1159 }
1160 #endif
1161
1162 #ifdef CONFIG_SYS_FSL_DDR3
1163 void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1164 {
1165         unsigned int i;
1166
1167         /* General Section: Bytes 0-59 */
1168
1169 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1170 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1171         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1172
1173         PRINT_NXS(0, spd->info_size_crc,
1174                 "info_size_crc  bytes written into serial memory, "
1175                 "CRC coverage");
1176         PRINT_NXS(1, spd->spd_rev,
1177                 "spd_rev        SPD Revision");
1178         PRINT_NXS(2, spd->mem_type,
1179                 "mem_type       Key Byte / DRAM Device Type");
1180         PRINT_NXS(3, spd->module_type,
1181                 "module_type    Key Byte / Module Type");
1182         PRINT_NXS(4, spd->density_banks,
1183                 "density_banks  SDRAM Density and Banks");
1184         PRINT_NXS(5, spd->addressing,
1185                 "addressing     SDRAM Addressing");
1186         PRINT_NXS(6, spd->module_vdd,
1187                 "module_vdd     Module Nominal Voltage, VDD");
1188         PRINT_NXS(7, spd->organization,
1189                 "organization   Module Organization");
1190         PRINT_NXS(8, spd->bus_width,
1191                 "bus_width      Module Memory Bus Width");
1192         PRINT_NXS(9, spd->ftb_div,
1193                 "ftb_div        Fine Timebase (FTB) Dividend / Divisor");
1194         PRINT_NXS(10, spd->mtb_dividend,
1195                 "mtb_dividend   Medium Timebase (MTB) Dividend");
1196         PRINT_NXS(11, spd->mtb_divisor,
1197                 "mtb_divisor    Medium Timebase (MTB) Divisor");
1198         PRINT_NXS(12, spd->tck_min,
1199                   "tck_min        SDRAM Minimum Cycle Time");
1200         PRINT_NXS(13, spd->res_13,
1201                 "res_13         Reserved");
1202         PRINT_NXS(14, spd->caslat_lsb,
1203                 "caslat_lsb     CAS Latencies Supported, LSB");
1204         PRINT_NXS(15, spd->caslat_msb,
1205                 "caslat_msb     CAS Latencies Supported, MSB");
1206         PRINT_NXS(16, spd->taa_min,
1207                   "taa_min        Min CAS Latency Time");
1208         PRINT_NXS(17, spd->twr_min,
1209                   "twr_min        Min Write REcovery Time");
1210         PRINT_NXS(18, spd->trcd_min,
1211                   "trcd_min       Min RAS# to CAS# Delay Time");
1212         PRINT_NXS(19, spd->trrd_min,
1213                   "trrd_min       Min Row Active to Row Active Delay Time");
1214         PRINT_NXS(20, spd->trp_min,
1215                   "trp_min        Min Row Precharge Delay Time");
1216         PRINT_NXS(21, spd->tras_trc_ext,
1217                   "tras_trc_ext   Upper Nibbles for tRAS and tRC");
1218         PRINT_NXS(22, spd->tras_min_lsb,
1219                   "tras_min_lsb   Min Active to Precharge Delay Time, LSB");
1220         PRINT_NXS(23, spd->trc_min_lsb,
1221                   "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1222         PRINT_NXS(24, spd->trfc_min_lsb,
1223                   "trfc_min_lsb   Min Refresh Recovery Delay Time LSB");
1224         PRINT_NXS(25, spd->trfc_min_msb,
1225                   "trfc_min_msb   Min Refresh Recovery Delay Time MSB");
1226         PRINT_NXS(26, spd->twtr_min,
1227                   "twtr_min Min Internal Write to Read Command Delay Time");
1228         PRINT_NXS(27, spd->trtp_min,
1229                   "trtp_min "
1230                   "Min Internal Read to Precharge Command Delay Time");
1231         PRINT_NXS(28, spd->tfaw_msb,
1232                   "tfaw_msb       Upper Nibble for tFAW");
1233         PRINT_NXS(29, spd->tfaw_min,
1234                   "tfaw_min       Min Four Activate Window Delay Time");
1235         PRINT_NXS(30, spd->opt_features,
1236                 "opt_features   SDRAM Optional Features");
1237         PRINT_NXS(31, spd->therm_ref_opt,
1238                 "therm_ref_opt  SDRAM Thermal and Refresh Opts");
1239         PRINT_NXS(32, spd->therm_sensor,
1240                 "therm_sensor  SDRAM Thermal Sensor");
1241         PRINT_NXS(33, spd->device_type,
1242                 "device_type  SDRAM Device Type");
1243         PRINT_NXS(34, spd->fine_tck_min,
1244                   "fine_tck_min  Fine offset for tCKmin");
1245         PRINT_NXS(35, spd->fine_taa_min,
1246                   "fine_taa_min  Fine offset for tAAmin");
1247         PRINT_NXS(36, spd->fine_trcd_min,
1248                   "fine_trcd_min Fine offset for tRCDmin");
1249         PRINT_NXS(37, spd->fine_trp_min,
1250                   "fine_trp_min  Fine offset for tRPmin");
1251         PRINT_NXS(38, spd->fine_trc_min,
1252                   "fine_trc_min  Fine offset for tRCmin");
1253
1254         printf("%-3d-%3d: ",  39, 59);  /* Reserved, General Section */
1255
1256         for (i = 39; i <= 59; i++)
1257                 printf("%02x ", spd->res_39_59[i - 39]);
1258
1259         puts("\n");
1260
1261         switch (spd->module_type) {
1262         case 0x02:  /* UDIMM */
1263         case 0x03:  /* SO-DIMM */
1264         case 0x04:  /* Micro-DIMM */
1265         case 0x06:  /* Mini-UDIMM */
1266                 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1267                         "mod_height    (Unbuffered) Module Nominal Height");
1268                 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1269                         "mod_thickness (Unbuffered) Module Maximum Thickness");
1270                 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1271                         "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1272                 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1273                         "addr_mapping  (Unbuffered) Address mapping from "
1274                         "Edge Connector to DRAM");
1275                 break;
1276         case 0x01:  /* RDIMM */
1277         case 0x05:  /* Mini-RDIMM */
1278                 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1279                         "mod_height    (Registered) Module Nominal Height");
1280                 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1281                         "mod_thickness (Registered) Module Maximum Thickness");
1282                 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1283                         "ref_raw_card  (Registered) Reference Raw Card Used");
1284                 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1285                         "modu_attr     (Registered) DIMM Module Attributes");
1286                 PRINT_NXS(64, spd->mod_section.registered.thermal,
1287                         "thermal       (Registered) Thermal Heat "
1288                         "Spreader Solution");
1289                 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1290                         "reg_id_lo     (Registered) Register Manufacturer ID "
1291                         "Code, LSB");
1292                 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1293                         "reg_id_hi     (Registered) Register Manufacturer ID "
1294                         "Code, MSB");
1295                 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1296                         "reg_rev       (Registered) Register "
1297                         "Revision Number");
1298                 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1299                         "reg_type      (Registered) Register Type");
1300                 for (i = 69; i <= 76; i++) {
1301                         printf("%-3d    : %02x rcw[%d]\n", i,
1302                                 spd->mod_section.registered.rcw[i-69], i-69);
1303                 }
1304                 break;
1305         default:
1306                 /* Module-specific Section, Unsupported Module Type */
1307                 printf("%-3d-%3d: ", 60, 116);
1308
1309                 for (i = 60; i <= 116; i++)
1310                         printf("%02x", spd->mod_section.uc[i - 60]);
1311
1312                 break;
1313         }
1314
1315         /* Unique Module ID: Bytes 117-125 */
1316         PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1317         PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1318         PRINT_NXS(119, spd->mloc,     "Mfg Location");
1319         PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1320
1321         printf("%-3d-%3d: ", 122, 125);
1322
1323         for (i = 122; i <= 125; i++)
1324                 printf("%02x ", spd->sernum[i - 122]);
1325         printf("   Module Serial Number\n");
1326
1327         /* CRC: Bytes 126-127 */
1328         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1329
1330         /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1331         printf("%-3d-%3d: ", 128, 145);
1332         for (i = 128; i <= 145; i++)
1333                 printf("%02x ", spd->mpart[i - 128]);
1334         printf("   Mfg's Module Part Number\n");
1335
1336         PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1337                 "Module Revision code");
1338
1339         PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1340         PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1341
1342         printf("%-3d-%3d: ", 150, 175);
1343         for (i = 150; i <= 175; i++)
1344                 printf("%02x ", spd->msd[i - 150]);
1345         printf("   Mfg's Specific Data\n");
1346
1347         printf("%-3d-%3d: ", 176, 255);
1348         for (i = 176; i <= 255; i++)
1349                 printf("%02x", spd->cust[i - 176]);
1350         printf("   Mfg's Specific Data\n");
1351
1352 }
1353 #endif
1354
1355 #ifdef CONFIG_SYS_FSL_DDR4
1356 void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
1357 {
1358         unsigned int i;
1359
1360         /* General Section: Bytes 0-127 */
1361
1362 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1363 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1364         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1365
1366         PRINT_NXS(0, spd->info_size_crc,
1367                   "info_size_crc  bytes written into serial memory, CRC coverage");
1368         PRINT_NXS(1, spd->spd_rev,
1369                   "spd_rev        SPD Revision");
1370         PRINT_NXS(2, spd->mem_type,
1371                   "mem_type       Key Byte / DRAM Device Type");
1372         PRINT_NXS(3, spd->module_type,
1373                   "module_type    Key Byte / Module Type");
1374         PRINT_NXS(4, spd->density_banks,
1375                   "density_banks  SDRAM Density and Banks");
1376         PRINT_NXS(5, spd->addressing,
1377                   "addressing     SDRAM Addressing");
1378         PRINT_NXS(6, spd->package_type,
1379                   "package_type   Package type");
1380         PRINT_NXS(7, spd->opt_feature,
1381                   "opt_feature    Optional features");
1382         PRINT_NXS(8, spd->thermal_ref,
1383                   "thermal_ref    Thermal and Refresh options");
1384         PRINT_NXS(9, spd->oth_opt_features,
1385                   "oth_opt_features Other SDRAM optional features");
1386         PRINT_NXS(10, spd->res_10,
1387                   "res_10         Reserved");
1388         PRINT_NXS(11, spd->module_vdd,
1389                   "module_vdd     Module Nominal Voltage, VDD");
1390         PRINT_NXS(12, spd->organization,
1391                   "organization Module Organization");
1392         PRINT_NXS(13, spd->bus_width,
1393                   "bus_width      Module Memory Bus Width");
1394         PRINT_NXS(14, spd->therm_sensor,
1395                   "therm_sensor   Module Thermal Sensor");
1396         PRINT_NXS(15, spd->ext_type,
1397                   "ext_type       Extended module type");
1398         PRINT_NXS(16, spd->res_16,
1399                   "res_16       Reserved");
1400         PRINT_NXS(17, spd->timebases,
1401                   "timebases    MTb and FTB");
1402         PRINT_NXS(18, spd->tck_min,
1403                   "tck_min      tCKAVGmin");
1404         PRINT_NXS(19, spd->tck_max,
1405                   "tck_max      TCKAVGmax");
1406         PRINT_NXS(20, spd->caslat_b1,
1407                   "caslat_b1    CAS latencies, 1st byte");
1408         PRINT_NXS(21, spd->caslat_b2,
1409                   "caslat_b2    CAS latencies, 2nd byte");
1410         PRINT_NXS(22, spd->caslat_b3,
1411                   "caslat_b3    CAS latencies, 3rd byte ");
1412         PRINT_NXS(23, spd->caslat_b4,
1413                   "caslat_b4    CAS latencies, 4th byte");
1414         PRINT_NXS(24, spd->taa_min,
1415                   "taa_min      Min CAS Latency Time");
1416         PRINT_NXS(25, spd->trcd_min,
1417                   "trcd_min     Min RAS# to CAS# Delay Time");
1418         PRINT_NXS(26, spd->trp_min,
1419                   "trp_min      Min Row Precharge Delay Time");
1420         PRINT_NXS(27, spd->tras_trc_ext,
1421                   "tras_trc_ext Upper Nibbles for tRAS and tRC");
1422         PRINT_NXS(28, spd->tras_min_lsb,
1423                   "tras_min_lsb tRASmin, lsb");
1424         PRINT_NXS(29, spd->trc_min_lsb,
1425                   "trc_min_lsb  tRCmin, lsb");
1426         PRINT_NXS(30, spd->trfc1_min_lsb,
1427                   "trfc1_min_lsb  Min Refresh Recovery Delay Time, LSB");
1428         PRINT_NXS(31, spd->trfc1_min_msb,
1429                   "trfc1_min_msb  Min Refresh Recovery Delay Time, MSB ");
1430         PRINT_NXS(32, spd->trfc2_min_lsb,
1431                   "trfc2_min_lsb  Min Refresh Recovery Delay Time, LSB");
1432         PRINT_NXS(33, spd->trfc2_min_msb,
1433                   "trfc2_min_msb  Min Refresh Recovery Delay Time, MSB");
1434         PRINT_NXS(34, spd->trfc4_min_lsb,
1435                   "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
1436         PRINT_NXS(35, spd->trfc4_min_msb,
1437                   "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
1438         PRINT_NXS(36, spd->tfaw_msb,
1439                   "tfaw_msb      Upper Nibble for tFAW");
1440         PRINT_NXS(37, spd->tfaw_min,
1441                   "tfaw_min      tFAW, lsb");
1442         PRINT_NXS(38, spd->trrds_min,
1443                   "trrds_min     tRRD_Smin, MTB");
1444         PRINT_NXS(39, spd->trrdl_min,
1445                   "trrdl_min     tRRD_Lmin, MTB");
1446         PRINT_NXS(40, spd->tccdl_min,
1447                   "tccdl_min     tCCS_Lmin, MTB");
1448
1449         printf("%-3d-%3d: ", 41, 59);  /* Reserved, General Section */
1450         for (i = 41; i <= 59; i++)
1451                 printf("%02x ", spd->res_41[i - 41]);
1452
1453         puts("\n");
1454         printf("%-3d-%3d: ", 60, 77);
1455         for (i = 60; i <= 77; i++)
1456                 printf("%02x ", spd->mapping[i - 60]);
1457         puts("   mapping[] Connector to SDRAM bit map\n");
1458
1459         PRINT_NXS(117, spd->fine_tccdl_min,
1460                   "fine_tccdl_min Fine offset for tCCD_Lmin");
1461         PRINT_NXS(118, spd->fine_trrdl_min,
1462                   "fine_trrdl_min Fine offset for tRRD_Lmin");
1463         PRINT_NXS(119, spd->fine_trrds_min,
1464                   "fine_trrds_min Fine offset for tRRD_Smin");
1465         PRINT_NXS(120, spd->fine_trc_min,
1466                   "fine_trc_min   Fine offset for tRCmin");
1467         PRINT_NXS(121, spd->fine_trp_min,
1468                   "fine_trp_min   Fine offset for tRPmin");
1469         PRINT_NXS(122, spd->fine_trcd_min,
1470                   "fine_trcd_min  Fine offset for tRCDmin");
1471         PRINT_NXS(123, spd->fine_taa_min,
1472                   "fine_taa_min   Fine offset for tAAmin");
1473         PRINT_NXS(124, spd->fine_tck_max,
1474                   "fine_tck_max   Fine offset for tCKAVGmax");
1475         PRINT_NXS(125, spd->fine_tck_min,
1476                   "fine_tck_min   Fine offset for tCKAVGmin");
1477
1478         /* CRC: Bytes 126-127 */
1479         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1480
1481         switch (spd->module_type) {
1482         case 0x02:  /* UDIMM */
1483         case 0x03:  /* SO-DIMM */
1484                 PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
1485                           "mod_height    (Unbuffered) Module Nominal Height");
1486                 PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
1487                           "mod_thickness (Unbuffered) Module Maximum Thickness");
1488                 PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
1489                           "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1490                 PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
1491                           "addr_mapping  (Unbuffered) Address mapping from Edge Connector to DRAM");
1492                 PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
1493                             spd->mod_section.unbuffered.crc[1], "  Module CRC");
1494                 break;
1495         case 0x01:  /* RDIMM */
1496                 PRINT_NXS(128, spd->mod_section.registered.mod_height,
1497                           "mod_height    (Registered) Module Nominal Height");
1498                 PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
1499                           "mod_thickness (Registered) Module Maximum Thickness");
1500                 PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
1501                           "ref_raw_card  (Registered) Reference Raw Card Used");
1502                 PRINT_NXS(131, spd->mod_section.registered.modu_attr,
1503                           "modu_attr     (Registered) DIMM Module Attributes");
1504                 PRINT_NXS(132, spd->mod_section.registered.thermal,
1505                           "thermal       (Registered) Thermal Heat Spreader Solution");
1506                 PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
1507                           "reg_id_lo     (Registered) Register Manufacturer ID Code, LSB");
1508                 PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
1509                           "reg_id_hi     (Registered) Register Manufacturer ID Code, MSB");
1510                 PRINT_NXS(135, spd->mod_section.registered.reg_rev,
1511                           "reg_rev       (Registered) Register Revision Number");
1512                 PRINT_NXS(136, spd->mod_section.registered.reg_map,
1513                           "reg_map       (Registered) Address mapping");
1514                 PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
1515                             spd->mod_section.registered.crc[1], "  Module CRC");
1516                 break;
1517         case 0x04:  /* LRDIMM */
1518                 PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
1519                           "mod_height    (Loadreduced) Module Nominal Height");
1520                 PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
1521                           "mod_thickness (Loadreduced) Module Maximum Thickness");
1522                 PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
1523                           "ref_raw_card  (Loadreduced) Reference Raw Card Used");
1524                 PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
1525                           "modu_attr     (Loadreduced) DIMM Module Attributes");
1526                 PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
1527                           "thermal       (Loadreduced) Thermal Heat Spreader Solution");
1528                 PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
1529                           "reg_id_lo     (Loadreduced) Register Manufacturer ID Code, LSB");
1530                 PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
1531                           "reg_id_hi     (Loadreduced) Register Manufacturer ID Code, MSB");
1532                 PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
1533                           "reg_rev       (Loadreduced) Register Revision Number");
1534                 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
1535                           "reg_map       (Loadreduced) Address mapping");
1536                 PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
1537                           "reg_drv       (Loadreduced) Reg output drive strength");
1538                 PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
1539                           "reg_drv_ck    (Loadreduced) Reg output drive strength for CK");
1540                 PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
1541                           "data_buf_rev  (Loadreduced) Data Buffer Revision Numbe");
1542                 PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
1543                           "vrefqe_r0     (Loadreduced) DRAM VrefDQ for Package Rank 0");
1544                 PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
1545                           "vrefqe_r1     (Loadreduced) DRAM VrefDQ for Package Rank 1");
1546                 PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
1547                           "vrefqe_r2     (Loadreduced) DRAM VrefDQ for Package Rank 2");
1548                 PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
1549                           "vrefqe_r3     (Loadreduced) DRAM VrefDQ for Package Rank 3");
1550                 PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
1551                           "data_intf     (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
1552                 PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
1553                           "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1554                 PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
1555                           "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1556                 PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
1557                           "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1558                 PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
1559                           "dram_drv      (Loadreduced) DRAM Drive Strength");
1560                 PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
1561                           "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1562                 PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
1563                           "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1564                 PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
1565                           "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1566                 PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
1567                           "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
1568                 PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
1569                           "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
1570                 PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
1571                           "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
1572                 PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
1573                             spd->mod_section.loadreduced.crc[1],
1574                             "  Module CRC");
1575                 break;
1576         default:
1577                 /* Module-specific Section, Unsupported Module Type */
1578                 printf("%-3d-%3d: ", 128, 255);
1579
1580                 for (i = 128; i <= 255; i++)
1581                         printf("%02x", spd->mod_section.uc[i - 60]);
1582
1583                 break;
1584         }
1585
1586         /* Unique Module ID: Bytes 320-383 */
1587         PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1588         PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1589         PRINT_NXS(322, spd->mloc,     "Mfg Location");
1590         PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
1591
1592         printf("%-3d-%3d: ", 325, 328);
1593
1594         for (i = 325; i <= 328; i++)
1595                 printf("%02x ", spd->sernum[i - 325]);
1596         printf("   Module Serial Number\n");
1597
1598         printf("%-3d-%3d: ", 329, 348);
1599         for (i = 329; i <= 348; i++)
1600                 printf("%02x ", spd->mpart[i - 329]);
1601         printf("   Mfg's Module Part Number\n");
1602
1603         PRINT_NXS(349, spd->mrev, "Module Revision code");
1604         PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1605         PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1606         PRINT_NXS(352, spd->stepping, "DRAM stepping");
1607
1608         printf("%-3d-%3d: ", 353, 381);
1609         for (i = 353; i <= 381; i++)
1610                 printf("%02x ", spd->msd[i - 353]);
1611         printf("   Mfg's Specific Data\n");
1612 }
1613 #endif
1614
1615 static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1616 {
1617 #if defined(CONFIG_SYS_FSL_DDR1)
1618         ddr1_spd_dump(spd);
1619 #elif defined(CONFIG_SYS_FSL_DDR2)
1620         ddr2_spd_dump(spd);
1621 #elif defined(CONFIG_SYS_FSL_DDR3)
1622         ddr3_spd_dump(spd);
1623 #elif defined(CONFIG_SYS_FSL_DDR4)
1624         ddr4_spd_dump(spd);
1625 #endif
1626 }
1627
1628 static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1629                         unsigned int ctrl_mask,
1630                         unsigned int dimm_mask,
1631                         unsigned int do_mask)
1632 {
1633         unsigned int i, j, retval;
1634
1635         /* STEP 1:  DIMM SPD data */
1636         if (do_mask & STEP_GET_SPD) {
1637                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1638                         if (!(ctrl_mask & (1 << i)))
1639                                 continue;
1640
1641                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1642                                 if (!(dimm_mask & (1 << j)))
1643                                         continue;
1644
1645                                 printf("SPD info:  Controller=%u "
1646                                                 "DIMM=%u\n", i, j);
1647                                 generic_spd_dump(
1648                                         &(pinfo->spd_installed_dimms[i][j]));
1649                                 printf("\n");
1650                         }
1651                         printf("\n");
1652                 }
1653                 printf("\n");
1654         }
1655
1656         /* STEP 2:  DIMM Parameters */
1657         if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1658                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1659                         if (!(ctrl_mask & (1 << i)))
1660                                 continue;
1661                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1662                                 if (!(dimm_mask & (1 << j)))
1663                                         continue;
1664                                 printf("DIMM parameters:  Controller=%u "
1665                                                 "DIMM=%u\n", i, j);
1666                                 print_dimm_parameters(
1667                                         &(pinfo->dimm_params[i][j]));
1668                                 printf("\n");
1669                         }
1670                         printf("\n");
1671                 }
1672                 printf("\n");
1673         }
1674
1675         /* STEP 3:  Common Parameters */
1676         if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1677                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1678                         if (!(ctrl_mask & (1 << i)))
1679                                 continue;
1680                         printf("\"lowest common\" DIMM parameters:  "
1681                                         "Controller=%u\n", i);
1682                         print_lowest_common_dimm_parameters(
1683                                 &pinfo->common_timing_params[i]);
1684                         printf("\n");
1685                 }
1686                 printf("\n");
1687         }
1688
1689         /* STEP 4:  User Configuration Options */
1690         if (do_mask & STEP_GATHER_OPTS) {
1691                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1692                         if (!(ctrl_mask & (1 << i)))
1693                                 continue;
1694                         printf("User Config Options: Controller=%u\n", i);
1695                         print_memctl_options(&pinfo->memctl_opts[i]);
1696                         printf("\n");
1697                 }
1698                 printf("\n");
1699         }
1700
1701         /* STEP 5:  Address assignment */
1702         if (do_mask & STEP_ASSIGN_ADDRESSES) {
1703                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1704                         if (!(ctrl_mask & (1 << i)))
1705                                 continue;
1706                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1707                                 printf("Address Assignment: Controller=%u "
1708                                                 "DIMM=%u\n", i, j);
1709                                 printf("Don't have this functionality yet\n");
1710                         }
1711                         printf("\n");
1712                 }
1713                 printf("\n");
1714         }
1715
1716         /* STEP 6:  computed controller register values */
1717         if (do_mask & STEP_COMPUTE_REGS) {
1718                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1719                         if (!(ctrl_mask & (1 << i)))
1720                                 continue;
1721                         printf("Computed Register Values: Controller=%u\n", i);
1722                         print_fsl_memctl_config_regs(
1723                                 &pinfo->fsl_ddr_config_reg[i]);
1724                         retval = check_fsl_memctl_config_regs(
1725                                 &pinfo->fsl_ddr_config_reg[i]);
1726                         if (retval) {
1727                                 printf("check_fsl_memctl_config_regs "
1728                                         "result = %u\n", retval);
1729                         }
1730                         printf("\n");
1731                 }
1732                 printf("\n");
1733         }
1734 }
1735
1736 struct data_strings {
1737         const char *data_name;
1738         unsigned int step_mask;
1739         unsigned int dimm_number_required;
1740 };
1741
1742 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1743
1744 static unsigned int fsl_ddr_parse_interactive_cmd(
1745         char **argv,
1746         int argc,
1747         unsigned int *pstep_mask,
1748         unsigned int *pctlr_mask,
1749         unsigned int *pdimm_mask,
1750         unsigned int *pdimm_number_required
1751          ) {
1752
1753         static const struct data_strings options[] = {
1754                 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1755                 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1756                 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1757                 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1758                 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1759                 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1760         };
1761         static const unsigned int n_opts = ARRAY_SIZE(options);
1762
1763         unsigned int i, j;
1764         unsigned int error = 0;
1765
1766         for (i = 1; i < argc; i++) {
1767                 unsigned int matched = 0;
1768
1769                 for (j = 0; j < n_opts; j++) {
1770                         if (strcmp(options[j].data_name, argv[i]) != 0)
1771                                 continue;
1772                         *pstep_mask |= options[j].step_mask;
1773                         *pdimm_number_required =
1774                                 options[j].dimm_number_required;
1775                         matched = 1;
1776                         break;
1777                 }
1778
1779                 if (matched)
1780                         continue;
1781
1782                 if (argv[i][0] == 'c') {
1783                         char c = argv[i][1];
1784                         if (isdigit(c))
1785                                 *pctlr_mask |= 1 << (c - '0');
1786                         continue;
1787                 }
1788
1789                 if (argv[i][0] == 'd') {
1790                         char c = argv[i][1];
1791                         if (isdigit(c))
1792                                 *pdimm_mask |= 1 << (c - '0');
1793                         continue;
1794                 }
1795
1796                 printf("unknown arg %s\n", argv[i]);
1797                 *pstep_mask = 0;
1798                 error = 1;
1799                 break;
1800         }
1801
1802         return error;
1803 }
1804
1805 int fsl_ddr_interactive_env_var_exists(void)
1806 {
1807         char buffer[CONFIG_SYS_CBSIZE];
1808
1809         if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
1810                 return 1;
1811
1812         return 0;
1813 }
1814
1815 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
1816 {
1817         unsigned long long ddrsize;
1818         const char *prompt = "FSL DDR>";
1819         char buffer[CONFIG_SYS_CBSIZE];
1820         char buffer2[CONFIG_SYS_CBSIZE];
1821         char *p = NULL;
1822         char *argv[CONFIG_SYS_MAXARGS + 1];     /* NULL terminated */
1823         int argc;
1824         unsigned int next_step = STEP_GET_SPD;
1825         const char *usage = {
1826                 "commands:\n"
1827                 "print      print SPD and intermediate computed data\n"
1828                 "reset      reboot machine\n"
1829                 "recompute  reload SPD and options to default and recompute regs\n"
1830                 "edit       modify spd, parameter, or option\n"
1831                 "compute    recompute registers from current next_step to end\n"
1832                 "copy       copy parameters\n"
1833                 "next_step  shows current next_step\n"
1834                 "help       this message\n"
1835                 "go         program the memory controller and continue with u-boot\n"
1836         };
1837
1838         if (var_is_set) {
1839                 if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
1840                         p = buffer2;
1841                 } else {
1842                         var_is_set = 0;
1843                 }
1844         }
1845
1846         /*
1847          * The strategy for next_step is that it points to the next
1848          * step in the computation process that needs to be done.
1849          */
1850         while (1) {
1851                 if (var_is_set) {
1852                         char *pend = strchr(p, ';');
1853                         if (pend) {
1854                                 /* found command separator, copy sub-command */
1855                                 *pend = '\0';
1856                                 strcpy(buffer, p);
1857                                 p = pend + 1;
1858                         } else {
1859                                 /* separator not found, copy whole string */
1860                                 strcpy(buffer, p);
1861                                 p = NULL;
1862                                 var_is_set = 0;
1863                         }
1864                 } else {
1865                         /*
1866                          * No need to worry for buffer overflow here in
1867                          * this function;  readline() maxes out at CFG_CBSIZE
1868                          */
1869                         readline_into_buffer(prompt, buffer, 0);
1870                 }
1871                 argc = parse_line(buffer, argv);
1872                 if (argc == 0)
1873                         continue;
1874
1875
1876                 if (strcmp(argv[0], "help") == 0) {
1877                         puts(usage);
1878                         continue;
1879                 }
1880
1881                 if (strcmp(argv[0], "next_step") == 0) {
1882                         printf("next_step = 0x%02X (%s)\n",
1883                                next_step,
1884                                step_to_string(next_step));
1885                         continue;
1886                 }
1887
1888                 if (strcmp(argv[0], "copy") == 0) {
1889                         unsigned int error = 0;
1890                         unsigned int step_mask = 0;
1891                         unsigned int src_ctlr_mask = 0;
1892                         unsigned int src_dimm_mask = 0;
1893                         unsigned int dimm_number_required = 0;
1894                         unsigned int src_ctlr_num = 0;
1895                         unsigned int src_dimm_num = 0;
1896                         unsigned int dst_ctlr_num = -1;
1897                         unsigned int dst_dimm_num = -1;
1898                         unsigned int i, num_dest_parms;
1899
1900                         if (argc == 1) {
1901                                 printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
1902                                 continue;
1903                         }
1904
1905                         error = fsl_ddr_parse_interactive_cmd(
1906                                 argv, argc,
1907                                 &step_mask,
1908                                 &src_ctlr_mask,
1909                                 &src_dimm_mask,
1910                                 &dimm_number_required
1911                         );
1912
1913                         /* XXX: only dimm_number_required and step_mask will
1914                            be used by this function.  Parse the controller and
1915                            DIMM number separately because it is easier.  */
1916
1917                         if (error)
1918                                 continue;
1919
1920                         /* parse source destination controller / DIMM */
1921
1922                         num_dest_parms = dimm_number_required ? 2 : 1;
1923
1924                         for (i = 0; i < argc; i++) {
1925                                 if (argv[i][0] == 'c') {
1926                                         char c = argv[i][1];
1927                                         if (isdigit(c)) {
1928                                                 src_ctlr_num = (c - '0');
1929                                                 break;
1930                                         }
1931                                 }
1932                         }
1933
1934                         for (i = 0; i < argc; i++) {
1935                                 if (argv[i][0] == 'd') {
1936                                         char c = argv[i][1];
1937                                         if (isdigit(c)) {
1938                                                 src_dimm_num = (c - '0');
1939                                                 break;
1940                                         }
1941                                 }
1942                         }
1943
1944                         /* parse destination controller / DIMM */
1945
1946                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
1947                                 if (argv[i][0] == 'c') {
1948                                         char c = argv[i][1];
1949                                         if (isdigit(c)) {
1950                                                 dst_ctlr_num = (c - '0');
1951                                                 break;
1952                                         }
1953                                 }
1954                         }
1955
1956                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
1957                                 if (argv[i][0] == 'd') {
1958                                         char c = argv[i][1];
1959                                         if (isdigit(c)) {
1960                                                 dst_dimm_num = (c - '0');
1961                                                 break;
1962                                         }
1963                                 }
1964                         }
1965
1966                         /* TODO: validate inputs */
1967
1968                         debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
1969                                 src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
1970
1971
1972                         switch (step_mask) {
1973
1974                         case STEP_GET_SPD:
1975                                 memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
1976                                         &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
1977                                         sizeof(pinfo->spd_installed_dimms[0][0]));
1978                                 break;
1979
1980                         case STEP_COMPUTE_DIMM_PARMS:
1981                                 memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
1982                                         &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
1983                                         sizeof(pinfo->dimm_params[0][0]));
1984                                 break;
1985
1986                         case STEP_COMPUTE_COMMON_PARMS:
1987                                 memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
1988                                         &(pinfo->common_timing_params[src_ctlr_num]),
1989                                         sizeof(pinfo->common_timing_params[0]));
1990                                 break;
1991
1992                         case STEP_GATHER_OPTS:
1993                                 memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
1994                                         &(pinfo->memctl_opts[src_ctlr_num]),
1995                                         sizeof(pinfo->memctl_opts[0]));
1996                                 break;
1997
1998                         /* someday be able to have addresses to copy addresses... */
1999
2000                         case STEP_COMPUTE_REGS:
2001                                 memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
2002                                         &(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
2003                                         sizeof(pinfo->memctl_opts[0]));
2004                                 break;
2005
2006                         default:
2007                                 printf("unexpected step_mask value\n");
2008                         }
2009
2010                         continue;
2011
2012                 }
2013
2014                 if (strcmp(argv[0], "edit") == 0) {
2015                         unsigned int error = 0;
2016                         unsigned int step_mask = 0;
2017                         unsigned int ctlr_mask = 0;
2018                         unsigned int dimm_mask = 0;
2019                         char *p_element = NULL;
2020                         char *p_value = NULL;
2021                         unsigned int dimm_number_required = 0;
2022                         unsigned int ctrl_num;
2023                         unsigned int dimm_num;
2024
2025                         if (argc == 1) {
2026                                 /* Only the element and value must be last */
2027                                 printf("edit <c#> <d#> "
2028                                         "<spd|dimmparms|commonparms|opts|"
2029                                         "addresses|regs> <element> <value>\n");
2030                                 printf("for spd, specify byte number for "
2031                                         "element\n");
2032                                 continue;
2033                         }
2034
2035                         error = fsl_ddr_parse_interactive_cmd(
2036                                 argv, argc - 2,
2037                                 &step_mask,
2038                                 &ctlr_mask,
2039                                 &dimm_mask,
2040                                 &dimm_number_required
2041                         );
2042
2043                         if (error)
2044                                 continue;
2045
2046
2047                         /* Check arguments */
2048
2049                         /* ERROR: If no steps were found */
2050                         if (step_mask == 0) {
2051                                 printf("Error: No valid steps were specified "
2052                                                 "in argument.\n");
2053                                 continue;
2054                         }
2055
2056                         /* ERROR: If multiple steps were found */
2057                         if (step_mask & (step_mask - 1)) {
2058                                 printf("Error: Multiple steps specified in "
2059                                                 "argument.\n");
2060                                 continue;
2061                         }
2062
2063                         /* ERROR: Controller not specified */
2064                         if (ctlr_mask == 0) {
2065                                 printf("Error: controller number not "
2066                                         "specified or no element and "
2067                                         "value specified\n");
2068                                 continue;
2069                         }
2070
2071                         if (ctlr_mask & (ctlr_mask - 1)) {
2072                                 printf("Error: multiple controllers "
2073                                                 "specified, %X\n", ctlr_mask);
2074                                 continue;
2075                         }
2076
2077                         /* ERROR: DIMM number not specified */
2078                         if (dimm_number_required && dimm_mask == 0) {
2079                                 printf("Error: DIMM number number not "
2080                                         "specified or no element and "
2081                                         "value specified\n");
2082                                 continue;
2083                         }
2084
2085                         if (dimm_mask & (dimm_mask - 1)) {
2086                                 printf("Error: multipled DIMMs specified\n");
2087                                 continue;
2088                         }
2089
2090                         p_element = argv[argc - 2];
2091                         p_value = argv[argc - 1];
2092
2093                         ctrl_num = __ilog2(ctlr_mask);
2094                         dimm_num = __ilog2(dimm_mask);
2095
2096                         switch (step_mask) {
2097                         case STEP_GET_SPD:
2098                                 {
2099                                         unsigned int element_num;
2100                                         unsigned int value;
2101
2102                                         element_num = simple_strtoul(p_element,
2103                                                                      NULL, 0);
2104                                         value = simple_strtoul(p_value,
2105                                                                NULL, 0);
2106                                         fsl_ddr_spd_edit(pinfo,
2107                                                                ctrl_num,
2108                                                                dimm_num,
2109                                                                element_num,
2110                                                                value);
2111                                         next_step = STEP_COMPUTE_DIMM_PARMS;
2112                                 }
2113                                 break;
2114
2115                         case STEP_COMPUTE_DIMM_PARMS:
2116                                 fsl_ddr_dimm_parameters_edit(
2117                                                  pinfo, ctrl_num, dimm_num,
2118                                                  p_element, p_value);
2119                                 next_step = STEP_COMPUTE_COMMON_PARMS;
2120                                 break;
2121
2122                         case STEP_COMPUTE_COMMON_PARMS:
2123                                 lowest_common_dimm_parameters_edit(pinfo,
2124                                                 ctrl_num, p_element, p_value);
2125                                 next_step = STEP_GATHER_OPTS;
2126                                 break;
2127
2128                         case STEP_GATHER_OPTS:
2129                                 fsl_ddr_options_edit(pinfo, ctrl_num,
2130                                                            p_element, p_value);
2131                                 next_step = STEP_ASSIGN_ADDRESSES;
2132                                 break;
2133
2134                         case STEP_ASSIGN_ADDRESSES:
2135                                 printf("editing of address assignment "
2136                                                 "not yet implemented\n");
2137                                 break;
2138
2139                         case STEP_COMPUTE_REGS:
2140                                 {
2141                                         fsl_ddr_regs_edit(pinfo,
2142                                                                 ctrl_num,
2143                                                                 p_element,
2144                                                                 p_value);
2145                                         next_step = STEP_PROGRAM_REGS;
2146                                 }
2147                                 break;
2148
2149                         default:
2150                                 printf("programming error\n");
2151                                 while (1)
2152                                         ;
2153                                 break;
2154                         }
2155                         continue;
2156                 }
2157
2158                 if (strcmp(argv[0], "reset") == 0) {
2159                         /*
2160                          * Reboot machine.
2161                          * Args don't seem to matter because this
2162                          * doesn't return
2163                          */
2164                         do_reset(NULL, 0, 0, NULL);
2165                         printf("Reset didn't work\n");
2166                 }
2167
2168                 if (strcmp(argv[0], "recompute") == 0) {
2169                         /*
2170                          * Recalculate everything, starting with
2171                          * loading SPD EEPROM from DIMMs
2172                          */
2173                         next_step = STEP_GET_SPD;
2174                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2175                         continue;
2176                 }
2177
2178                 if (strcmp(argv[0], "compute") == 0) {
2179                         /*
2180                          * Compute rest of steps starting at
2181                          * the current next_step/
2182                          */
2183                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2184                         continue;
2185                 }
2186
2187                 if (strcmp(argv[0], "print") == 0) {
2188                         unsigned int error = 0;
2189                         unsigned int step_mask = 0;
2190                         unsigned int ctlr_mask = 0;
2191                         unsigned int dimm_mask = 0;
2192                         unsigned int dimm_number_required = 0;
2193
2194                         if (argc == 1) {
2195                                 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
2196                                   "[commonparms] [opts] [addresses] [regs]\n");
2197                                 continue;
2198                         }
2199
2200                         error = fsl_ddr_parse_interactive_cmd(
2201                                 argv, argc,
2202                                 &step_mask,
2203                                 &ctlr_mask,
2204                                 &dimm_mask,
2205                                 &dimm_number_required
2206                         );
2207
2208                         if (error)
2209                                 continue;
2210
2211                         /* If no particular controller was found, print all */
2212                         if (ctlr_mask == 0)
2213                                 ctlr_mask = 0xFF;
2214
2215                         /* If no particular dimm was found, print all dimms. */
2216                         if (dimm_mask == 0)
2217                                 dimm_mask = 0xFF;
2218
2219                         /* If no steps were found, print all steps. */
2220                         if (step_mask == 0)
2221                                 step_mask = STEP_ALL;
2222
2223                         fsl_ddr_printinfo(pinfo, ctlr_mask,
2224                                                 dimm_mask, step_mask);
2225                         continue;
2226                 }
2227
2228                 if (strcmp(argv[0], "go") == 0) {
2229                         if (next_step)
2230                                 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2231                         break;
2232                 }
2233
2234                 printf("unknown command %s\n", argv[0]);
2235         }
2236
2237         debug("end of memory = %llu\n", (u64)ddrsize);
2238
2239         return ddrsize;
2240 }