2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/processor.h>
12 #include <fsl_ddr_sdram.h>
14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
19 unsigned int ctrl_num, int step)
22 struct ccsr_ddr __iomem *ddr =
23 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
25 #if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
26 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
31 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
35 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
37 * Set the DDR IO receiver to an acceptable bias point.
41 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
42 if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
43 SDRAM_CFG_SDRAM_TYPE_DDR2)
44 out_be32(&gur->ddrioovcr, 0x90000000);
46 out_be32(&gur->ddrioovcr, 0xA8000000);
50 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
52 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
53 out_be32(&ddr->cs0_config, regs->cs[i].config);
56 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
57 out_be32(&ddr->cs1_config, regs->cs[i].config);
60 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
61 out_be32(&ddr->cs2_config, regs->cs[i].config);
64 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
65 out_be32(&ddr->cs3_config, regs->cs[i].config);
69 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
70 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
71 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
72 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
73 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
74 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
75 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
76 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
77 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
78 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
79 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
80 out_be32(&ddr->init_addr, regs->ddr_init_addr);
81 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
84 * 200 painful micro-seconds must elapse between
85 * the DDR clock setup and the DDR config enable.
88 asm volatile("sync;isync");
90 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
92 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
93 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
94 udelay(10000); /* throttle polling rate */