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1 /*
2  * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <hwconfig.h>
9 #include <fsl_ddr_sdram.h>
10
11 #include <fsl_ddr.h>
12
13 /*
14  * Use our own stack based buffer before relocation to allow accessing longer
15  * hwconfig strings that might be in the environment before we've relocated.
16  * This is pretty fragile on both the use of stack and if the buffer is big
17  * enough. However we will get a warning from getenv_f for the later.
18  */
19
20 /* Board-specific functions defined in each board's ddr.c */
21 extern void fsl_ddr_board_options(memctl_options_t *popts,
22                 dimm_params_t *pdimm,
23                 unsigned int ctrl_num);
24
25 struct dynamic_odt {
26         unsigned int odt_rd_cfg;
27         unsigned int odt_wr_cfg;
28         unsigned int odt_rtt_norm;
29         unsigned int odt_rtt_wr;
30 };
31
32 #ifdef CONFIG_SYS_FSL_DDR4
33 /* Quad rank is not verified yet due availability.
34  * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
35  */
36 static const struct dynamic_odt single_Q[4] = {
37         {       /* cs0 */
38                 FSL_DDR_ODT_NEVER,
39                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
40                 DDR4_RTT_34_OHM,        /* unverified */
41                 DDR4_RTT_120_OHM
42         },
43         {       /* cs1 */
44                 FSL_DDR_ODT_NEVER,
45                 FSL_DDR_ODT_NEVER,
46                 DDR4_RTT_OFF,
47                 DDR4_RTT_120_OHM
48         },
49         {       /* cs2 */
50                 FSL_DDR_ODT_NEVER,
51                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
52                 DDR4_RTT_34_OHM,
53                 DDR4_RTT_120_OHM
54         },
55         {       /* cs3 */
56                 FSL_DDR_ODT_NEVER,
57                 FSL_DDR_ODT_NEVER,      /* tied high */
58                 DDR4_RTT_OFF,
59                 DDR4_RTT_120_OHM
60         }
61 };
62
63 static const struct dynamic_odt single_D[4] = {
64         {       /* cs0 */
65                 FSL_DDR_ODT_NEVER,
66                 FSL_DDR_ODT_ALL,
67                 DDR4_RTT_40_OHM,
68                 DDR4_RTT_OFF
69         },
70         {       /* cs1 */
71                 FSL_DDR_ODT_NEVER,
72                 FSL_DDR_ODT_NEVER,
73                 DDR4_RTT_OFF,
74                 DDR4_RTT_OFF
75         },
76         {0, 0, 0, 0},
77         {0, 0, 0, 0}
78 };
79
80 static const struct dynamic_odt single_S[4] = {
81         {       /* cs0 */
82                 FSL_DDR_ODT_NEVER,
83                 FSL_DDR_ODT_ALL,
84                 DDR4_RTT_40_OHM,
85                 DDR4_RTT_OFF
86         },
87         {0, 0, 0, 0},
88         {0, 0, 0, 0},
89         {0, 0, 0, 0},
90 };
91
92 static const struct dynamic_odt dual_DD[4] = {
93         {       /* cs0 */
94                 FSL_DDR_ODT_NEVER,
95                 FSL_DDR_ODT_SAME_DIMM,
96                 DDR4_RTT_120_OHM,
97                 DDR4_RTT_OFF
98         },
99         {       /* cs1 */
100                 FSL_DDR_ODT_OTHER_DIMM,
101                 FSL_DDR_ODT_OTHER_DIMM,
102                 DDR4_RTT_34_OHM,
103                 DDR4_RTT_OFF
104         },
105         {       /* cs2 */
106                 FSL_DDR_ODT_NEVER,
107                 FSL_DDR_ODT_SAME_DIMM,
108                 DDR4_RTT_120_OHM,
109                 DDR4_RTT_OFF
110         },
111         {       /* cs3 */
112                 FSL_DDR_ODT_OTHER_DIMM,
113                 FSL_DDR_ODT_OTHER_DIMM,
114                 DDR4_RTT_34_OHM,
115                 DDR4_RTT_OFF
116         }
117 };
118
119 static const struct dynamic_odt dual_DS[4] = {
120         {       /* cs0 */
121                 FSL_DDR_ODT_NEVER,
122                 FSL_DDR_ODT_SAME_DIMM,
123                 DDR4_RTT_120_OHM,
124                 DDR4_RTT_OFF
125         },
126         {       /* cs1 */
127                 FSL_DDR_ODT_OTHER_DIMM,
128                 FSL_DDR_ODT_OTHER_DIMM,
129                 DDR4_RTT_34_OHM,
130                 DDR4_RTT_OFF
131         },
132         {       /* cs2 */
133                 FSL_DDR_ODT_OTHER_DIMM,
134                 FSL_DDR_ODT_ALL,
135                 DDR4_RTT_34_OHM,
136                 DDR4_RTT_120_OHM
137         },
138         {0, 0, 0, 0}
139 };
140 static const struct dynamic_odt dual_SD[4] = {
141         {       /* cs0 */
142                 FSL_DDR_ODT_OTHER_DIMM,
143                 FSL_DDR_ODT_ALL,
144                 DDR4_RTT_34_OHM,
145                 DDR4_RTT_120_OHM
146         },
147         {0, 0, 0, 0},
148         {       /* cs2 */
149                 FSL_DDR_ODT_NEVER,
150                 FSL_DDR_ODT_SAME_DIMM,
151                 DDR4_RTT_120_OHM,
152                 DDR4_RTT_OFF
153         },
154         {       /* cs3 */
155                 FSL_DDR_ODT_OTHER_DIMM,
156                 FSL_DDR_ODT_OTHER_DIMM,
157                 DDR4_RTT_34_OHM,
158                 DDR4_RTT_OFF
159         }
160 };
161
162 static const struct dynamic_odt dual_SS[4] = {
163         {       /* cs0 */
164                 FSL_DDR_ODT_OTHER_DIMM,
165                 FSL_DDR_ODT_ALL,
166                 DDR4_RTT_34_OHM,
167                 DDR4_RTT_120_OHM
168         },
169         {0, 0, 0, 0},
170         {       /* cs2 */
171                 FSL_DDR_ODT_OTHER_DIMM,
172                 FSL_DDR_ODT_ALL,
173                 DDR4_RTT_34_OHM,
174                 DDR4_RTT_120_OHM
175         },
176         {0, 0, 0, 0}
177 };
178
179 static const struct dynamic_odt dual_D0[4] = {
180         {       /* cs0 */
181                 FSL_DDR_ODT_NEVER,
182                 FSL_DDR_ODT_SAME_DIMM,
183                 DDR4_RTT_40_OHM,
184                 DDR4_RTT_OFF
185         },
186         {       /* cs1 */
187                 FSL_DDR_ODT_NEVER,
188                 FSL_DDR_ODT_NEVER,
189                 DDR4_RTT_OFF,
190                 DDR4_RTT_OFF
191         },
192         {0, 0, 0, 0},
193         {0, 0, 0, 0}
194 };
195
196 static const struct dynamic_odt dual_0D[4] = {
197         {0, 0, 0, 0},
198         {0, 0, 0, 0},
199         {       /* cs2 */
200                 FSL_DDR_ODT_NEVER,
201                 FSL_DDR_ODT_SAME_DIMM,
202                 DDR4_RTT_40_OHM,
203                 DDR4_RTT_OFF
204         },
205         {       /* cs3 */
206                 FSL_DDR_ODT_NEVER,
207                 FSL_DDR_ODT_NEVER,
208                 DDR4_RTT_OFF,
209                 DDR4_RTT_OFF
210         }
211 };
212
213 static const struct dynamic_odt dual_S0[4] = {
214         {       /* cs0 */
215                 FSL_DDR_ODT_NEVER,
216                 FSL_DDR_ODT_CS,
217                 DDR4_RTT_40_OHM,
218                 DDR4_RTT_OFF
219         },
220         {0, 0, 0, 0},
221         {0, 0, 0, 0},
222         {0, 0, 0, 0}
223
224 };
225
226 static const struct dynamic_odt dual_0S[4] = {
227         {0, 0, 0, 0},
228         {0, 0, 0, 0},
229         {       /* cs2 */
230                 FSL_DDR_ODT_NEVER,
231                 FSL_DDR_ODT_CS,
232                 DDR4_RTT_40_OHM,
233                 DDR4_RTT_OFF
234         },
235         {0, 0, 0, 0}
236
237 };
238
239 static const struct dynamic_odt odt_unknown[4] = {
240         {       /* cs0 */
241                 FSL_DDR_ODT_NEVER,
242                 FSL_DDR_ODT_CS,
243                 DDR4_RTT_120_OHM,
244                 DDR4_RTT_OFF
245         },
246         {       /* cs1 */
247                 FSL_DDR_ODT_NEVER,
248                 FSL_DDR_ODT_CS,
249                 DDR4_RTT_120_OHM,
250                 DDR4_RTT_OFF
251         },
252         {       /* cs2 */
253                 FSL_DDR_ODT_NEVER,
254                 FSL_DDR_ODT_CS,
255                 DDR4_RTT_120_OHM,
256                 DDR4_RTT_OFF
257         },
258         {       /* cs3 */
259                 FSL_DDR_ODT_NEVER,
260                 FSL_DDR_ODT_CS,
261                 DDR4_RTT_120_OHM,
262                 DDR4_RTT_OFF
263         }
264 };
265 #elif defined(CONFIG_SYS_FSL_DDR3)
266 static const struct dynamic_odt single_Q[4] = {
267         {       /* cs0 */
268                 FSL_DDR_ODT_NEVER,
269                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
270                 DDR3_RTT_20_OHM,
271                 DDR3_RTT_120_OHM
272         },
273         {       /* cs1 */
274                 FSL_DDR_ODT_NEVER,
275                 FSL_DDR_ODT_NEVER,      /* tied high */
276                 DDR3_RTT_OFF,
277                 DDR3_RTT_120_OHM
278         },
279         {       /* cs2 */
280                 FSL_DDR_ODT_NEVER,
281                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
282                 DDR3_RTT_20_OHM,
283                 DDR3_RTT_120_OHM
284         },
285         {       /* cs3 */
286                 FSL_DDR_ODT_NEVER,
287                 FSL_DDR_ODT_NEVER,      /* tied high */
288                 DDR3_RTT_OFF,
289                 DDR3_RTT_120_OHM
290         }
291 };
292
293 static const struct dynamic_odt single_D[4] = {
294         {       /* cs0 */
295                 FSL_DDR_ODT_NEVER,
296                 FSL_DDR_ODT_ALL,
297                 DDR3_RTT_40_OHM,
298                 DDR3_RTT_OFF
299         },
300         {       /* cs1 */
301                 FSL_DDR_ODT_NEVER,
302                 FSL_DDR_ODT_NEVER,
303                 DDR3_RTT_OFF,
304                 DDR3_RTT_OFF
305         },
306         {0, 0, 0, 0},
307         {0, 0, 0, 0}
308 };
309
310 static const struct dynamic_odt single_S[4] = {
311         {       /* cs0 */
312                 FSL_DDR_ODT_NEVER,
313                 FSL_DDR_ODT_ALL,
314                 DDR3_RTT_40_OHM,
315                 DDR3_RTT_OFF
316         },
317         {0, 0, 0, 0},
318         {0, 0, 0, 0},
319         {0, 0, 0, 0},
320 };
321
322 static const struct dynamic_odt dual_DD[4] = {
323         {       /* cs0 */
324                 FSL_DDR_ODT_NEVER,
325                 FSL_DDR_ODT_SAME_DIMM,
326                 DDR3_RTT_120_OHM,
327                 DDR3_RTT_OFF
328         },
329         {       /* cs1 */
330                 FSL_DDR_ODT_OTHER_DIMM,
331                 FSL_DDR_ODT_OTHER_DIMM,
332                 DDR3_RTT_30_OHM,
333                 DDR3_RTT_OFF
334         },
335         {       /* cs2 */
336                 FSL_DDR_ODT_NEVER,
337                 FSL_DDR_ODT_SAME_DIMM,
338                 DDR3_RTT_120_OHM,
339                 DDR3_RTT_OFF
340         },
341         {       /* cs3 */
342                 FSL_DDR_ODT_OTHER_DIMM,
343                 FSL_DDR_ODT_OTHER_DIMM,
344                 DDR3_RTT_30_OHM,
345                 DDR3_RTT_OFF
346         }
347 };
348
349 static const struct dynamic_odt dual_DS[4] = {
350         {       /* cs0 */
351                 FSL_DDR_ODT_NEVER,
352                 FSL_DDR_ODT_SAME_DIMM,
353                 DDR3_RTT_120_OHM,
354                 DDR3_RTT_OFF
355         },
356         {       /* cs1 */
357                 FSL_DDR_ODT_OTHER_DIMM,
358                 FSL_DDR_ODT_OTHER_DIMM,
359                 DDR3_RTT_30_OHM,
360                 DDR3_RTT_OFF
361         },
362         {       /* cs2 */
363                 FSL_DDR_ODT_OTHER_DIMM,
364                 FSL_DDR_ODT_ALL,
365                 DDR3_RTT_20_OHM,
366                 DDR3_RTT_120_OHM
367         },
368         {0, 0, 0, 0}
369 };
370 static const struct dynamic_odt dual_SD[4] = {
371         {       /* cs0 */
372                 FSL_DDR_ODT_OTHER_DIMM,
373                 FSL_DDR_ODT_ALL,
374                 DDR3_RTT_20_OHM,
375                 DDR3_RTT_120_OHM
376         },
377         {0, 0, 0, 0},
378         {       /* cs2 */
379                 FSL_DDR_ODT_NEVER,
380                 FSL_DDR_ODT_SAME_DIMM,
381                 DDR3_RTT_120_OHM,
382                 DDR3_RTT_OFF
383         },
384         {       /* cs3 */
385                 FSL_DDR_ODT_OTHER_DIMM,
386                 FSL_DDR_ODT_OTHER_DIMM,
387                 DDR3_RTT_20_OHM,
388                 DDR3_RTT_OFF
389         }
390 };
391
392 static const struct dynamic_odt dual_SS[4] = {
393         {       /* cs0 */
394                 FSL_DDR_ODT_OTHER_DIMM,
395                 FSL_DDR_ODT_ALL,
396                 DDR3_RTT_30_OHM,
397                 DDR3_RTT_120_OHM
398         },
399         {0, 0, 0, 0},
400         {       /* cs2 */
401                 FSL_DDR_ODT_OTHER_DIMM,
402                 FSL_DDR_ODT_ALL,
403                 DDR3_RTT_30_OHM,
404                 DDR3_RTT_120_OHM
405         },
406         {0, 0, 0, 0}
407 };
408
409 static const struct dynamic_odt dual_D0[4] = {
410         {       /* cs0 */
411                 FSL_DDR_ODT_NEVER,
412                 FSL_DDR_ODT_SAME_DIMM,
413                 DDR3_RTT_40_OHM,
414                 DDR3_RTT_OFF
415         },
416         {       /* cs1 */
417                 FSL_DDR_ODT_NEVER,
418                 FSL_DDR_ODT_NEVER,
419                 DDR3_RTT_OFF,
420                 DDR3_RTT_OFF
421         },
422         {0, 0, 0, 0},
423         {0, 0, 0, 0}
424 };
425
426 static const struct dynamic_odt dual_0D[4] = {
427         {0, 0, 0, 0},
428         {0, 0, 0, 0},
429         {       /* cs2 */
430                 FSL_DDR_ODT_NEVER,
431                 FSL_DDR_ODT_SAME_DIMM,
432                 DDR3_RTT_40_OHM,
433                 DDR3_RTT_OFF
434         },
435         {       /* cs3 */
436                 FSL_DDR_ODT_NEVER,
437                 FSL_DDR_ODT_NEVER,
438                 DDR3_RTT_OFF,
439                 DDR3_RTT_OFF
440         }
441 };
442
443 static const struct dynamic_odt dual_S0[4] = {
444         {       /* cs0 */
445                 FSL_DDR_ODT_NEVER,
446                 FSL_DDR_ODT_CS,
447                 DDR3_RTT_40_OHM,
448                 DDR3_RTT_OFF
449         },
450         {0, 0, 0, 0},
451         {0, 0, 0, 0},
452         {0, 0, 0, 0}
453
454 };
455
456 static const struct dynamic_odt dual_0S[4] = {
457         {0, 0, 0, 0},
458         {0, 0, 0, 0},
459         {       /* cs2 */
460                 FSL_DDR_ODT_NEVER,
461                 FSL_DDR_ODT_CS,
462                 DDR3_RTT_40_OHM,
463                 DDR3_RTT_OFF
464         },
465         {0, 0, 0, 0}
466
467 };
468
469 static const struct dynamic_odt odt_unknown[4] = {
470         {       /* cs0 */
471                 FSL_DDR_ODT_NEVER,
472                 FSL_DDR_ODT_CS,
473                 DDR3_RTT_120_OHM,
474                 DDR3_RTT_OFF
475         },
476         {       /* cs1 */
477                 FSL_DDR_ODT_NEVER,
478                 FSL_DDR_ODT_CS,
479                 DDR3_RTT_120_OHM,
480                 DDR3_RTT_OFF
481         },
482         {       /* cs2 */
483                 FSL_DDR_ODT_NEVER,
484                 FSL_DDR_ODT_CS,
485                 DDR3_RTT_120_OHM,
486                 DDR3_RTT_OFF
487         },
488         {       /* cs3 */
489                 FSL_DDR_ODT_NEVER,
490                 FSL_DDR_ODT_CS,
491                 DDR3_RTT_120_OHM,
492                 DDR3_RTT_OFF
493         }
494 };
495 #else   /* CONFIG_SYS_FSL_DDR3 */
496 static const struct dynamic_odt single_Q[4] = {
497         {0, 0, 0, 0},
498         {0, 0, 0, 0},
499         {0, 0, 0, 0},
500         {0, 0, 0, 0}
501 };
502
503 static const struct dynamic_odt single_D[4] = {
504         {       /* cs0 */
505                 FSL_DDR_ODT_NEVER,
506                 FSL_DDR_ODT_ALL,
507                 DDR2_RTT_150_OHM,
508                 DDR2_RTT_OFF
509         },
510         {       /* cs1 */
511                 FSL_DDR_ODT_NEVER,
512                 FSL_DDR_ODT_NEVER,
513                 DDR2_RTT_OFF,
514                 DDR2_RTT_OFF
515         },
516         {0, 0, 0, 0},
517         {0, 0, 0, 0}
518 };
519
520 static const struct dynamic_odt single_S[4] = {
521         {       /* cs0 */
522                 FSL_DDR_ODT_NEVER,
523                 FSL_DDR_ODT_ALL,
524                 DDR2_RTT_150_OHM,
525                 DDR2_RTT_OFF
526         },
527         {0, 0, 0, 0},
528         {0, 0, 0, 0},
529         {0, 0, 0, 0},
530 };
531
532 static const struct dynamic_odt dual_DD[4] = {
533         {       /* cs0 */
534                 FSL_DDR_ODT_OTHER_DIMM,
535                 FSL_DDR_ODT_OTHER_DIMM,
536                 DDR2_RTT_75_OHM,
537                 DDR2_RTT_OFF
538         },
539         {       /* cs1 */
540                 FSL_DDR_ODT_NEVER,
541                 FSL_DDR_ODT_NEVER,
542                 DDR2_RTT_OFF,
543                 DDR2_RTT_OFF
544         },
545         {       /* cs2 */
546                 FSL_DDR_ODT_OTHER_DIMM,
547                 FSL_DDR_ODT_OTHER_DIMM,
548                 DDR2_RTT_75_OHM,
549                 DDR2_RTT_OFF
550         },
551         {       /* cs3 */
552                 FSL_DDR_ODT_NEVER,
553                 FSL_DDR_ODT_NEVER,
554                 DDR2_RTT_OFF,
555                 DDR2_RTT_OFF
556         }
557 };
558
559 static const struct dynamic_odt dual_DS[4] = {
560         {       /* cs0 */
561                 FSL_DDR_ODT_OTHER_DIMM,
562                 FSL_DDR_ODT_OTHER_DIMM,
563                 DDR2_RTT_75_OHM,
564                 DDR2_RTT_OFF
565         },
566         {       /* cs1 */
567                 FSL_DDR_ODT_NEVER,
568                 FSL_DDR_ODT_NEVER,
569                 DDR2_RTT_OFF,
570                 DDR2_RTT_OFF
571         },
572         {       /* cs2 */
573                 FSL_DDR_ODT_OTHER_DIMM,
574                 FSL_DDR_ODT_OTHER_DIMM,
575                 DDR2_RTT_75_OHM,
576                 DDR2_RTT_OFF
577         },
578         {0, 0, 0, 0}
579 };
580
581 static const struct dynamic_odt dual_SD[4] = {
582         {       /* cs0 */
583                 FSL_DDR_ODT_OTHER_DIMM,
584                 FSL_DDR_ODT_OTHER_DIMM,
585                 DDR2_RTT_75_OHM,
586                 DDR2_RTT_OFF
587         },
588         {0, 0, 0, 0},
589         {       /* cs2 */
590                 FSL_DDR_ODT_OTHER_DIMM,
591                 FSL_DDR_ODT_OTHER_DIMM,
592                 DDR2_RTT_75_OHM,
593                 DDR2_RTT_OFF
594         },
595         {       /* cs3 */
596                 FSL_DDR_ODT_NEVER,
597                 FSL_DDR_ODT_NEVER,
598                 DDR2_RTT_OFF,
599                 DDR2_RTT_OFF
600         }
601 };
602
603 static const struct dynamic_odt dual_SS[4] = {
604         {       /* cs0 */
605                 FSL_DDR_ODT_OTHER_DIMM,
606                 FSL_DDR_ODT_OTHER_DIMM,
607                 DDR2_RTT_75_OHM,
608                 DDR2_RTT_OFF
609         },
610         {0, 0, 0, 0},
611         {       /* cs2 */
612                 FSL_DDR_ODT_OTHER_DIMM,
613                 FSL_DDR_ODT_OTHER_DIMM,
614                 DDR2_RTT_75_OHM,
615                 DDR2_RTT_OFF
616         },
617         {0, 0, 0, 0}
618 };
619
620 static const struct dynamic_odt dual_D0[4] = {
621         {       /* cs0 */
622                 FSL_DDR_ODT_NEVER,
623                 FSL_DDR_ODT_ALL,
624                 DDR2_RTT_150_OHM,
625                 DDR2_RTT_OFF
626         },
627         {       /* cs1 */
628                 FSL_DDR_ODT_NEVER,
629                 FSL_DDR_ODT_NEVER,
630                 DDR2_RTT_OFF,
631                 DDR2_RTT_OFF
632         },
633         {0, 0, 0, 0},
634         {0, 0, 0, 0}
635 };
636
637 static const struct dynamic_odt dual_0D[4] = {
638         {0, 0, 0, 0},
639         {0, 0, 0, 0},
640         {       /* cs2 */
641                 FSL_DDR_ODT_NEVER,
642                 FSL_DDR_ODT_ALL,
643                 DDR2_RTT_150_OHM,
644                 DDR2_RTT_OFF
645         },
646         {       /* cs3 */
647                 FSL_DDR_ODT_NEVER,
648                 FSL_DDR_ODT_NEVER,
649                 DDR2_RTT_OFF,
650                 DDR2_RTT_OFF
651         }
652 };
653
654 static const struct dynamic_odt dual_S0[4] = {
655         {       /* cs0 */
656                 FSL_DDR_ODT_NEVER,
657                 FSL_DDR_ODT_CS,
658                 DDR2_RTT_150_OHM,
659                 DDR2_RTT_OFF
660         },
661         {0, 0, 0, 0},
662         {0, 0, 0, 0},
663         {0, 0, 0, 0}
664
665 };
666
667 static const struct dynamic_odt dual_0S[4] = {
668         {0, 0, 0, 0},
669         {0, 0, 0, 0},
670         {       /* cs2 */
671                 FSL_DDR_ODT_NEVER,
672                 FSL_DDR_ODT_CS,
673                 DDR2_RTT_150_OHM,
674                 DDR2_RTT_OFF
675         },
676         {0, 0, 0, 0}
677
678 };
679
680 static const struct dynamic_odt odt_unknown[4] = {
681         {       /* cs0 */
682                 FSL_DDR_ODT_NEVER,
683                 FSL_DDR_ODT_CS,
684                 DDR2_RTT_75_OHM,
685                 DDR2_RTT_OFF
686         },
687         {       /* cs1 */
688                 FSL_DDR_ODT_NEVER,
689                 FSL_DDR_ODT_NEVER,
690                 DDR2_RTT_OFF,
691                 DDR2_RTT_OFF
692         },
693         {       /* cs2 */
694                 FSL_DDR_ODT_NEVER,
695                 FSL_DDR_ODT_CS,
696                 DDR2_RTT_75_OHM,
697                 DDR2_RTT_OFF
698         },
699         {       /* cs3 */
700                 FSL_DDR_ODT_NEVER,
701                 FSL_DDR_ODT_NEVER,
702                 DDR2_RTT_OFF,
703                 DDR2_RTT_OFF
704         }
705 };
706 #endif
707
708 /*
709  * Automatically seleect bank interleaving mode based on DIMMs
710  * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
711  * This function only deal with one or two slots per controller.
712  */
713 static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
714 {
715 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
716         if (pdimm[0].n_ranks == 4)
717                 return FSL_DDR_CS0_CS1_CS2_CS3;
718         else if (pdimm[0].n_ranks == 2)
719                 return FSL_DDR_CS0_CS1;
720 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
721 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
722         if (pdimm[0].n_ranks == 4)
723                 return FSL_DDR_CS0_CS1_CS2_CS3;
724 #endif
725         if (pdimm[0].n_ranks == 2) {
726                 if (pdimm[1].n_ranks == 2)
727                         return FSL_DDR_CS0_CS1_CS2_CS3;
728                 else
729                         return FSL_DDR_CS0_CS1;
730         }
731 #endif
732         return 0;
733 }
734
735 unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
736                         memctl_options_t *popts,
737                         dimm_params_t *pdimm,
738                         unsigned int ctrl_num)
739 {
740         unsigned int i;
741         char buffer[HWCONFIG_BUFFER_SIZE];
742         char *buf = NULL;
743 #if defined(CONFIG_SYS_FSL_DDR3) || \
744         defined(CONFIG_SYS_FSL_DDR2) || \
745         defined(CONFIG_SYS_FSL_DDR4)
746         const struct dynamic_odt *pdodt = odt_unknown;
747 #endif
748         ulong ddr_freq;
749
750         /*
751          * Extract hwconfig from environment since we have not properly setup
752          * the environment but need it for ddr config params
753          */
754         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
755                 buf = buffer;
756
757 #if defined(CONFIG_SYS_FSL_DDR3) || \
758         defined(CONFIG_SYS_FSL_DDR2) || \
759         defined(CONFIG_SYS_FSL_DDR4)
760         /* Chip select options. */
761 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
762         switch (pdimm[0].n_ranks) {
763         case 1:
764                 pdodt = single_S;
765                 break;
766         case 2:
767                 pdodt = single_D;
768                 break;
769         case 4:
770                 pdodt = single_Q;
771                 break;
772         }
773 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
774         switch (pdimm[0].n_ranks) {
775 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
776         case 4:
777                 pdodt = single_Q;
778                 if (pdimm[1].n_ranks)
779                         printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
780                 break;
781 #endif
782         case 2:
783                 switch (pdimm[1].n_ranks) {
784                 case 2:
785                         pdodt = dual_DD;
786                         break;
787                 case 1:
788                         pdodt = dual_DS;
789                         break;
790                 case 0:
791                         pdodt = dual_D0;
792                         break;
793                 }
794                 break;
795         case 1:
796                 switch (pdimm[1].n_ranks) {
797                 case 2:
798                         pdodt = dual_SD;
799                         break;
800                 case 1:
801                         pdodt = dual_SS;
802                         break;
803                 case 0:
804                         pdodt = dual_S0;
805                         break;
806                 }
807                 break;
808         case 0:
809                 switch (pdimm[1].n_ranks) {
810                 case 2:
811                         pdodt = dual_0D;
812                         break;
813                 case 1:
814                         pdodt = dual_0S;
815                         break;
816                 }
817                 break;
818         }
819 #endif  /* CONFIG_DIMM_SLOTS_PER_CTLR */
820 #endif  /* CONFIG_SYS_FSL_DDR2, 3, 4 */
821
822         /* Pick chip-select local options. */
823         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
824 #if defined(CONFIG_SYS_FSL_DDR3) || \
825         defined(CONFIG_SYS_FSL_DDR2) || \
826         defined(CONFIG_SYS_FSL_DDR4)
827                 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
828                 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
829                 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
830                 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
831 #else
832                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
833                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
834 #endif
835                 popts->cs_local_opts[i].auto_precharge = 0;
836         }
837
838         /* Pick interleaving mode. */
839
840         /*
841          * 0 = no interleaving
842          * 1 = interleaving between 2 controllers
843          */
844         popts->memctl_interleaving = 0;
845
846         /*
847          * 0 = cacheline
848          * 1 = page
849          * 2 = (logical) bank
850          * 3 = superbank (only if CS interleaving is enabled)
851          */
852         popts->memctl_interleaving_mode = 0;
853
854         /*
855          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
856          * 1: page:      bit to the left of the column bits selects the memctl
857          * 2: bank:      bit to the left of the bank bits selects the memctl
858          * 3: superbank: bit to the left of the chip select selects the memctl
859          *
860          * NOTE: ba_intlv (rank interleaving) is independent of memory
861          * controller interleaving; it is only within a memory controller.
862          * Must use superbank interleaving if rank interleaving is used and
863          * memory controller interleaving is enabled.
864          */
865
866         /*
867          * 0 = no
868          * 0x40 = CS0,CS1
869          * 0x20 = CS2,CS3
870          * 0x60 = CS0,CS1 + CS2,CS3
871          * 0x04 = CS0,CS1,CS2,CS3
872          */
873         popts->ba_intlv_ctl = 0;
874
875         /* Memory Organization Parameters */
876         popts->registered_dimm_en = common_dimm->all_dimms_registered;
877
878         /* Operational Mode Paramters */
879
880         /* Pick ECC modes */
881         popts->ecc_mode = 0;              /* 0 = disabled, 1 = enabled */
882 #ifdef CONFIG_DDR_ECC
883         if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
884                 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
885                         popts->ecc_mode = 1;
886         } else
887                 popts->ecc_mode = 1;
888 #endif
889         popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
890
891         /*
892          * Choose DQS config
893          * 0 for DDR1
894          * 1 for DDR2
895          */
896 #if defined(CONFIG_SYS_FSL_DDR1)
897         popts->dqs_config = 0;
898 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
899         popts->dqs_config = 1;
900 #endif
901
902         /* Choose self-refresh during sleep. */
903         popts->self_refresh_in_sleep = 1;
904
905         /* Choose dynamic power management mode. */
906         popts->dynamic_power = 0;
907
908         /*
909          * check first dimm for primary sdram width
910          * presuming all dimms are similar
911          * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
912          */
913 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
914         if (pdimm[0].n_ranks != 0) {
915                 if ((pdimm[0].data_width >= 64) && \
916                         (pdimm[0].data_width <= 72))
917                         popts->data_bus_width = 0;
918                 else if ((pdimm[0].data_width >= 32) || \
919                         (pdimm[0].data_width <= 40))
920                         popts->data_bus_width = 1;
921                 else {
922                         panic("Error: data width %u is invalid!\n",
923                                 pdimm[0].data_width);
924                 }
925         }
926 #else
927         if (pdimm[0].n_ranks != 0) {
928                 if (pdimm[0].primary_sdram_width == 64)
929                         popts->data_bus_width = 0;
930                 else if (pdimm[0].primary_sdram_width == 32)
931                         popts->data_bus_width = 1;
932                 else if (pdimm[0].primary_sdram_width == 16)
933                         popts->data_bus_width = 2;
934                 else {
935                         panic("Error: primary sdram width %u is invalid!\n",
936                                 pdimm[0].primary_sdram_width);
937                 }
938         }
939 #endif
940
941         popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
942
943         /* Choose burst length. */
944 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
945 #if defined(CONFIG_E500MC)
946         popts->otf_burst_chop_en = 0;   /* on-the-fly burst chop disable */
947         popts->burst_length = DDR_BL8;  /* Fixed 8-beat burst len */
948 #else
949         if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
950                 /* 32-bit or 16-bit bus */
951                 popts->otf_burst_chop_en = 0;
952                 popts->burst_length = DDR_BL8;
953         } else {
954                 popts->otf_burst_chop_en = 1;   /* on-the-fly burst chop */
955                 popts->burst_length = DDR_OTF;  /* on-the-fly BC4 and BL8 */
956         }
957 #endif
958 #else
959         popts->burst_length = DDR_BL4;  /* has to be 4 for DDR2 */
960 #endif
961
962         /* Choose ddr controller address mirror mode */
963 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
964         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
965                 if (pdimm[i].n_ranks) {
966                         popts->mirrored_dimm = pdimm[i].mirrored_dimm;
967                         break;
968                 }
969         }
970 #endif
971
972         /* Global Timing Parameters. */
973         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
974
975         /* Pick a caslat override. */
976         popts->cas_latency_override = 0;
977         popts->cas_latency_override_value = 3;
978         if (popts->cas_latency_override) {
979                 debug("using caslat override value = %u\n",
980                        popts->cas_latency_override_value);
981         }
982
983         /* Decide whether to use the computed derated latency */
984         popts->use_derated_caslat = 0;
985
986         /* Choose an additive latency. */
987         popts->additive_latency_override = 0;
988         popts->additive_latency_override_value = 3;
989         if (popts->additive_latency_override) {
990                 debug("using additive latency override value = %u\n",
991                        popts->additive_latency_override_value);
992         }
993
994         /*
995          * 2T_EN setting
996          *
997          * Factors to consider for 2T_EN:
998          *      - number of DIMMs installed
999          *      - number of components, number of active ranks
1000          *      - how much time you want to spend playing around
1001          */
1002         popts->twot_en = 0;
1003         popts->threet_en = 0;
1004
1005         /* for RDIMM, address parity enable */
1006         popts->ap_en = 1;
1007
1008         /*
1009          * BSTTOPRE precharge interval
1010          *
1011          * Set this to 0 for global auto precharge
1012          * The value of 0x100 has been used for DDR1, DDR2, DDR3.
1013          * It is not wrong. Any value should be OK. The performance depends on
1014          * applications. There is no one good value for all. One way to set
1015          * is to use 1/4 of refint value.
1016          */
1017         popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
1018                          >> 2;
1019
1020         /*
1021          * Window for four activates -- tFAW
1022          *
1023          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
1024          * FIXME: varies depending upon number of column addresses or data
1025          * FIXME: width, was considering looking at pdimm->primary_sdram_width
1026          */
1027 #if defined(CONFIG_SYS_FSL_DDR1)
1028         popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
1029
1030 #elif defined(CONFIG_SYS_FSL_DDR2)
1031         /*
1032          * x4/x8;  some datasheets have 35000
1033          * x16 wide columns only?  Use 50000?
1034          */
1035         popts->tfaw_window_four_activates_ps = 37500;
1036
1037 #else
1038         popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
1039 #endif
1040         popts->zq_en = 0;
1041         popts->wrlvl_en = 0;
1042 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1043         /*
1044          * due to ddr3 dimm is fly-by topology
1045          * we suggest to enable write leveling to
1046          * meet the tQDSS under different loading.
1047          */
1048         popts->wrlvl_en = 1;
1049         popts->zq_en = 1;
1050         popts->wrlvl_override = 0;
1051 #endif
1052
1053         /*
1054          * Check interleaving configuration from environment.
1055          * Please refer to doc/README.fsl-ddr for the detail.
1056          *
1057          * If memory controller interleaving is enabled, then the data
1058          * bus widths must be programmed identically for all memory controllers.
1059          *
1060          * Attempt to set all controllers to the same chip select
1061          * interleaving mode. It will do a best effort to get the
1062          * requested ranks interleaved together such that the result
1063          * should be a subset of the requested configuration.
1064          *
1065          * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
1066          * with 256 Byte is enabled.
1067          */
1068 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
1069         if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
1070 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1071                 ;
1072 #else
1073                 goto done;
1074 #endif
1075         if (pdimm[0].n_ranks == 0) {
1076                 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
1077                 popts->memctl_interleaving = 0;
1078                 goto done;
1079         }
1080         popts->memctl_interleaving = 1;
1081 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1082         popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
1083         popts->memctl_interleaving = 1;
1084         debug("256 Byte interleaving\n");
1085 #else
1086         /*
1087          * test null first. if CONFIG_HWCONFIG is not defined
1088          * hwconfig_arg_cmp returns non-zero
1089          */
1090         if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
1091                                     "null", buf)) {
1092                 popts->memctl_interleaving = 0;
1093                 debug("memory controller interleaving disabled.\n");
1094         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1095                                         "ctlr_intlv",
1096                                         "cacheline", buf)) {
1097                 popts->memctl_interleaving_mode =
1098                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1099                         0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
1100                 popts->memctl_interleaving =
1101                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1102                         0 : 1;
1103         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1104                                         "ctlr_intlv",
1105                                         "page", buf)) {
1106                 popts->memctl_interleaving_mode =
1107                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1108                         0 : FSL_DDR_PAGE_INTERLEAVING;
1109                 popts->memctl_interleaving =
1110                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1111                         0 : 1;
1112         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1113                                         "ctlr_intlv",
1114                                         "bank", buf)) {
1115                 popts->memctl_interleaving_mode =
1116                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1117                         0 : FSL_DDR_BANK_INTERLEAVING;
1118                 popts->memctl_interleaving =
1119                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1120                         0 : 1;
1121         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1122                                         "ctlr_intlv",
1123                                         "superbank", buf)) {
1124                 popts->memctl_interleaving_mode =
1125                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1126                         0 : FSL_DDR_SUPERBANK_INTERLEAVING;
1127                 popts->memctl_interleaving =
1128                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1129                         0 : 1;
1130 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
1131         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1132                                         "ctlr_intlv",
1133                                         "3way_1KB", buf)) {
1134                 popts->memctl_interleaving_mode =
1135                         FSL_DDR_3WAY_1KB_INTERLEAVING;
1136         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1137                                         "ctlr_intlv",
1138                                         "3way_4KB", buf)) {
1139                 popts->memctl_interleaving_mode =
1140                         FSL_DDR_3WAY_4KB_INTERLEAVING;
1141         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1142                                         "ctlr_intlv",
1143                                         "3way_8KB", buf)) {
1144                 popts->memctl_interleaving_mode =
1145                         FSL_DDR_3WAY_8KB_INTERLEAVING;
1146 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
1147         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1148                                         "ctlr_intlv",
1149                                         "4way_1KB", buf)) {
1150                 popts->memctl_interleaving_mode =
1151                         FSL_DDR_4WAY_1KB_INTERLEAVING;
1152         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1153                                         "ctlr_intlv",
1154                                         "4way_4KB", buf)) {
1155                 popts->memctl_interleaving_mode =
1156                         FSL_DDR_4WAY_4KB_INTERLEAVING;
1157         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1158                                         "ctlr_intlv",
1159                                         "4way_8KB", buf)) {
1160                 popts->memctl_interleaving_mode =
1161                         FSL_DDR_4WAY_8KB_INTERLEAVING;
1162 #endif
1163         } else {
1164                 popts->memctl_interleaving = 0;
1165                 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
1166         }
1167 #endif  /* CONFIG_SYS_FSL_DDR_INTLV_256B */
1168 done:
1169 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
1170         if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
1171                 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
1172                 /* test null first. if CONFIG_HWCONFIG is not defined,
1173                  * hwconfig_subarg_cmp_f returns non-zero */
1174                 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1175                                             "null", buf))
1176                         debug("bank interleaving disabled.\n");
1177                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1178                                                  "cs0_cs1", buf))
1179                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
1180                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1181                                                  "cs2_cs3", buf))
1182                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
1183                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1184                                                  "cs0_cs1_and_cs2_cs3", buf))
1185                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
1186                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1187                                                  "cs0_cs1_cs2_cs3", buf))
1188                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
1189                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1190                                                 "auto", buf))
1191                         popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
1192                 else
1193                         printf("hwconfig has unrecognized parameter for bank_intlv.\n");
1194                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1195                 case FSL_DDR_CS0_CS1_CS2_CS3:
1196 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1197                         if (pdimm[0].n_ranks < 4) {
1198                                 popts->ba_intlv_ctl = 0;
1199                                 printf("Not enough bank(chip-select) for "
1200                                         "CS0+CS1+CS2+CS3 on controller %d, "
1201                                         "interleaving disabled!\n", ctrl_num);
1202                         }
1203 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1204 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
1205                         if (pdimm[0].n_ranks == 4)
1206                                 break;
1207 #endif
1208                         if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
1209                                 popts->ba_intlv_ctl = 0;
1210                                 printf("Not enough bank(chip-select) for "
1211                                         "CS0+CS1+CS2+CS3 on controller %d, "
1212                                         "interleaving disabled!\n", ctrl_num);
1213                         }
1214                         if (pdimm[0].capacity != pdimm[1].capacity) {
1215                                 popts->ba_intlv_ctl = 0;
1216                                 printf("Not identical DIMM size for "
1217                                         "CS0+CS1+CS2+CS3 on controller %d, "
1218                                         "interleaving disabled!\n", ctrl_num);
1219                         }
1220 #endif
1221                         break;
1222                 case FSL_DDR_CS0_CS1:
1223                         if (pdimm[0].n_ranks < 2) {
1224                                 popts->ba_intlv_ctl = 0;
1225                                 printf("Not enough bank(chip-select) for "
1226                                         "CS0+CS1 on controller %d, "
1227                                         "interleaving disabled!\n", ctrl_num);
1228                         }
1229                         break;
1230                 case FSL_DDR_CS2_CS3:
1231 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1232                         if (pdimm[0].n_ranks < 4) {
1233                                 popts->ba_intlv_ctl = 0;
1234                                 printf("Not enough bank(chip-select) for CS2+CS3 "
1235                                         "on controller %d, interleaving disabled!\n", ctrl_num);
1236                         }
1237 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1238                         if (pdimm[1].n_ranks < 2) {
1239                                 popts->ba_intlv_ctl = 0;
1240                                 printf("Not enough bank(chip-select) for CS2+CS3 "
1241                                         "on controller %d, interleaving disabled!\n", ctrl_num);
1242                         }
1243 #endif
1244                         break;
1245                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1246 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1247                         if (pdimm[0].n_ranks < 4) {
1248                                 popts->ba_intlv_ctl = 0;
1249                                 printf("Not enough bank(CS) for CS0+CS1 and "
1250                                         "CS2+CS3 on controller %d, "
1251                                         "interleaving disabled!\n", ctrl_num);
1252                         }
1253 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1254                         if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
1255                                 popts->ba_intlv_ctl = 0;
1256                                 printf("Not enough bank(CS) for CS0+CS1 and "
1257                                         "CS2+CS3 on controller %d, "
1258                                         "interleaving disabled!\n", ctrl_num);
1259                         }
1260 #endif
1261                         break;
1262                 default:
1263                         popts->ba_intlv_ctl = 0;
1264                         break;
1265                 }
1266         }
1267
1268         if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
1269                 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
1270                         popts->addr_hash = 0;
1271                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1272                                                "true", buf))
1273                         popts->addr_hash = 1;
1274         }
1275
1276         if (pdimm[0].n_ranks == 4)
1277                 popts->quad_rank_present = 1;
1278
1279         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
1280         if (popts->registered_dimm_en) {
1281                 popts->rcw_override = 1;
1282                 popts->rcw_1 = 0x000a5a00;
1283                 if (ddr_freq <= 800)
1284                         popts->rcw_2 = 0x00000000;
1285                 else if (ddr_freq <= 1066)
1286                         popts->rcw_2 = 0x00100000;
1287                 else if (ddr_freq <= 1333)
1288                         popts->rcw_2 = 0x00200000;
1289                 else
1290                         popts->rcw_2 = 0x00300000;
1291         }
1292
1293         fsl_ddr_board_options(popts, pdimm, ctrl_num);
1294
1295         return 0;
1296 }
1297
1298 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1299 {
1300         int i, j, k, check_n_ranks, intlv_invalid = 0;
1301         unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1302         unsigned long long check_rank_density;
1303         struct dimm_params_s *dimm;
1304         int first_ctrl = pinfo->first_ctrl;
1305         int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
1306
1307         /*
1308          * Check if all controllers are configured for memory
1309          * controller interleaving. Identical dimms are recommended. At least
1310          * the size, row and col address should be checked.
1311          */
1312         j = 0;
1313         check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
1314         check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
1315         check_n_row_addr =  pinfo->dimm_params[first_ctrl][0].n_row_addr;
1316         check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
1317         check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
1318         for (i = first_ctrl; i <= last_ctrl; i++) {
1319                 dimm = &pinfo->dimm_params[i][0];
1320                 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1321                         continue;
1322                 } else if (((check_rank_density != dimm->rank_density) ||
1323                      (check_n_ranks != dimm->n_ranks) ||
1324                      (check_n_row_addr != dimm->n_row_addr) ||
1325                      (check_n_col_addr != dimm->n_col_addr) ||
1326                      (check_intlv !=
1327                         pinfo->memctl_opts[i].memctl_interleaving_mode))){
1328                         intlv_invalid = 1;
1329                         break;
1330                 } else {
1331                         j++;
1332                 }
1333
1334         }
1335         if (intlv_invalid) {
1336                 for (i = first_ctrl; i <= last_ctrl; i++)
1337                         pinfo->memctl_opts[i].memctl_interleaving = 0;
1338                 printf("Not all DIMMs are identical. "
1339                         "Memory controller interleaving disabled.\n");
1340         } else {
1341                 switch (check_intlv) {
1342                 case FSL_DDR_256B_INTERLEAVING:
1343                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1344                 case FSL_DDR_PAGE_INTERLEAVING:
1345                 case FSL_DDR_BANK_INTERLEAVING:
1346                 case FSL_DDR_SUPERBANK_INTERLEAVING:
1347 #if (3 == CONFIG_NUM_DDR_CONTROLLERS)
1348                                 k = 2;
1349 #else
1350                                 k = CONFIG_NUM_DDR_CONTROLLERS;
1351 #endif
1352                         break;
1353                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1354                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1355                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1356                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1357                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1358                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1359                 default:
1360                         k = CONFIG_NUM_DDR_CONTROLLERS;
1361                         break;
1362                 }
1363                 debug("%d of %d controllers are interleaving.\n", j, k);
1364                 if (j && (j != k)) {
1365                         for (i = first_ctrl; i <= last_ctrl; i++)
1366                                 pinfo->memctl_opts[i].memctl_interleaving = 0;
1367                         if ((last_ctrl - first_ctrl) > 1)
1368                                 puts("Not all controllers have compatible interleaving mode. All disabled.\n");
1369                 }
1370         }
1371         debug("Checking interleaving options completed\n");
1372 }
1373
1374 int fsl_use_spd(void)
1375 {
1376         int use_spd = 0;
1377
1378 #ifdef CONFIG_DDR_SPD
1379         char buffer[HWCONFIG_BUFFER_SIZE];
1380         char *buf = NULL;
1381
1382         /*
1383          * Extract hwconfig from environment since we have not properly setup
1384          * the environment but need it for ddr config params
1385          */
1386         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
1387                 buf = buffer;
1388
1389         /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1390         if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1391                 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1392                         use_spd = 1;
1393                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
1394                                                "fixed", buf))
1395                         use_spd = 0;
1396                 else
1397                         use_spd = 1;
1398         } else
1399                 use_spd = 1;
1400 #endif
1401
1402         return use_spd;
1403 }