1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
8 #include <asm/fsl_law.h>
13 #include <fsl_immap.h>
15 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
17 #include <asm/arch/clock.h>
20 /* To avoid 64-bit full-divides, we factor this here */
21 #define ULL_2E12 2000000000000ULL
22 #define UL_5POW12 244140625UL
23 #define UL_2POW13 (1UL << 13)
25 #define ULL_8FS 0xFFFFFFFFULL
27 u32 fsl_ddr_get_version(unsigned int ctrl_num)
29 struct ccsr_ddr __iomem *ddr;
30 u32 ver_major_minor_errata;
34 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
36 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
38 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
41 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
43 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
46 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
48 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
52 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
55 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
56 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
58 return ver_major_minor_errata;
62 * Round up mclk_ps to nearest 1 ps in memory controller code
63 * if the error is 0.5ps or more.
65 * If an imprecise data rate is too high due to rounding error
66 * propagation, compute a suitably rounded mclk_ps to compute
67 * a working memory controller configuration.
69 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
71 unsigned int data_rate = get_ddr_freq(ctrl_num);
74 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
75 unsigned long long rem, mclk_ps = ULL_2E12;
77 /* Now perform the big divide, the result fits in 32-bits */
78 rem = do_div(mclk_ps, data_rate);
79 result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
84 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
85 unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
87 unsigned long long clks, clks_rem;
88 unsigned long data_rate = get_ddr_freq(ctrl_num);
90 /* Short circuit for zero picos */
94 /* First multiply the time by the data rate (32x32 => 64) */
95 clks = picos * (unsigned long long)data_rate;
97 * Now divide by 5^12 and track the 32-bit remainder, then divide
98 * by 2*(2^12) using shifts (and updating the remainder).
100 clks_rem = do_div(clks, UL_5POW12);
101 clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
104 /* If we had a remainder greater than the 1ps error, then round up */
105 if (clks_rem > data_rate)
108 /* Clamp to the maximum representable value */
111 return (unsigned int) clks;
114 unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
116 return get_memory_clk_period_ps(ctrl_num) * mclk;
121 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
122 unsigned int law_memctl,
123 unsigned int ctrl_num)
125 unsigned long long base = memctl_common_params->base_address;
126 unsigned long long size = memctl_common_params->total_mem;
129 * If no DIMMs on this controller, do not proceed any further.
131 if (!memctl_common_params->ndimms_present) {
135 #if !defined(CONFIG_PHYS_64BIT)
136 if (base >= CONFIG_MAX_MEM_MAPPED)
138 if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
139 size = CONFIG_MAX_MEM_MAPPED - base;
141 if (set_ddr_laws(base, size, law_memctl) < 0) {
142 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
146 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
147 base, size, law_memctl);
150 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
151 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
152 unsigned int memctl_interleaved,
153 unsigned int ctrl_num);
156 void fsl_ddr_set_intl3r(const unsigned int granule_size)
159 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
160 *mcintl3r = 0x80000000 | (granule_size & 0x1f);
161 debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
165 u32 fsl_ddr_get_intl3r(void)
169 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
175 void print_ddr_info(unsigned int start_ctrl)
177 struct ccsr_ddr __iomem *ddr =
178 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
180 #if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
181 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
183 #if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
184 uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
186 uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
189 #if CONFIG_SYS_NUM_DDR_CTLRS >= 2
190 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
192 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
193 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
196 #if CONFIG_SYS_NUM_DDR_CTLRS >= 3
197 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
199 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
200 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
204 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
205 puts(" (DDR not enabled)\n");
210 switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
211 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
212 case SDRAM_TYPE_DDR1:
215 case SDRAM_TYPE_DDR2:
218 case SDRAM_TYPE_DDR3:
221 case SDRAM_TYPE_DDR4:
229 if (sdram_cfg & SDRAM_CFG_32_BE)
231 else if (sdram_cfg & SDRAM_CFG_16_BE)
236 /* Calculate CAS latency based on timing cfg values */
237 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
238 if (fsl_ddr_get_version(0) <= 0x40400)
242 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
243 printf(", CL=%d", cas_lat >> 1);
247 if (sdram_cfg & SDRAM_CFG_ECC_EN)
252 #if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
254 if (*mcintl3r & 0x80000000) {
256 puts(" DDR Controller Interleaving Mode: ");
257 switch (*mcintl3r & 0x1f) {
258 case FSL_DDR_3WAY_1KB_INTERLEAVING:
261 case FSL_DDR_3WAY_4KB_INTERLEAVING:
264 case FSL_DDR_3WAY_8KB_INTERLEAVING:
268 puts("3-way UNKNOWN");
274 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
275 if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
277 puts(" DDR Controller Interleaving Mode: ");
279 switch ((cs0_config >> 24) & 0xf) {
280 case FSL_DDR_256B_INTERLEAVING:
283 case FSL_DDR_CACHE_LINE_INTERLEAVING:
286 case FSL_DDR_PAGE_INTERLEAVING:
289 case FSL_DDR_BANK_INTERLEAVING:
292 case FSL_DDR_SUPERBANK_INTERLEAVING:
302 if ((sdram_cfg >> 8) & 0x7f) {
304 puts(" DDR Chip-Select Interleaving Mode: ");
305 switch(sdram_cfg >> 8 & 0x7f) {
306 case FSL_DDR_CS0_CS1_CS2_CS3:
307 puts("CS0+CS1+CS2+CS3");
309 case FSL_DDR_CS0_CS1:
312 case FSL_DDR_CS2_CS3:
315 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
316 puts("CS0+CS1 and CS2+CS3");
325 void __weak detail_board_ddr_info(void)
330 void board_add_ram_info(int use_default)
332 detail_board_ddr_info();
335 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
336 #define DDRC_DEBUG20_INIT_DONE 0x80000000
337 #define DDRC_DEBUG2_RF 0x00000040
338 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
339 unsigned int last_ctrl)
343 u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
344 u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
345 struct ccsr_ddr __iomem *ddr;
347 for (i = first_ctrl; i <= last_ctrl; i++) {
350 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
352 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
354 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
357 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
359 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
362 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
364 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
368 printf("%s unexpected ctrl = %u\n", __func__, i);
371 ddrc_debug20 = ddr_in32(&ddr->debug[19]);
372 ddrc_debug2_p[i] = &ddr->debug[1];
373 while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
374 /* keep polling until DDRC init is done */
376 ddrc_debug20 = ddr_in32(&ddr->debug[19]);
378 ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
382 * This is put together to make sure the refresh reqeusts are sent
383 * closely to each other.
385 for (i = first_ctrl; i <= last_ctrl; i++)
386 ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
388 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
390 void remove_unused_controllers(fsl_ddr_info_t *info)
392 #ifdef CONFIG_SYS_FSL_HAS_CCN504
395 void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
396 bool ddr0_used = false;
397 bool ddr1_used = false;
399 for (i = 0; i < 8; i++) {
400 nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
401 if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
403 } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
406 printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
409 hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
411 if (!ddr0_used && !ddr1_used) {
412 printf("Invalid configuration in HN-F SAM control\n");
416 if (!ddr0_used && info->first_ctrl == 0) {
417 info->first_ctrl = 1;
419 debug("First DDR controller disabled\n");
423 if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
425 debug("Second DDR controller disabled\n");