1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
6 #ifndef _DDR3_HWS_HW_TRAINING_DEF_H
7 #define _DDR3_HWS_HW_TRAINING_DEF_H
9 #define SAR_DDR3_FREQ_MASK 0xfe00000
10 #define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | \
15 #define MIN_DIMM_ADDR 0x50
16 #define FAR_END_DIMM_ADDR 0x50
17 #define MAX_DIMM_ADDR 0x60
19 #define SDRAM_CS_SIZE 0xfffffff
20 #define SDRAM_CS_BASE 0x0
21 #define SDRAM_DIMM_SIZE 0x80000000
23 #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100))
24 #define CPU_MRVL_ID_OFFSET 0x10
25 #define SAR1_CPU_CORE_MASK 0x38000000
26 #define SAR1_CPU_CORE_OFFSET 27
28 #define NEW_FABRIC_TWSI_ADDR 0x4e
30 #define BUS_WIDTH_ECC_TWSI_ADDR 0x4e
32 #define BUS_WIDTH_ECC_TWSI_ADDR 0x4f
34 #define MV_MAX_DDR3_STATIC_SIZE 50
35 #define MV_DDR3_MODES_NUMBER 30
37 #define RESUME_RL_PATTERNS_ADDR 0xfe0000
38 #define RESUME_RL_PATTERNS_SIZE 0x100
39 #define RESUME_TRAINING_VALUES_ADDR (RESUME_RL_PATTERNS_ADDR + \
40 RESUME_RL_PATTERNS_SIZE)
41 #define RESUME_TRAINING_VALUES_MAX 0xcd0
42 #define BOOT_INFO_ADDR (RESUME_RL_PATTERNS_ADDR + 0x1000)
43 #define CHECKSUM_RESULT_ADDR (BOOT_INFO_ADDR + 0x1000)
44 #define NUM_OF_REGISTER_ADDR (CHECKSUM_RESULT_ADDR + 4)
45 #define SUSPEND_MAGIC_WORD 0xdeadb002
46 #define REGISTER_LIST_END 0xffffffff
49 #define INTER_REGS_BASE SOC_REGS_PHY_BASE
52 #define REG_SDRAM_CONFIG_ADDR 0x1400
53 #define REG_SDRAM_CONFIG_MASK 0x9fffffff
54 #define REG_SDRAM_CONFIG_RFRS_MASK 0x3fff
55 #define REG_SDRAM_CONFIG_WIDTH_OFFS 15
56 #define REG_SDRAM_CONFIG_REGDIMM_OFFS 17
57 #define REG_SDRAM_CONFIG_ECC_OFFS 18
58 #define REG_SDRAM_CONFIG_IERR_OFFS 19
59 #define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS 28
60 #define REG_SDRAM_CONFIG_RSTRD_OFFS 30
62 #define REG_SDRAM_PINS_MUX 0x19d4
64 #define REG_DUNIT_CTRL_LOW_ADDR 0x1404
65 #define REG_DUNIT_CTRL_LOW_2T_OFFS 3
66 #define REG_DUNIT_CTRL_LOW_2T_MASK 0x3
67 #define REG_DUNIT_CTRL_LOW_DPDE_OFFS 14
69 #define REG_SDRAM_TIMING_LOW_ADDR 0x1408
70 #define REG_SDRAM_TIMING_HIGH_ADDR 0x140c
71 #define REG_SDRAM_TIMING_H_R2R_OFFS 7
72 #define REG_SDRAM_TIMING_H_R2R_MASK 0x3
73 #define REG_SDRAM_TIMING_H_R2W_W2R_OFFS 9
74 #define REG_SDRAM_TIMING_H_R2W_W2R_MASK 0x3
75 #define REG_SDRAM_TIMING_H_W2W_OFFS 11
76 #define REG_SDRAM_TIMING_H_W2W_MASK 0x1f
77 #define REG_SDRAM_TIMING_H_R2R_H_OFFS 19
78 #define REG_SDRAM_TIMING_H_R2R_H_MASK 0x7
79 #define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS 22
80 #define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK 0x7
82 #define REG_SDRAM_ADDRESS_CTRL_ADDR 0x1410
83 #define REG_SDRAM_ADDRESS_SIZE_OFFS 2
84 #define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS 18
85 #define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS 4
87 #define REG_SDRAM_OPEN_PAGES_ADDR 0x1414
88 #define REG_SDRAM_OPERATION_CS_OFFS 8
90 #define REG_SDRAM_OPERATION_ADDR 0x1418
91 #define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS 24
92 #define REG_SDRAM_OPERATION_CWA_DATA_OFFS 20
93 #define REG_SDRAM_OPERATION_CWA_DATA_MASK 0xf
94 #define REG_SDRAM_OPERATION_CWA_RC_OFFS 16
95 #define REG_SDRAM_OPERATION_CWA_RC_MASK 0xf
96 #define REG_SDRAM_OPERATION_CMD_MR0 0xf03
97 #define REG_SDRAM_OPERATION_CMD_MR1 0xf04
98 #define REG_SDRAM_OPERATION_CMD_MR2 0xf08
99 #define REG_SDRAM_OPERATION_CMD_MR3 0xf09
100 #define REG_SDRAM_OPERATION_CMD_RFRS 0xf02
101 #define REG_SDRAM_OPERATION_CMD_CWA 0xf0e
102 #define REG_SDRAM_OPERATION_CMD_RFRS_DONE 0xf
103 #define REG_SDRAM_OPERATION_CMD_MASK 0xf
104 #define REG_SDRAM_OPERATION_CS_OFFS 8
106 #define REG_OUDDR3_TIMING_ADDR 0x142c
108 #define REG_SDRAM_MODE_ADDR 0x141c
110 #define REG_SDRAM_EXT_MODE_ADDR 0x1420
112 #define REG_DDR_CONT_HIGH_ADDR 0x1424
114 #define REG_ODT_TIME_LOW_ADDR 0x1428
115 #define REG_ODT_ON_CTL_RD_OFFS 12
116 #define REG_ODT_OFF_CTL_RD_OFFS 16
117 #define REG_SDRAM_ERROR_ADDR 0x1454
118 #define REG_SDRAM_AUTO_PWR_SAVE_ADDR 0x1474
119 #define REG_ODT_TIME_HIGH_ADDR 0x147c
121 #define REG_SDRAM_INIT_CTRL_ADDR 0x1480
122 #define REG_SDRAM_INIT_CTRL_OFFS 0
123 #define REG_SDRAM_INIT_CKE_ASSERT_OFFS 2
124 #define REG_SDRAM_INIT_RESET_DEASSERT_OFFS 3
125 #define REG_SDRAM_INIT_RESET_MASK_OFFS 1
127 #define REG_SDRAM_ODT_CTRL_LOW_ADDR 0x1494
129 #define REG_SDRAM_ODT_CTRL_HIGH_ADDR 0x1498
130 #define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0x0
131 #define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA 0x3
133 #define REG_DUNIT_ODT_CTRL_ADDR 0x149c
134 #define REG_DUNIT_ODT_CTRL_OVRD_OFFS 8
135 #define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS 9
137 #define REG_DRAM_FIFO_CTRL_ADDR 0x14a0
139 #define REG_DRAM_AXI_CTRL_ADDR 0x14a8
140 #define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS 0
142 #define REG_METAL_MASK_ADDR 0x14b0
143 #define REG_METAL_MASK_MASK 0xdfffffff
144 #define REG_METAL_MASK_RETRY_OFFS 0
146 #define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR 0x14c0
148 #define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR 0x14c4
149 #define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR 0x14c8
150 #define REG_DRAM_MAIN_PADS_CAL_ADDR 0x14cc
152 #define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR 0x17c8
154 #define REG_CS_SIZE_SCRATCH_ADDR 0x1504
155 #define REG_DYNAMIC_POWER_SAVE_ADDR 0x1520
156 #define REG_DDR_IO_ADDR 0x1524
157 #define REG_DDR_IO_CLK_RATIO_OFFS 15
159 #define REG_DFS_ADDR 0x1528
160 #define REG_DFS_DLLNEXTSTATE_OFFS 0
161 #define REG_DFS_BLOCK_OFFS 1
162 #define REG_DFS_SR_OFFS 2
163 #define REG_DFS_ATSR_OFFS 3
164 #define REG_DFS_RECONF_OFFS 4
165 #define REG_DFS_CL_NEXT_STATE_OFFS 8
166 #define REG_DFS_CL_NEXT_STATE_MASK 0xf
167 #define REG_DFS_CWL_NEXT_STATE_OFFS 12
168 #define REG_DFS_CWL_NEXT_STATE_MASK 0x7
170 #define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
171 #define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1f
172 #define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8
174 #define REG_READ_DATA_READY_DELAYS_ADDR 0x153c
175 #define REG_READ_DATA_READY_DELAYS_MASK 0x1f
176 #define REG_READ_DATA_READY_DELAYS_OFFS 8
178 #define START_BURST_IN_ADDR 1
180 #define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488
181 #define REG_DRAM_TRAINING_ADDR 0x15b0
182 #define REG_DRAM_TRAINING_LOW_FREQ_OFFS 0
183 #define REG_DRAM_TRAINING_PATTERNS_OFFS 4
184 #define REG_DRAM_TRAINING_MED_FREQ_OFFS 2
185 #define REG_DRAM_TRAINING_WL_OFFS 3
186 #define REG_DRAM_TRAINING_RL_OFFS 6
187 #define REG_DRAM_TRAINING_DQS_RX_OFFS 15
188 #define REG_DRAM_TRAINING_DQS_TX_OFFS 16
189 #define REG_DRAM_TRAINING_CS_OFFS 20
190 #define REG_DRAM_TRAINING_RETEST_OFFS 24
191 #define REG_DRAM_TRAINING_DFS_FREQ_OFFS 27
192 #define REG_DRAM_TRAINING_DFS_REQ_OFFS 29
193 #define REG_DRAM_TRAINING_ERROR_OFFS 30
194 #define REG_DRAM_TRAINING_AUTO_OFFS 31
195 #define REG_DRAM_TRAINING_RETEST_PAR 0x3
196 #define REG_DRAM_TRAINING_RETEST_MASK 0xf8ffffff
197 #define REG_DRAM_TRAINING_CS_MASK 0xff0fffff
198 #define REG_DRAM_TRAINING_PATTERNS_MASK 0xff0f0000
200 #define REG_DRAM_TRAINING_1_ADDR 0x15b4
201 #define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS 16
203 #define REG_DRAM_TRAINING_2_ADDR 0x15b8
204 #define REG_DRAM_TRAINING_2_OVERRUN_OFFS 17
205 #define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4
206 #define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3
207 #define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2
208 #define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1
209 #define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0
211 #define REG_DRAM_TRAINING_PATTERN_BASE_ADDR 0x15bc
212 #define REG_DRAM_TRAINING_PATTERN_BASE_OFFS 3
214 #define REG_TRAINING_DEBUG_2_ADDR 0x15c4
215 #define REG_TRAINING_DEBUG_2_OFFS 16
216 #define REG_TRAINING_DEBUG_2_MASK 0x3
218 #define REG_TRAINING_DEBUG_3_ADDR 0x15c8
219 #define REG_TRAINING_DEBUG_3_OFFS 3
220 #define REG_TRAINING_DEBUG_3_MASK 0x7
222 #define MR_CS_ADDR_OFFS 4
224 #define REG_DDR3_MR0_ADDR 0x15d0
225 #define REG_DDR3_MR0_CS_ADDR 0x1870
226 #define REG_DDR3_MR0_CL_MASK 0x74
227 #define REG_DDR3_MR0_CL_OFFS 2
228 #define REG_DDR3_MR0_CL_HIGH_OFFS 3
231 #define REG_DDR3_MR1_ADDR 0x15d4
232 #define REG_DDR3_MR1_CS_ADDR 0x1874
233 #define REG_DDR3_MR1_RTT_MASK 0xfffffdbb
234 #define REG_DDR3_MR1_DLL_ENA_OFFS 0
235 #define REG_DDR3_MR1_RTT_DISABLED 0x0
236 #define REG_DDR3_MR1_RTT_RZQ2 0x40
237 #define REG_DDR3_MR1_RTT_RZQ4 0x2
238 #define REG_DDR3_MR1_RTT_RZQ6 0x42
239 #define REG_DDR3_MR1_RTT_RZQ8 0x202
240 #define REG_DDR3_MR1_RTT_RZQ12 0x4
241 /* WL-disabled, OB-enabled */
242 #define REG_DDR3_MR1_OUTBUF_WL_MASK 0xffffef7f
243 /* Output Buffer Disabled */
244 #define REG_DDR3_MR1_OUTBUF_DIS_OFFS 12
245 #define REG_DDR3_MR1_WL_ENA_OFFS 7
246 #define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */
247 #define REG_DDR3_MR1_ODT_MASK 0xfffffdbb
249 #define REG_DDR3_MR2_ADDR 0x15d8
250 #define REG_DDR3_MR2_CS_ADDR 0x1878
251 #define REG_DDR3_MR2_CWL_OFFS 3
252 #define REG_DDR3_MR2_CWL_MASK 0x7
253 #define REG_DDR3_MR2_ODT_MASK 0xfffff9ff
254 #define REG_DDR3_MR3_ADDR 0x15dc
255 #define REG_DDR3_MR3_CS_ADDR 0x187c
257 #define REG_DDR3_RANK_CTRL_ADDR 0x15e0
258 #define REG_DDR3_RANK_CTRL_CS_ENA_MASK 0xf
259 #define REG_DDR3_RANK_CTRL_MIRROR_OFFS 4
261 #define REG_ZQC_CONF_ADDR 0x15e4
263 #define REG_DRAM_PHY_CONFIG_ADDR 0x15ec
264 #define REG_DRAM_PHY_CONFIG_MASK 0x3fffffff
266 #define REG_ODPG_CNTRL_ADDR 0x1600
267 #define REG_ODPG_CNTRL_OFFS 21
269 #define REG_PHY_LOCK_MASK_ADDR 0x1670
270 #define REG_PHY_LOCK_MASK_MASK 0xfffff000
272 #define REG_PHY_LOCK_STATUS_ADDR 0x1674
273 #define REG_PHY_LOCK_STATUS_LOCK_OFFS 9
274 #define REG_PHY_LOCK_STATUS_LOCK_MASK 0xfff
275 #define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK 0x7ff
277 #define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16a0
278 #define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xc0000000
279 #define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD 0x80000000
280 #define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE 0x80000000
281 #define REG_PHY_BC_OFFS 27
282 #define REG_PHY_CNTRL_OFFS 26
283 #define REG_PHY_CS_OFFS 16
284 #define REG_PHY_DQS_REF_DLY_OFFS 10
285 #define REG_PHY_PHASE_OFFS 8
286 #define REG_PHY_PUP_OFFS 22
288 #define REG_TRAINING_WL_ADDR 0x16ac
289 #define REG_TRAINING_WL_CS_MASK 0xfffffffc
290 #define REG_TRAINING_WL_UPD_OFFS 2
291 #define REG_TRAINING_WL_CS_DONE_OFFS 3
292 #define REG_TRAINING_WL_RATIO_MASK 0xffffff0f
293 #define REG_TRAINING_WL_1TO1 0x50
294 #define REG_TRAINING_WL_2TO1 0x10
295 #define REG_TRAINING_WL_DELAYEXP_MASK 0x20000000
296 #define REG_TRAINING_WL_RESULTS_MASK 0x000001ff
297 #define REG_TRAINING_WL_RESULTS_OFFS 20
299 #define REG_REGISTERED_DRAM_CTRL_ADDR 0x16d0
300 #define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS 15
301 #define REG_REGISTERED_DRAM_CTRL_PARITY_MASK 0x3f
304 #define REG_STATIC_DRAM_DLB_CONTROL 0x1700
305 #define DLB_BUS_OPTIMIZATION_WEIGHTS_REG 0x1704
306 #define DLB_AGING_REGISTER 0x1708
307 #define DLB_EVICTION_CONTROL_REG 0x170c
308 #define DLB_EVICTION_TIMERS_REGISTER_REG 0x1710
309 #define DLB_USER_COMMAND_REG 0x1714
310 #define DLB_BUS_WEIGHTS_DIFF_CS 0x1770
311 #define DLB_BUS_WEIGHTS_DIFF_BG 0x1774
312 #define DLB_BUS_WEIGHTS_SAME_BG 0x1778
313 #define DLB_BUS_WEIGHTS_RD_WR 0x177c
314 #define DLB_BUS_WEIGHTS_ATTR_SYS_PRIO 0x1780
315 #define DLB_MAIN_QUEUE_MAP 0x1784
316 #define DLB_LINE_SPLIT 0x1788
318 #define DLB_ENABLE 0x1
319 #define DLB_WRITE_COALESING (0x1 << 2)
320 #define DLB_AXI_PREFETCH_EN (0x1 << 3)
321 #define DLB_MBUS_PREFETCH_EN (0x1 << 4)
322 #define PREFETCH_N_LN_SZ_TR (0x1 << 6)
323 #define DLB_INTERJECTION_ENABLE (0x1 << 3)
326 #define REG_BOOTROM_ROUTINE_ADDR 0x182d0
327 #define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12
329 #define REG_DRAM_INIT_CTRL_STATUS_ADDR 0x18488
330 #define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS 16
331 #define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO 0x000200ff
332 #define REG_DRAM_INIT_CTRL_STATUS_2_ADDR 0x1488
334 #define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700
336 #define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704
337 #define REG_CPU_DIV_CLK_CTRL_2_ADDR 0x18708
339 #define REG_CPU_DIV_CLK_CTRL_3_ADDR 0x1870c
340 #define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK 0xffffc0ff
341 #define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS 8
343 #define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710
345 #define REG_CPU_DIV_CLK_STATUS_0_ADDR 0x18718
346 #define REG_CPU_DIV_CLK_ALL_STABLE_OFFS 8
348 #define REG_CPU_PLL_CTRL_0_ADDR 0x1871c
349 #define REG_CPU_PLL_STATUS_0_ADDR 0x18724
350 #define REG_CORE_DIV_CLK_CTRL_ADDR 0x18740
351 #define REG_CORE_DIV_CLK_STATUS_ADDR 0x18744
352 #define REG_DDRPHY_APLL_CTRL_ADDR 0x18780
354 #define REG_DDRPHY_APLL_CTRL_2_ADDR 0x18784
355 #define REG_SFABRIC_CLK_CTRL_ADDR 0x20858
356 #define REG_SFABRIC_CLK_CTRL_SMPL_OFFS 8
359 #define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
360 #define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
361 #define REG_XBAR_WIN_4_BASE_ADDR 0x20044
362 #define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
363 #define REG_FASTPATH_WIN_0_CTRL_ADDR 0x20184
364 #define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
367 #define REG_CDI_CONFIG_ADDR 0x20220
368 #define REG_SRAM_WINDOW_0_ADDR 0x20240
369 #define REG_SRAM_WINDOW_0_ENA_OFFS 0
370 #define REG_SRAM_WINDOW_1_ADDR 0x20244
371 #define REG_SRAM_L2_ENA_ADDR 0x8500
372 #define REG_SRAM_CLEAN_BY_WAY_ADDR 0x87bc
375 #define REG_TIMERS_CTRL_ADDR 0x20300
376 #define REG_TIMERS_EVENTS_ADDR 0x20304
377 #define REG_TIMER0_VALUE_ADDR 0x20314
378 #define REG_TIMER1_VALUE_ADDR 0x2031c
379 #define REG_TIMER0_ENABLE_MASK 0x1
381 #define MV_BOARD_REFCLK_25MHZ 25000000
382 #define CNTMR_RELOAD_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x10 + (tmr * 8))
383 #define CNTMR_VAL_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x14 + (tmr * 8))
384 #define CNTMR_CTRL_REG(tmr) (REG_TIMERS_CTRL_ADDR)
385 #define CTCR_ARM_TIMER_EN_OFFS(timer) (timer * 2)
386 #define CTCR_ARM_TIMER_EN_MASK(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
387 #define CTCR_ARM_TIMER_EN(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
389 #define CTCR_ARM_TIMER_AUTO_OFFS(timer) (1 + (timer * 2))
390 #define CTCR_ARM_TIMER_AUTO_MASK(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
391 #define CTCR_ARM_TIMER_AUTO_EN(timer) (1 << CTCR_ARM_TIMER_AUTO_OFFS(timer))
394 #define REG_PMU_I_F_CTRL_ADDR 0x1c090
395 #define REG_PMU_DUNIT_BLK_OFFS 16
396 #define REG_PMU_DUNIT_RFRS_OFFS 20
397 #define REG_PMU_DUNIT_ACK_OFFS 24
400 #define MBUS_UNITS_PRIORITY_CONTROL_REG (MBUS_REGS_OFFSET + 0x420)
401 #define FABRIC_UNITS_PRIORITY_CONTROL_REG (MBUS_REGS_OFFSET + 0x424)
402 #define MBUS_UNITS_PREFETCH_CONTROL_REG (MBUS_REGS_OFFSET + 0x428)
403 #define FABRIC_UNITS_PREFETCH_CONTROL_REG (MBUS_REGS_OFFSET + 0x42c)
405 #define REG_PM_STAT_MASK_ADDR 0x2210c
406 #define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS 16
408 #define REG_PM_EVENT_STAT_MASK_ADDR 0x22120
409 #define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS 17
411 #define REG_PM_CTRL_CONFIG_ADDR 0x22104
412 #define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS 18
414 #define REG_FABRIC_LOCAL_IRQ_MASK_ADDR 0x218c4
415 #define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS 18
417 /* Controller revision info */
418 #define PCI_CLASS_CODE_AND_REVISION_ID 0x008
419 #define PCCRIR_REVID_OFFS 0 /* Revision ID */
420 #define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
422 /* Power Management Clock Gating Control Register */
423 #define POWER_MNG_CTRL_REG 0x18220
424 #define PMC_PEXSTOPCLOCK_OFFS(p) ((p) < 8 ? (5 + (p)) : (18 + (p)))
425 #define PMC_PEXSTOPCLOCK_MASK(p) (1 << PMC_PEXSTOPCLOCK_OFFS(p))
426 #define PMC_PEXSTOPCLOCK_EN(p) (1 << PMC_PEXSTOPCLOCK_OFFS(p))
427 #define PMC_PEXSTOPCLOCK_STOP(p) (0 << PMC_PEXSTOPCLOCK_OFFS(p))
430 #define TWSI_DATA_ADDR_MASK 0x7
431 #define TWSI_DATA_ADDR_OFFS 1
439 #define CLK_VCO (2 * CLK_CPU)
442 /* CPU Frequencies: */
443 #define CLK_CPU_1000 0
444 #define CLK_CPU_1066 1
445 #define CLK_CPU_1200 2
446 #define CLK_CPU_1333 3
447 #define CLK_CPU_1500 4
448 #define CLK_CPU_1666 5
449 #define CLK_CPU_1800 6
450 #define CLK_CPU_2000 7
451 #define CLK_CPU_600 8
452 #define CLK_CPU_667 9
453 #define CLK_CPU_800 0xa
455 /* Extra Cpu Frequencies: */
456 #define CLK_CPU_1600 11
457 #define CLK_CPU_2133 12
458 #define CLK_CPU_2200 13
459 #define CLK_CPU_2400 14
461 #endif /* _DDR3_HWS_HW_TRAINING_DEF_H */