git.sur5r.net Git - u-boot/blob - drivers/ddr/marvell/axp/ddr3_init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Marvell International Ltd. and its affiliates
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <spl.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/cpu.h>
  11 #include <asm/arch/soc.h>
  12
  13 #include "ddr3_init.h"
  14
  15 #if defined(MV88F78X60)
  16 #include "ddr3_axp_vars.h"
  17 #elif defined(MV88F67XX)
  18 #include "ddr3_a370_vars.h"
  19 #elif defined(MV88F672X)
  20 #include "ddr3_a375_vars.h"
  21 #endif
  22
  23 #ifdef STATIC_TRAINING
  24 static void ddr3_static_training_init(void);
  25 #endif
  26 #ifdef DUNIT_STATIC
  27 static void ddr3_static_mc_init(void);
  28 #endif
  29 #if defined(DUNIT_STATIC) || defined(STATIC_TRAINING)
  30 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void);
  31 #endif
  32 #if defined(MV88F672X)
  33 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
  34 #endif
  35 u32 mv_board_id_get(void);
  36 extern void ddr3_set_sw_wl_rl_debug(u32);
  37 extern void ddr3_set_pbs(u32);
  38 extern void ddr3_set_log_level(u32 val);
  39
  40 static u32 log_level = DDR3_LOG_LEVEL;
  41
  42 static u32 ddr3_init_main(void);
  43
  44 /*
  45  * Name:     ddr3_set_log_level
  46  * Desc:     This routine initialize the log_level acording to nLogLevel
  47  *           which getting from user
  48  * Args:     nLogLevel
  49  * Notes:
  50  * Returns:  None.
  51  */
  52 void ddr3_set_log_level(u32 val)
  53 {
  54         log_level = val;
  55 }
  56
  57 /*
  58  * Name:     ddr3_get_log_level
  59  * Desc:     This routine returns the log level
  60  * Args:     none
  61  * Notes:
  62  * Returns:  log level.
  63  */
  64 u32 ddr3_get_log_level(void)
  65 {
  66         return log_level;
  67 }
  68
  69 static void debug_print_reg(u32 reg)
  70 {
  71         printf("0x%08x = 0x%08x\n", reg, reg_read(reg));
  72 }
  73
  74 static void print_dunit_setup(void)
  75 {
  76         puts("\n########### LOG LEVEL 1 (D-UNIT SETUP)###########\n");
  77
  78 #ifdef DUNIT_STATIC
  79         puts("\nStatic D-UNIT Setup:\n");
  80 #endif
  81 #ifdef DUNIT_SPD
  82         puts("\nDynamic(using SPD) D-UNIT Setup:\n");
  83 #endif
  84         debug_print_reg(REG_SDRAM_CONFIG_ADDR);
  85         debug_print_reg(REG_DUNIT_CTRL_LOW_ADDR);
  86         debug_print_reg(REG_SDRAM_TIMING_LOW_ADDR);
  87         debug_print_reg(REG_SDRAM_TIMING_HIGH_ADDR);
  88         debug_print_reg(REG_SDRAM_ADDRESS_CTRL_ADDR);
  89         debug_print_reg(REG_SDRAM_OPEN_PAGES_ADDR);
  90         debug_print_reg(REG_SDRAM_OPERATION_ADDR);
  91         debug_print_reg(REG_SDRAM_MODE_ADDR);
  92         debug_print_reg(REG_SDRAM_EXT_MODE_ADDR);
  93         debug_print_reg(REG_DDR_CONT_HIGH_ADDR);
  94         debug_print_reg(REG_ODT_TIME_LOW_ADDR);
  95         debug_print_reg(REG_SDRAM_ERROR_ADDR);
  96         debug_print_reg(REG_SDRAM_AUTO_PWR_SAVE_ADDR);
  97         debug_print_reg(REG_OUDDR3_TIMING_ADDR);
  98         debug_print_reg(REG_ODT_TIME_HIGH_ADDR);
  99         debug_print_reg(REG_SDRAM_ODT_CTRL_LOW_ADDR);
 100         debug_print_reg(REG_SDRAM_ODT_CTRL_HIGH_ADDR);
 101         debug_print_reg(REG_DUNIT_ODT_CTRL_ADDR);
 102 #ifndef MV88F67XX
 103         debug_print_reg(REG_DRAM_FIFO_CTRL_ADDR);
 104         debug_print_reg(REG_DRAM_AXI_CTRL_ADDR);
 105         debug_print_reg(REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR);
 106         debug_print_reg(REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR);
 107         debug_print_reg(REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR);
 108         debug_print_reg(REG_DRAM_MAIN_PADS_CAL_ADDR);
 109         debug_print_reg(REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR);
 110         debug_print_reg(REG_CS_SIZE_SCRATCH_ADDR);
 111         debug_print_reg(REG_DYNAMIC_POWER_SAVE_ADDR);
 112         debug_print_reg(REG_READ_DATA_SAMPLE_DELAYS_ADDR);
 113         debug_print_reg(REG_READ_DATA_READY_DELAYS_ADDR);
 114         debug_print_reg(REG_DDR3_MR0_ADDR);
 115         debug_print_reg(REG_DDR3_MR1_ADDR);
 116         debug_print_reg(REG_DDR3_MR2_ADDR);
 117         debug_print_reg(REG_DDR3_MR3_ADDR);
 118         debug_print_reg(REG_DDR3_RANK_CTRL_ADDR);
 119         debug_print_reg(REG_DRAM_PHY_CONFIG_ADDR);
 120         debug_print_reg(REG_STATIC_DRAM_DLB_CONTROL);
 121         debug_print_reg(DLB_BUS_OPTIMIZATION_WEIGHTS_REG);
 122         debug_print_reg(DLB_AGING_REGISTER);
 123         debug_print_reg(DLB_EVICTION_CONTROL_REG);
 124         debug_print_reg(DLB_EVICTION_TIMERS_REGISTER_REG);
 125 #if defined(MV88F672X)
 126         debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(0));
 127         debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(0));
 128         debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(1));
 129         debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(1));
 130 #else
 131         debug_print_reg(REG_FASTPATH_WIN_0_CTRL_ADDR);
 132 #endif
 133         debug_print_reg(REG_CDI_CONFIG_ADDR);
 134 #endif
 135 }
 136
 137 #if !defined(STATIC_TRAINING)
 138 static void ddr3_restore_and_set_final_windows(u32 *win_backup)
 139 {
 140         u32 ui, reg, cs;
 141         u32 win_ctrl_reg, num_of_win_regs;
 142         u32 cs_ena = ddr3_get_cs_ena_from_reg();
 143
 144 #if defined(MV88F672X)
 145         if (DDR3_FAST_PATH_EN == 0)
 146                 return;
 147 #endif
 148
 149 #if defined(MV88F672X)
 150         win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR;
 151         num_of_win_regs = 8;
 152 #else
 153         win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
 154         num_of_win_regs = 16;
 155 #endif
 156
 157         /* Return XBAR windows 4-7 or 16-19 init configuration */
 158         for (ui = 0; ui < num_of_win_regs; ui++)
 159                 reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]);
 160
 161         DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n");
 162
 163 #if defined(MV88F672X)
 164         /* Set L2 filtering to 1G */
 165         reg_write(0x8c04, 0x40000000);
 166
 167         /* Open fast path windows */
 168         for (cs = 0; cs < MAX_CS; cs++) {
 169                 if (cs_ena & (1 << cs)) {
 170                         /* set fast path window control for the cs */
 171                         reg = 0x1FFFFFE1;
 172                         reg |= (cs << 2);
 173                         reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
 174                         /* Open fast path Window */
 175                         reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg);
 176                         /* set fast path window base address for the cs */
 177                         reg = (((SDRAM_CS_SIZE + 1) * cs) & 0xFFFF0000);
 178                         /* Set base address */
 179                         reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg);
 180                 }
 181         }
 182 #else
 183         reg = 0x1FFFFFE1;
 184         for (cs = 0; cs < MAX_CS; cs++) {
 185                 if (cs_ena & (1 << cs)) {
 186                         reg |= (cs << 2);
 187                         break;
 188                 }
 189         }
 190
 191         /* Open fast path Window to - 0.5G */
 192         reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg);
 193 #endif
 194 }
 195
 196 static void ddr3_save_and_set_training_windows(u32 *win_backup)
 197 {
 198         u32 cs_ena = ddr3_get_cs_ena_from_reg();
 199         u32 reg, tmp_count, cs, ui;
 200         u32 win_ctrl_reg, win_base_reg, win_remap_reg;
 201         u32 num_of_win_regs, win_jump_index;
 202
 203 #if defined(MV88F672X)
 204         /* Disable L2 filtering */
 205         reg_write(0x8c04, 0);
 206
 207         win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR;
 208         win_base_reg = REG_XBAR_WIN_16_BASE_ADDR;
 209         win_remap_reg = REG_XBAR_WIN_16_REMAP_ADDR;
 210         win_jump_index = 0x8;
 211         num_of_win_regs = 8;
 212 #else
 213         win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
 214         win_base_reg = REG_XBAR_WIN_4_BASE_ADDR;
 215         win_remap_reg = REG_XBAR_WIN_4_REMAP_ADDR;
 216         win_jump_index = 0x10;
 217         num_of_win_regs = 16;
 218 #endif
 219
 220         /* Close XBAR Window 19 - Not needed */
 221         /* {0x000200e8}  -   Open Mbus Window - 2G */
 222         reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0);
 223
 224         /* Save XBAR Windows 4-19 init configurations */
 225         for (ui = 0; ui < num_of_win_regs; ui++)
 226                 win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui);
 227
 228         /* Open XBAR Windows 4-7 or 16-19 for other CS */
 229         reg = 0;
 230         tmp_count = 0;
 231         for (cs = 0; cs < MAX_CS; cs++) {
 232                 if (cs_ena & (1 << cs)) {
 233                         switch (cs) {
 234                         case 0:
 235                                 reg = 0x0E00;
 236                                 break;
 237                         case 1:
 238                                 reg = 0x0D00;
 239                                 break;
 240                         case 2:
 241                                 reg = 0x0B00;
 242                                 break;
 243                         case 3:
 244                                 reg = 0x0700;
 245                                 break;
 246                         }
 247                         reg |= (1 << 0);
 248                         reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
 249
 250                         reg_write(win_ctrl_reg + win_jump_index * tmp_count,
 251                                   reg);
 252                         reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000;
 253                         reg_write(win_base_reg + win_jump_index * tmp_count,
 254                                   reg);
 255
 256                         if (win_remap_reg <= REG_XBAR_WIN_7_REMAP_ADDR) {
 257                                 reg_write(win_remap_reg +
 258                                           win_jump_index * tmp_count, 0);
 259                         }
 260
 261                         tmp_count++;
 262                 }
 263         }
 264 }
 265 #endif /*  !defined(STATIC_TRAINING) */
 266
 267 /*
 268  * Name:     ddr3_init - Main DDR3 Init function
 269  * Desc:     This routine initialize the DDR3 MC and runs HW training.
 270  * Args:     None.
 271  * Notes:
 272  * Returns:  None.
 273  */
 274 int ddr3_init(void)
 275 {
 276         unsigned int status;
 277
 278         ddr3_set_pbs(DDR3_PBS);
 279         ddr3_set_sw_wl_rl_debug(DDR3_RUN_SW_WHEN_HW_FAIL);
 280
 281         status = ddr3_init_main();
 282         if (status == MV_DDR3_TRAINING_ERR_BAD_SAR)
 283                 DEBUG_INIT_S("DDR3 Training Error: Bad sample at reset");
 284         if (status == MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP)
 285                 DEBUG_INIT_S("DDR3 Training Error: Bad DIMM setup");
 286         if (status == MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT)
 287                 DEBUG_INIT_S("DDR3 Training Error: Max CS limit");
 288         if (status == MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT)
 289                 DEBUG_INIT_S("DDR3 Training Error: Max enable CS limit");
 290         if (status == MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP)
 291                 DEBUG_INIT_S("DDR3 Training Error: Bad R-DIMM setup");
 292         if (status == MV_DDR3_TRAINING_ERR_TWSI_FAIL)
 293                 DEBUG_INIT_S("DDR3 Training Error: TWSI failure");
 294         if (status == MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH)
 295                 DEBUG_INIT_S("DDR3 Training Error: DIMM type no match");
 296         if (status == MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE)
 297                 DEBUG_INIT_S("DDR3 Training Error: TWSI bad type");
 298         if (status == MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH)
 299                 DEBUG_INIT_S("DDR3 Training Error: bus width no match");
 300         if (status > MV_DDR3_TRAINING_ERR_HW_FAIL_BASE)
 301                 DEBUG_INIT_C("DDR3 Training Error: HW Failure 0x", status, 8);
 302
 303         return status;
 304 }
 305
 306 static void print_ddr_target_freq(u32 cpu_freq, u32 fab_opt)
 307 {
 308         puts("\nDDR3 Training Sequence - Run DDR3 at ");
 309
 310         switch (cpu_freq) {
 311 #if defined(MV88F672X)
 312         case 21:
 313                 puts("533 Mhz\n");
 314                 break;
 315 #else
 316         case 1:
 317                 puts("533 Mhz\n");
 318                 break;
 319         case 2:
 320                 if (fab_opt == 5)
 321                         puts("600 Mhz\n");
 322                 if (fab_opt == 9)
 323                         puts("400 Mhz\n");
 324                 break;
 325         case 3:
 326                 puts("667 Mhz\n");
 327                 break;
 328         case 4:
 329                 if (fab_opt == 5)
 330                         puts("750 Mhz\n");
 331                 if (fab_opt == 9)
 332                         puts("500 Mhz\n");
 333                 break;
 334         case 0xa:
 335                 puts("400 Mhz\n");
 336                 break;
 337         case 0xb:
 338                 if (fab_opt == 5)
 339                         puts("800 Mhz\n");
 340                 if (fab_opt == 9)
 341                         puts("553 Mhz\n");
 342                 if (fab_opt == 0xA)
 343                         puts("640 Mhz\n");
 344                 break;
 345 #endif
 346         default:
 347                 puts("NOT DEFINED FREQ\n");
 348         }
 349 }
 350
 351 static u32 ddr3_init_main(void)
 352 {
 353         u32 target_freq;
 354         u32 reg = 0;
 355         u32 cpu_freq, fab_opt, hclk_time_ps, soc_num;
 356         __maybe_unused u32 ecc = DRAM_ECC;
 357         __maybe_unused int dqs_clk_aligned = 0;
 358         __maybe_unused u32 scrub_offs, scrub_size;
 359         __maybe_unused u32 ddr_width = BUS_WIDTH;
 360         __maybe_unused int status;
 361         __maybe_unused u32 win_backup[16];
 362
 363         /* SoC/Board special Initializtions */
 364         fab_opt = ddr3_get_fab_opt();
 365
 366 #ifdef CONFIG_SPD_EEPROM
 367         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 368 #endif
 369
 370         ddr3_print_version();
 371         DEBUG_INIT_S("4\n");
 372         /* Lib version 5.5.4 */
 373
 374         fab_opt = ddr3_get_fab_opt();
 375
 376         /* Switching CPU to MRVL ID */
 377         soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >>
 378                 SAR1_CPU_CORE_OFFSET;
 379         switch (soc_num) {
 380         case 0x3:
 381                 reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
 382                 reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
 383         case 0x1:
 384                 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
 385         case 0x0:
 386                 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET);
 387         default:
 388                 break;
 389         }
 390
 391         /* Power down deskew PLL */
 392 #if !defined(MV88F672X)
 393         /* 0x18780 [25] */
 394         reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~(1 << 25));
 395         reg_write(REG_DDRPHY_APLL_CTRL_ADDR, reg);
 396 #endif
 397
 398         /*
 399          * Stage 0 - Set board configuration
 400          */
 401         cpu_freq = ddr3_get_cpu_freq();
 402         if (fab_opt > FAB_OPT)
 403                 fab_opt = FAB_OPT - 1;
 404
 405         if (ddr3_get_log_level() > 0)
 406                 print_ddr_target_freq(cpu_freq, fab_opt);
 407
 408 #if defined(MV88F672X)
 409         get_target_freq(cpu_freq, &target_freq, &hclk_time_ps);
 410 #else
 411         target_freq = cpu_ddr_ratios[fab_opt][cpu_freq];
 412         hclk_time_ps = cpu_fab_clk_to_hclk[fab_opt][cpu_freq];
 413 #endif
 414         if ((target_freq == 0) || (hclk_time_ps == 0)) {
 415                 DEBUG_INIT_S("DDR3 Training Sequence - FAILED - Wrong Sample at Reset Configurations\n");
 416                 if (target_freq == 0) {
 417                         DEBUG_INIT_C("target_freq", target_freq, 2);
 418                         DEBUG_INIT_C("fab_opt", fab_opt, 2);
 419                         DEBUG_INIT_C("cpu_freq", cpu_freq, 2);
 420                 } else if (hclk_time_ps == 0) {
 421                         DEBUG_INIT_C("hclk_time_ps", hclk_time_ps, 2);
 422                         DEBUG_INIT_C("fab_opt", fab_opt, 2);
 423                         DEBUG_INIT_C("cpu_freq", cpu_freq, 2);
 424                 }
 425
 426                 return MV_DDR3_TRAINING_ERR_BAD_SAR;
 427         }
 428
 429 #if defined(ECC_SUPPORT)
 430         scrub_offs = U_BOOT_START_ADDR;
 431         scrub_size = U_BOOT_SCRUB_SIZE;
 432 #else
 433         scrub_offs = 0;
 434         scrub_size = 0;
 435 #endif
 436
 437 #if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT)
 438         ecc = DRAM_ECC;
 439 #endif
 440
 441 #if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT)
 442         ecc = 0;
 443         if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_ECC))
 444                 ecc = 1;
 445 #endif
 446
 447 #ifdef DQS_CLK_ALIGNED
 448         dqs_clk_aligned = 1;
 449 #endif
 450
 451         /* Check if DRAM is already initialized  */
 452         if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
 453             (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
 454                 DEBUG_INIT_S("DDR3 Training Sequence - 2nd boot - Skip\n");
 455                 return MV_OK;
 456         }
 457
 458         /*
 459          * Stage 1 - Dunit Setup
 460          */
 461
 462 #ifdef DUNIT_STATIC
 463         /*
 464          * For Static D-Unit Setup use must set the correct static values
 465          * at the ddr3_*soc*_vars.h file
 466          */
 467         DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static MC Init\n");
 468         ddr3_static_mc_init();
 469
 470 #ifdef ECC_SUPPORT
 471         ecc = DRAM_ECC;
 472         if (ecc) {
 473                 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
 474                 reg |= (1 << REG_SDRAM_CONFIG_ECC_OFFS);
 475                 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
 476         }
 477 #endif
 478 #endif
 479
 480 #if defined(MV88F78X60) || defined(MV88F672X)
 481 #if defined(AUTO_DETECTION_SUPPORT)
 482         /*
 483          * Configurations for both static and dynamic MC setups
 484          *
 485          * Dynamically Set 32Bit and ECC for AXP (Relevant only for
 486          * Marvell DB boards)
 487          */
 488         if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_BUS_WIDTH)) {
 489                 ddr_width = 32;
 490                 DEBUG_INIT_S("DDR3 Training Sequence - DRAM bus width 32Bit\n");
 491         }
 492 #endif
 493
 494 #if defined(MV88F672X)
 495         reg = reg_read(REG_SDRAM_CONFIG_ADDR);
 496         if ((reg >> 15) & 1)
 497                 ddr_width = 32;
 498         else
 499                 ddr_width = 16;
 500 #endif
 501 #endif
 502
 503 #ifdef DUNIT_SPD
 504         status = ddr3_dunit_setup(ecc, hclk_time_ps, &ddr_width);
 505         if (MV_OK != status) {
 506                 DEBUG_INIT_S("DDR3 Training Sequence - FAILED (ddr3 Dunit Setup)\n");
 507                 return status;
 508         }
 509 #endif
 510
 511         /* Fix read ready phases for all SOC in reg 0x15C8 */
 512         reg = reg_read(REG_TRAINING_DEBUG_3_ADDR);
 513         reg &= ~(REG_TRAINING_DEBUG_3_MASK);
 514         reg |= 0x4;             /* Phase 0 */
 515         reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS);
 516         reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS));        /* Phase 1 */
 517         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS));
 518         reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS));        /* Phase 3 */
 519         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS));
 520         reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS));
 521         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS));
 522         reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS));
 523         reg_write(REG_TRAINING_DEBUG_3_ADDR, reg);
 524
 525 #if defined(MV88F672X)
 526         /*
 527          * AxiBrespMode[8] = Compliant,
 528          * AxiAddrDecodeCntrl[11] = Internal,
 529          * AxiDataBusWidth[0] = 128bit
 530          */
 531         /* 0x14A8 - AXI Control Register */
 532         reg_write(REG_DRAM_AXI_CTRL_ADDR, 0);
 533 #else
 534         /* 0x14A8 - AXI Control Register */
 535         reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000100);
 536         reg_write(REG_CDI_CONFIG_ADDR, 0x00000006);
 537
 538         if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) &
 539                                   (1 << REG_DDR_IO_CLK_RATIO_OFFS))) {
 540                 /* 0x14A8 - AXI Control Register */
 541                 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000101);
 542                 reg_write(REG_CDI_CONFIG_ADDR, 0x00000007);
 543         }
 544 #endif
 545
 546 #if !defined(MV88F67XX)
 547         /*
 548          * ARMADA-370 activate DLB later at the u-boot,
 549          * Armada38x - No DLB activation at this time
 550          */
 551         reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x18C01E);
 552
 553 #if defined(MV88F78X60)
 554         /* WA according to eratta GL-8672902*/
 555         if (mv_ctrl_rev_get() == MV_78XX0_B0_REV)
 556                 reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0xc19e);
 557 #endif
 558
 559         reg_write(DLB_AGING_REGISTER, 0x0f7f007f);
 560         reg_write(DLB_EVICTION_CONTROL_REG, 0x0);
 561         reg_write(DLB_EVICTION_TIMERS_REGISTER_REG, 0x00FF3C1F);
 562
 563         reg_write(MBUS_UNITS_PRIORITY_CONTROL_REG, 0x55555555);
 564         reg_write(FABRIC_UNITS_PRIORITY_CONTROL_REG, 0xAA);
 565         reg_write(MBUS_UNITS_PREFETCH_CONTROL_REG, 0xffff);
 566         reg_write(FABRIC_UNITS_PREFETCH_CONTROL_REG, 0xf0f);
 567
 568 #if defined(MV88F78X60)
 569         /* WA according to eratta GL-8672902 */
 570         if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) {
 571                 reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
 572                 reg |= DLB_ENABLE;
 573                 reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
 574         }
 575 #endif /* end defined(MV88F78X60) */
 576 #endif /* end !defined(MV88F67XX) */
 577
 578         if (ddr3_get_log_level() >= MV_LOG_LEVEL_1)
 579                 print_dunit_setup();
 580
 581         /*
 582          * Stage 2 - Training Values Setup
 583          */
 584 #ifdef STATIC_TRAINING
 585         /*
 586          * DRAM Init - After all the D-unit values are set, its time to init
 587          * the D-unit
 588          */
 589         /* Wait for '0' */
 590         reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);
 591         do {
 592                 reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
 593                         (1 << REG_SDRAM_INIT_CTRL_OFFS);
 594         } while (reg);
 595
 596         /* ddr3 init using static parameters - HW training is disabled */
 597         DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static Training Parameters\n");
 598         ddr3_static_training_init();
 599
 600 #if defined(MV88F78X60)
 601         /*
 602          * If ECC is enabled, need to scrub the U-Boot area memory region -
 603          * Run training function with Xor bypass just to scrub the memory
 604          */
 605         status = ddr3_hw_training(target_freq, ddr_width,
 606                                   1, scrub_offs, scrub_size,
 607                                   dqs_clk_aligned, DDR3_TRAINING_DEBUG,
 608                                   REG_DIMM_SKIP_WL);
 609         if (MV_OK != status) {
 610                 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");
 611                 return status;
 612         }
 613 #endif
 614 #else
 615         /* Set X-BAR windows for the training sequence */
 616         ddr3_save_and_set_training_windows(win_backup);
 617
 618         /* Run DDR3 Training Sequence */
 619         /* DRAM Init */
 620         reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);
 621         do {
 622                 reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
 623                         (1 << REG_SDRAM_INIT_CTRL_OFFS);
 624         } while (reg);          /* Wait for '0' */
 625
 626         /* ddr3 init using DDR3 HW training procedure */
 627         DEBUG_INIT_FULL_S("DDR3 Training Sequence - HW Training Procedure\n");
 628         status = ddr3_hw_training(target_freq, ddr_width,
 629                                   0, scrub_offs, scrub_size,
 630                                   dqs_clk_aligned, DDR3_TRAINING_DEBUG,
 631                                   REG_DIMM_SKIP_WL);
 632         if (MV_OK != status) {
 633                 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");
 634                 return status;
 635         }
 636 #endif
 637
 638         /*
 639          * Stage 3 - Finish
 640          */
 641 #if defined(MV88F78X60) || defined(MV88F672X)
 642         /* Disable ECC Ignore bit */
 643         reg = reg_read(REG_SDRAM_CONFIG_ADDR) &
 644                 ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
 645         reg_write(REG_SDRAM_CONFIG_ADDR, reg);
 646 #endif
 647
 648 #if !defined(STATIC_TRAINING)
 649         /* Restore and set windows */
 650         ddr3_restore_and_set_final_windows(win_backup);
 651 #endif
 652
 653         /* Update DRAM init indication in bootROM register */
 654         reg = reg_read(REG_BOOTROM_ROUTINE_ADDR);
 655         reg_write(REG_BOOTROM_ROUTINE_ADDR,
 656                   reg | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS));
 657
 658 #if !defined(MV88F67XX)
 659 #if defined(MV88F78X60)
 660         if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) {
 661                 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
 662                 if (ecc == 0)
 663                         reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19));
 664         }
 665 #endif /* end defined(MV88F78X60) */
 666
 667         reg_write(DLB_EVICTION_CONTROL_REG, 0x9);
 668
 669         reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
 670         reg |= (DLB_ENABLE | DLB_WRITE_COALESING | DLB_AXI_PREFETCH_EN |
 671                 DLB_MBUS_PREFETCH_EN | PREFETCH_NLNSZTR);
 672         reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
 673 #endif /* end !defined(MV88F67XX) */
 674
 675 #ifdef STATIC_TRAINING
 676         DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully (S)\n");
 677 #else
 678         DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully\n");
 679 #endif
 680
 681         return MV_OK;
 682 }
 683
 684 /*
 685  * Name:     ddr3_get_cpu_freq
 686  * Desc:     read S@R and return CPU frequency
 687  * Args:
 688  * Notes:
 689  * Returns:  required value
 690  */
 691
 692 u32 ddr3_get_cpu_freq(void)
 693 {
 694         u32 reg, cpu_freq;
 695
 696 #if defined(MV88F672X)
 697         /* Read sample at reset setting */
 698         reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);     /* 0xE8200 */
 699         cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
 700                 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
 701 #else
 702         /* Read sample at reset setting */
 703         reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR);      /* 0x18230 [23:21] */
 704 #if defined(MV88F78X60)
 705         cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
 706                 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
 707         reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);     /* 0x18234 [20] */
 708         cpu_freq |= (((reg >> REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS) & 0x1) << 3);
 709 #elif defined(MV88F67XX)
 710         cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
 711                 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
 712 #endif
 713 #endif
 714
 715         return cpu_freq;
 716 }
 717
 718 /*
 719  * Name:     ddr3_get_fab_opt
 720  * Desc:     read S@R and return CPU frequency
 721  * Args:
 722  * Notes:
 723  * Returns:  required value
 724  */
 725 u32 ddr3_get_fab_opt(void)
 726 {
 727         __maybe_unused u32 reg, fab_opt;
 728
 729 #if defined(MV88F672X)
 730         return 0;               /* No fabric */
 731 #else
 732         /* Read sample at reset setting */
 733         reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR);
 734         fab_opt = (reg & REG_SAMPLE_RESET_FAB_MASK) >>
 735                 REG_SAMPLE_RESET_FAB_OFFS;
 736
 737 #if defined(MV88F78X60)
 738         reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);
 739         fab_opt |= (((reg >> 19) & 0x1) << 4);
 740 #endif
 741
 742         return fab_opt;
 743 #endif
 744 }
 745
 746 /*
 747  * Name:     ddr3_get_vco_freq
 748  * Desc:     read S@R and return VCO frequency
 749  * Args:
 750  * Notes:
 751  * Returns:  required value
 752  */
 753 u32 ddr3_get_vco_freq(void)
 754 {
 755         u32 fab, cpu_freq, ui_vco_freq;
 756
 757         fab = ddr3_get_fab_opt();
 758         cpu_freq = ddr3_get_cpu_freq();
 759
 760         if (fab == 2 || fab == 3 || fab == 7 || fab == 8 || fab == 10 ||
 761             fab == 15 || fab == 17 || fab == 20)
 762                 ui_vco_freq = cpu_freq + CLK_CPU;
 763         else
 764                 ui_vco_freq = cpu_freq;
 765
 766         return ui_vco_freq;
 767 }
 768
 769 #ifdef STATIC_TRAINING
 770 /*
 771  * Name:     ddr3_static_training_init - Init DDR3 Training with
 772  *           static parameters
 773  * Desc:     Use this routine to init the controller without the HW training
 774  *           procedure
 775  *           User must provide compatible header file with registers data.
 776  * Args:     None.
 777  * Notes:
 778  * Returns:  None.
 779  */
 780 void ddr3_static_training_init(void)
 781 {
 782         MV_DRAM_MODES *ddr_mode;
 783         u32 reg;
 784         int j;
 785
 786         ddr_mode = ddr3_get_static_ddr_mode();
 787
 788         j = 0;
 789         while (ddr_mode->vals[j].reg_addr != 0) {
 790                 udelay(10);     /* haim want to delay each write */
 791                 reg_write(ddr_mode->vals[j].reg_addr,
 792                           ddr_mode->vals[j].reg_value);
 793
 794                 if (ddr_mode->vals[j].reg_addr ==
 795                     REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
 796                         do {
 797                                 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
 798                                         REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
 799                         } while (reg);
 800                 j++;
 801         }
 802 }
 803 #endif
 804
 805 /*
 806  * Name:     ddr3_get_static_mc_value - Init Memory controller with static
 807  *           parameters
 808  * Desc:     Use this routine to init the controller without the HW training
 809  *           procedure
 810  *           User must provide compatible header file with registers data.
 811  * Args:     None.
 812  * Notes:
 813  * Returns:  None.
 814  */
 815 u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2,
 816                              u32 mask2)
 817 {
 818         u32 reg, tmp;
 819
 820         reg = reg_read(reg_addr);
 821
 822         tmp = (reg >> offset1) & mask1;
 823         if (mask2)
 824                 tmp |= (reg >> offset2) & mask2;
 825
 826         return tmp;
 827 }
 828
 829 /*
 830  * Name:     ddr3_get_static_ddr_mode - Init Memory controller with static
 831  *           parameters
 832  * Desc:     Use this routine to init the controller without the HW training
 833  *           procedure
 834  *           User must provide compatible header file with registers data.
 835  * Args:     None.
 836  * Notes:
 837  * Returns:  None.
 838  */
 839 __weak MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
 840 {
 841         u32 chip_board_rev, i;
 842         u32 size;
 843
 844         /* Do not modify this code. relevant only for marvell Boards */
 845 #if defined(DB_78X60_PCAC)
 846         chip_board_rev = Z1_PCAC;
 847 #elif defined(DB_78X60_AMC)
 848         chip_board_rev = A0_AMC;
 849 #elif defined(DB_88F6710_PCAC)
 850         chip_board_rev = A0_PCAC;
 851 #elif defined(RD_88F6710)
 852         chip_board_rev = A0_RD;
 853 #elif defined(MV88F672X)
 854         chip_board_rev = mv_board_id_get();
 855 #else
 856         chip_board_rev = A0;
 857 #endif
 858
 859         size = sizeof(ddr_modes) / sizeof(MV_DRAM_MODES);
 860         for (i = 0; i < size; i++) {
 861                 if ((ddr3_get_cpu_freq() == ddr_modes[i].cpu_freq) &&
 862                     (ddr3_get_fab_opt() == ddr_modes[i].fab_freq) &&
 863                     (chip_board_rev == ddr_modes[i].chip_board_rev))
 864                         return &ddr_modes[i];
 865         }
 866
 867         return &ddr_modes[0];
 868 }
 869
 870 #ifdef DUNIT_STATIC
 871 /*
 872  * Name:     ddr3_static_mc_init - Init Memory controller with static parameters
 873  * Desc:     Use this routine to init the controller without the HW training
 874  *           procedure
 875  *           User must provide compatible header file with registers data.
 876  * Args:     None.
 877  * Notes:
 878  * Returns:  None.
 879  */
 880 void ddr3_static_mc_init(void)
 881 {
 882         MV_DRAM_MODES *ddr_mode;
 883         u32 reg;
 884         int j;
 885
 886         ddr_mode = ddr3_get_static_ddr_mode();
 887         j = 0;
 888         while (ddr_mode->regs[j].reg_addr != 0) {
 889                 reg_write(ddr_mode->regs[j].reg_addr,
 890                           ddr_mode->regs[j].reg_value);
 891                 if (ddr_mode->regs[j].reg_addr ==
 892                     REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
 893                         do {
 894                                 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
 895                                         REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
 896                         } while (reg);
 897                 j++;
 898         }
 899 }
 900 #endif
 901
 902 /*
 903  * Name:     ddr3_check_config - Check user configurations: ECC/MultiCS
 904  * Desc:
 905  * Args:     twsi Address
 906  * Notes:    Only Available for ArmadaXP/Armada 370 DB boards
 907  * Returns:  None.
 908  */
 909 int ddr3_check_config(u32 twsi_addr, MV_CONFIG_TYPE config_type)
 910 {
 911 #ifdef AUTO_DETECTION_SUPPORT
 912         u8 data = 0;
 913         int ret;
 914         int offset;
 915
 916         if ((config_type == CONFIG_ECC) || (config_type == CONFIG_BUS_WIDTH))
 917                 offset = 1;
 918         else
 919                 offset = 0;
 920
 921         ret = i2c_read(twsi_addr, offset, 1, (u8 *)&data, 1);
 922         if (!ret) {
 923                 switch (config_type) {
 924                 case CONFIG_ECC:
 925                         if (data & 0x2)
 926                                 return 1;
 927                         break;
 928                 case CONFIG_BUS_WIDTH:
 929                         if (data & 0x1)
 930                                 return 1;
 931                         break;
 932 #ifdef DB_88F6710
 933                 case CONFIG_MULTI_CS:
 934                         if (CFG_MULTI_CS_MODE(data))
 935                                 return 1;
 936                         break;
 937 #else
 938                 case CONFIG_MULTI_CS:
 939                         break;
 940 #endif
 941                 }
 942         }
 943 #endif
 944
 945         return 0;
 946 }
 947
 948 #if defined(DB_88F78X60_REV2)
 949 /*
 950  * Name:     ddr3_get_eprom_fabric - Get Fabric configuration from EPROM
 951  * Desc:
 952  * Args:     twsi Address
 953  * Notes:    Only Available for ArmadaXP DB Rev2 boards
 954  * Returns:  None.
 955  */
 956 u8 ddr3_get_eprom_fabric(void)
 957 {
 958 #ifdef AUTO_DETECTION_SUPPORT
 959         u8 data = 0;
 960         int ret;
 961
 962         ret = i2c_read(NEW_FABRIC_TWSI_ADDR, 1, 1, (u8 *)&data, 1);
 963         if (!ret)
 964                 return data & 0x1F;
 965 #endif
 966
 967         return 0;
 968 }
 969
 970 #endif
 971
 972 /*
 973  * Name:     ddr3_cl_to_valid_cl - this return register matching CL value
 974  * Desc:
 975  * Args:     clValue - the value
 976
 977  * Notes:
 978  * Returns:  required CL value
 979  */
 980 u32 ddr3_cl_to_valid_cl(u32 cl)
 981 {
 982         switch (cl) {
 983         case 5:
 984                 return 2;
 985                 break;
 986         case 6:
 987                 return 4;
 988                 break;
 989         case 7:
 990                 return 6;
 991                 break;
 992         case 8:
 993                 return 8;
 994                 break;
 995         case 9:
 996                 return 10;
 997                 break;
 998         case 10:
 999                 return 12;
1000                 break;
1001         case 11:
1002                 return 14;
1003                 break;
1004         case 12:
1005                 return 1;
1006                 break;
1007         case 13:
1008                 return 3;
1009                 break;
1010         case 14:
1011                 return 5;
1012                 break;
1013         default:
1014                 return 2;
1015         }
1016 }
1017
1018 /*
1019  * Name:     ddr3_cl_to_valid_cl - this return register matching CL value
1020  * Desc:
1021  * Args:     clValue - the value
1022  * Notes:
1023  * Returns:  required CL value
1024  */
1025 u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl)
1026 {
1027         switch (ui_valid_cl) {
1028         case 1:
1029                 return 12;
1030                 break;
1031         case 2:
1032                 return 5;
1033                 break;
1034         case 3:
1035                 return 13;
1036                 break;
1037         case 4:
1038                 return 6;
1039                 break;
1040         case 5:
1041                 return 14;
1042                 break;
1043         case 6:
1044                 return 7;
1045                 break;
1046         case 8:
1047                 return 8;
1048                 break;
1049         case 10:
1050                 return 9;
1051                 break;
1052         case 12:
1053                 return 10;
1054                 break;
1055         case 14:
1056                 return 11;
1057                 break;
1058         default:
1059                 return 0;
1060         }
1061 }
1062
1063 /*
1064  * Name:     ddr3_get_cs_num_from_reg
1065  * Desc:
1066  * Args:
1067  * Notes:
1068  * Returns:
1069  */
1070 u32 ddr3_get_cs_num_from_reg(void)
1071 {
1072         u32 cs_ena = ddr3_get_cs_ena_from_reg();
1073         u32 cs_count = 0;
1074         u32 cs;
1075
1076         for (cs = 0; cs < MAX_CS; cs++) {
1077                 if (cs_ena & (1 << cs))
1078                         cs_count++;
1079         }
1080
1081         return cs_count;
1082 }
1083
1084 /*
1085  * Name:     ddr3_get_cs_ena_from_reg
1086  * Desc:
1087  * Args:
1088  * Notes:
1089  * Returns:
1090  */
1091 u32 ddr3_get_cs_ena_from_reg(void)
1092 {
1093         return reg_read(REG_DDR3_RANK_CTRL_ADDR) &
1094                 REG_DDR3_RANK_CTRL_CS_ENA_MASK;
1095 }
1096
1097 /*
1098  * mv_ctrl_rev_get - Get Marvell controller device revision number
1099  *
1100  * DESCRIPTION:
1101  *       This function returns 8bit describing the device revision as defined
1102  *       in PCI Express Class Code and Revision ID Register.
1103  *
1104  * INPUT:
1105  *       None.
1106  *
1107  * OUTPUT:
1108  *       None.
1109  *
1110  * RETURN:
1111  *       8bit desscribing Marvell controller revision number
1112  *
1113  */
1114 #if !defined(MV88F672X)
1115 u8 mv_ctrl_rev_get(void)
1116 {
1117         u8 rev_num;
1118
1119 #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
1120         /* Check pex power state */
1121         u32 pex_power;
1122         pex_power = mv_ctrl_pwr_clck_get(PEX_UNIT_ID, 0);
1123         if (pex_power == 0)
1124                 mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 1);
1125 #endif
1126         rev_num = (u8)reg_read(PEX_CFG_DIRECT_ACCESS(0,
1127                         PCI_CLASS_CODE_AND_REVISION_ID));
1128
1129 #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
1130         /* Return to power off state */
1131         if (pex_power == 0)
1132                 mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 0);
1133 #endif
1134
1135         return (rev_num & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS;
1136 }
1137
1138 #endif
1139
1140 #if defined(MV88F672X)
1141 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps)
1142 {
1143         u32 tmp, hclk;
1144
1145         switch (freq_mode) {
1146         case CPU_333MHz_DDR_167MHz_L2_167MHz:
1147                 hclk = 84;
1148                 tmp = DDR_100;
1149                 break;
1150         case CPU_266MHz_DDR_266MHz_L2_133MHz:
1151         case CPU_333MHz_DDR_222MHz_L2_167MHz:
1152         case CPU_400MHz_DDR_200MHz_L2_200MHz:
1153         case CPU_400MHz_DDR_267MHz_L2_200MHz:
1154         case CPU_533MHz_DDR_267MHz_L2_267MHz:
1155         case CPU_500MHz_DDR_250MHz_L2_250MHz:
1156         case CPU_600MHz_DDR_300MHz_L2_300MHz:
1157         case CPU_800MHz_DDR_267MHz_L2_400MHz:
1158         case CPU_900MHz_DDR_300MHz_L2_450MHz:
1159                 tmp = DDR_300;
1160                 hclk = 150;
1161                 break;
1162         case CPU_333MHz_DDR_333MHz_L2_167MHz:
1163         case CPU_500MHz_DDR_334MHz_L2_250MHz:
1164         case CPU_666MHz_DDR_333MHz_L2_333MHz:
1165                 tmp = DDR_333;
1166                 hclk = 165;
1167                 break;
1168         case CPU_533MHz_DDR_356MHz_L2_267MHz:
1169                 tmp = DDR_360;
1170                 hclk = 180;
1171                 break;
1172         case CPU_400MHz_DDR_400MHz_L2_200MHz:
1173         case CPU_600MHz_DDR_400MHz_L2_300MHz:
1174         case CPU_800MHz_DDR_400MHz_L2_400MHz:
1175         case CPU_400MHz_DDR_400MHz_L2_400MHz:
1176                 tmp = DDR_400;
1177                 hclk = 200;
1178                 break;
1179         case CPU_666MHz_DDR_444MHz_L2_333MHz:
1180         case CPU_900MHz_DDR_450MHz_L2_450MHz:
1181                 tmp = DDR_444;
1182                 hclk = 222;
1183                 break;
1184         case CPU_500MHz_DDR_500MHz_L2_250MHz:
1185         case CPU_1000MHz_DDR_500MHz_L2_500MHz:
1186         case CPU_1000MHz_DDR_500MHz_L2_333MHz:
1187                 tmp = DDR_500;
1188                 hclk = 250;
1189                 break;
1190         case CPU_533MHz_DDR_533MHz_L2_267MHz:
1191         case CPU_800MHz_DDR_534MHz_L2_400MHz:
1192         case CPU_1100MHz_DDR_550MHz_L2_550MHz:
1193                 tmp = DDR_533;
1194                 hclk = 267;
1195                 break;
1196         case CPU_600MHz_DDR_600MHz_L2_300MHz:
1197         case CPU_900MHz_DDR_600MHz_L2_450MHz:
1198         case CPU_1200MHz_DDR_600MHz_L2_600MHz:
1199                 tmp = DDR_600;
1200                 hclk = 300;
1201                 break;
1202         case CPU_666MHz_DDR_666MHz_L2_333MHz:
1203         case CPU_1000MHz_DDR_667MHz_L2_500MHz:
1204                 tmp = DDR_666;
1205                 hclk = 333;
1206                 break;
1207         default:
1208                 *ddr_freq = 0;
1209                 *hclk_ps = 0;
1210                 break;
1211         }
1212
1213         *ddr_freq = tmp;                /* DDR freq define */
1214         *hclk_ps = 1000000 / hclk;      /* values are 1/HCLK in ps */
1215
1216         return;
1217 }
1218 #endif