git.sur5r.net Git - u-boot/blob - drivers/ddr/mvebu/ddr3_init.c

   1 /*
   2  * Copyright (C) Marvell International Ltd. and its affiliates
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <spl.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/soc.h>
  13
  14 #include "ddr3_init.h"
  15
  16 #if defined(MV88F78X60)
  17 #include "ddr3_axp_vars.h"
  18 #elif defined(MV88F67XX)
  19 #include "ddr3_a370_vars.h"
  20 #elif defined(MV88F672X)
  21 #include "ddr3_a375_vars.h"
  22 #endif
  23
  24 #ifdef STATIC_TRAINING
  25 static void ddr3_static_training_init(void);
  26 #endif
  27 #ifdef DUNIT_STATIC
  28 static void ddr3_static_mc_init(void);
  29 #endif
  30 #if defined(DUNIT_STATIC) || defined(STATIC_TRAINING)
  31 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void);
  32 #endif
  33 #if defined(MV88F672X)
  34 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
  35 #endif
  36 u32 mv_board_id_get(void);
  37 extern void ddr3_set_sw_wl_rl_debug(u32);
  38 extern void ddr3_set_pbs(u32);
  39 extern void ddr3_set_log_level(u32 val);
  40
  41 static u32 log_level = DDR3_LOG_LEVEL;
  42
  43 static u32 ddr3_init_main(void);
  44
  45 /*
  46  * Name:     ddr3_set_log_level
  47  * Desc:     This routine initialize the log_level acording to nLogLevel
  48  *           which getting from user
  49  * Args:     nLogLevel
  50  * Notes:
  51  * Returns:  None.
  52  */
  53 void ddr3_set_log_level(u32 val)
  54 {
  55         log_level = val;
  56 }
  57
  58 /*
  59  * Name:     ddr3_get_log_level
  60  * Desc:     This routine returns the log level
  61  * Args:     none
  62  * Notes:
  63  * Returns:  log level.
  64  */
  65 u32 ddr3_get_log_level(void)
  66 {
  67         return log_level;
  68 }
  69
  70 static void debug_print_reg(u32 reg)
  71 {
  72         printf("0x%08x = 0x%08x\n", reg, reg_read(reg));
  73 }
  74
  75 static void print_dunit_setup(void)
  76 {
  77         puts("\n########### LOG LEVEL 1 (D-UNIT SETUP)###########\n");
  78
  79 #ifdef DUNIT_STATIC
  80         puts("\nStatic D-UNIT Setup:\n");
  81 #endif
  82 #ifdef DUNIT_SPD
  83         puts("\nDynamic(using SPD) D-UNIT Setup:\n");
  84 #endif
  85         debug_print_reg(REG_SDRAM_CONFIG_ADDR);
  86         debug_print_reg(REG_DUNIT_CTRL_LOW_ADDR);
  87         debug_print_reg(REG_SDRAM_TIMING_LOW_ADDR);
  88         debug_print_reg(REG_SDRAM_TIMING_HIGH_ADDR);
  89         debug_print_reg(REG_SDRAM_ADDRESS_CTRL_ADDR);
  90         debug_print_reg(REG_SDRAM_OPEN_PAGES_ADDR);
  91         debug_print_reg(REG_SDRAM_OPERATION_ADDR);
  92         debug_print_reg(REG_SDRAM_MODE_ADDR);
  93         debug_print_reg(REG_SDRAM_EXT_MODE_ADDR);
  94         debug_print_reg(REG_DDR_CONT_HIGH_ADDR);
  95         debug_print_reg(REG_ODT_TIME_LOW_ADDR);
  96         debug_print_reg(REG_SDRAM_ERROR_ADDR);
  97         debug_print_reg(REG_SDRAM_AUTO_PWR_SAVE_ADDR);
  98         debug_print_reg(REG_OUDDR3_TIMING_ADDR);
  99         debug_print_reg(REG_ODT_TIME_HIGH_ADDR);
 100         debug_print_reg(REG_SDRAM_ODT_CTRL_LOW_ADDR);
 101         debug_print_reg(REG_SDRAM_ODT_CTRL_HIGH_ADDR);
 102         debug_print_reg(REG_DUNIT_ODT_CTRL_ADDR);
 103 #ifndef MV88F67XX
 104         debug_print_reg(REG_DRAM_FIFO_CTRL_ADDR);
 105         debug_print_reg(REG_DRAM_AXI_CTRL_ADDR);
 106         debug_print_reg(REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR);
 107         debug_print_reg(REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR);
 108         debug_print_reg(REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR);
 109         debug_print_reg(REG_DRAM_MAIN_PADS_CAL_ADDR);
 110         debug_print_reg(REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR);
 111         debug_print_reg(REG_CS_SIZE_SCRATCH_ADDR);
 112         debug_print_reg(REG_DYNAMIC_POWER_SAVE_ADDR);
 113         debug_print_reg(REG_READ_DATA_SAMPLE_DELAYS_ADDR);
 114         debug_print_reg(REG_READ_DATA_READY_DELAYS_ADDR);
 115         debug_print_reg(REG_DDR3_MR0_ADDR);
 116         debug_print_reg(REG_DDR3_MR1_ADDR);
 117         debug_print_reg(REG_DDR3_MR2_ADDR);
 118         debug_print_reg(REG_DDR3_MR3_ADDR);
 119         debug_print_reg(REG_DDR3_RANK_CTRL_ADDR);
 120         debug_print_reg(REG_DRAM_PHY_CONFIG_ADDR);
 121         debug_print_reg(REG_STATIC_DRAM_DLB_CONTROL);
 122         debug_print_reg(DLB_BUS_OPTIMIZATION_WEIGHTS_REG);
 123         debug_print_reg(DLB_AGING_REGISTER);
 124         debug_print_reg(DLB_EVICTION_CONTROL_REG);
 125         debug_print_reg(DLB_EVICTION_TIMERS_REGISTER_REG);
 126 #if defined(MV88F672X)
 127         debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(0));
 128         debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(0));
 129         debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(1));
 130         debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(1));
 131 #else
 132         debug_print_reg(REG_FASTPATH_WIN_0_CTRL_ADDR);
 133 #endif
 134         debug_print_reg(REG_CDI_CONFIG_ADDR);
 135 #endif
 136 }
 137
 138 #if !defined(STATIC_TRAINING)
 139 static void ddr3_restore_and_set_final_windows(u32 *win_backup)
 140 {
 141         u32 ui, reg, cs;
 142         u32 win_ctrl_reg, num_of_win_regs;
 143         u32 cs_ena = ddr3_get_cs_ena_from_reg();
 144
 145 #if defined(MV88F672X)
 146         if (DDR3_FAST_PATH_EN == 0)
 147                 return;
 148 #endif
 149
 150 #if defined(MV88F672X)
 151         win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR;
 152         num_of_win_regs = 8;
 153 #else
 154         win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
 155         num_of_win_regs = 16;
 156 #endif
 157
 158         /* Return XBAR windows 4-7 or 16-19 init configuration */
 159         for (ui = 0; ui < num_of_win_regs; ui++)
 160                 reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]);
 161
 162         DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n");
 163
 164 #if defined(MV88F672X)
 165         /* Set L2 filtering to 1G */
 166         reg_write(0x8c04, 0x40000000);
 167
 168         /* Open fast path windows */
 169         for (cs = 0; cs < MAX_CS; cs++) {
 170                 if (cs_ena & (1 << cs)) {
 171                         /* set fast path window control for the cs */
 172                         reg = 0x1FFFFFE1;
 173                         reg |= (cs << 2);
 174                         reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
 175                         /* Open fast path Window */
 176                         reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg);
 177                         /* set fast path window base address for the cs */
 178                         reg = (((SDRAM_CS_SIZE + 1) * cs) & 0xFFFF0000);
 179                         /* Set base address */
 180                         reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg);
 181                 }
 182         }
 183 #else
 184         reg = 0x1FFFFFE1;
 185         for (cs = 0; cs < MAX_CS; cs++) {
 186                 if (cs_ena & (1 << cs)) {
 187                         reg |= (cs << 2);
 188                         break;
 189                 }
 190         }
 191
 192         /* Open fast path Window to - 0.5G */
 193         reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg);
 194 #endif
 195 }
 196
 197 static void ddr3_save_and_set_training_windows(u32 *win_backup)
 198 {
 199         u32 cs_ena = ddr3_get_cs_ena_from_reg();
 200         u32 reg, tmp_count, cs, ui;
 201         u32 win_ctrl_reg, win_base_reg, win_remap_reg;
 202         u32 num_of_win_regs, win_jump_index;
 203
 204 #if defined(MV88F672X)
 205         /* Disable L2 filtering */
 206         reg_write(0x8c04, 0);
 207
 208         win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR;
 209         win_base_reg = REG_XBAR_WIN_16_BASE_ADDR;
 210         win_remap_reg = REG_XBAR_WIN_16_REMAP_ADDR;
 211         win_jump_index = 0x8;
 212         num_of_win_regs = 8;
 213 #else
 214         win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
 215         win_base_reg = REG_XBAR_WIN_4_BASE_ADDR;
 216         win_remap_reg = REG_XBAR_WIN_4_REMAP_ADDR;
 217         win_jump_index = 0x10;
 218         num_of_win_regs = 16;
 219 #endif
 220
 221         /* Close XBAR Window 19 - Not needed */
 222         /* {0x000200e8}  -   Open Mbus Window - 2G */
 223         reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0);
 224
 225         /* Save XBAR Windows 4-19 init configurations */
 226         for (ui = 0; ui < num_of_win_regs; ui++)
 227                 win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui);
 228
 229         /* Open XBAR Windows 4-7 or 16-19 for other CS */
 230         reg = 0;
 231         tmp_count = 0;
 232         for (cs = 0; cs < MAX_CS; cs++) {
 233                 if (cs_ena & (1 << cs)) {
 234                         switch (cs) {
 235                         case 0:
 236                                 reg = 0x0E00;
 237                                 break;
 238                         case 1:
 239                                 reg = 0x0D00;
 240                                 break;
 241                         case 2:
 242                                 reg = 0x0B00;
 243                                 break;
 244                         case 3:
 245                                 reg = 0x0700;
 246                                 break;
 247                         }
 248                         reg |= (1 << 0);
 249                         reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
 250
 251                         reg_write(win_ctrl_reg + win_jump_index * tmp_count,
 252                                   reg);
 253                         reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000;
 254                         reg_write(win_base_reg + win_jump_index * tmp_count,
 255                                   reg);
 256
 257                         if (win_remap_reg <= REG_XBAR_WIN_7_REMAP_ADDR) {
 258                                 reg_write(win_remap_reg +
 259                                           win_jump_index * tmp_count, 0);
 260                         }
 261
 262                         tmp_count++;
 263                 }
 264         }
 265 }
 266 #endif /*  !defined(STATIC_TRAINING) */
 267
 268 /*
 269  * Name:     ddr3_init - Main DDR3 Init function
 270  * Desc:     This routine initialize the DDR3 MC and runs HW training.
 271  * Args:     None.
 272  * Notes:
 273  * Returns:  None.
 274  */
 275 int ddr3_init(void)
 276 {
 277         unsigned int status;
 278
 279         ddr3_set_pbs(DDR3_PBS);
 280         ddr3_set_sw_wl_rl_debug(DDR3_RUN_SW_WHEN_HW_FAIL);
 281
 282         status = ddr3_init_main();
 283         if (status == MV_DDR3_TRAINING_ERR_BAD_SAR)
 284                 DEBUG_INIT_S("DDR3 Training Error: Bad sample at reset");
 285         if (status == MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP)
 286                 DEBUG_INIT_S("DDR3 Training Error: Bad DIMM setup");
 287         if (status == MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT)
 288                 DEBUG_INIT_S("DDR3 Training Error: Max CS limit");
 289         if (status == MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT)
 290                 DEBUG_INIT_S("DDR3 Training Error: Max enable CS limit");
 291         if (status == MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP)
 292                 DEBUG_INIT_S("DDR3 Training Error: Bad R-DIMM setup");
 293         if (status == MV_DDR3_TRAINING_ERR_TWSI_FAIL)
 294                 DEBUG_INIT_S("DDR3 Training Error: TWSI failure");
 295         if (status == MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH)
 296                 DEBUG_INIT_S("DDR3 Training Error: DIMM type no match");
 297         if (status == MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE)
 298                 DEBUG_INIT_S("DDR3 Training Error: TWSI bad type");
 299         if (status == MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH)
 300                 DEBUG_INIT_S("DDR3 Training Error: bus width no match");
 301         if (status > MV_DDR3_TRAINING_ERR_HW_FAIL_BASE)
 302                 DEBUG_INIT_C("DDR3 Training Error: HW Failure 0x", status, 8);
 303
 304         return status;
 305 }
 306
 307 static void print_ddr_target_freq(u32 cpu_freq, u32 fab_opt)
 308 {
 309         puts("\nDDR3 Training Sequence - Run DDR3 at ");
 310
 311         switch (cpu_freq) {
 312 #if defined(MV88F672X)
 313         case 21:
 314                 puts("533 Mhz\n");
 315                 break;
 316 #else
 317         case 1:
 318                 puts("533 Mhz\n");
 319                 break;
 320         case 2:
 321                 if (fab_opt == 5)
 322                         puts("600 Mhz\n");
 323                 if (fab_opt == 9)
 324                         puts("400 Mhz\n");
 325                 break;
 326         case 3:
 327                 puts("667 Mhz\n");
 328                 break;
 329         case 4:
 330                 if (fab_opt == 5)
 331                         puts("750 Mhz\n");
 332                 if (fab_opt == 9)
 333                         puts("500 Mhz\n");
 334                 break;
 335         case 0xa:
 336                 puts("400 Mhz\n");
 337                 break;
 338         case 0xb:
 339                 if (fab_opt == 5)
 340                         puts("800 Mhz\n");
 341                 if (fab_opt == 9)
 342                         puts("553 Mhz\n");
 343                 if (fab_opt == 0xA)
 344                         puts("640 Mhz\n");
 345                 break;
 346 #endif
 347         default:
 348                 puts("NOT DEFINED FREQ\n");
 349         }
 350 }
 351
 352 static u32 ddr3_init_main(void)
 353 {
 354         u32 target_freq;
 355         u32 reg = 0;
 356         u32 cpu_freq, fab_opt, hclk_time_ps, soc_num;
 357         __maybe_unused u32 ecc = DRAM_ECC;
 358         __maybe_unused int dqs_clk_aligned = 0;
 359         __maybe_unused u32 scrub_offs, scrub_size;
 360         __maybe_unused u32 ddr_width = BUS_WIDTH;
 361         __maybe_unused int status;
 362         __maybe_unused u32 win_backup[16];
 363
 364         /* SoC/Board special Initializtions */
 365         fab_opt = ddr3_get_fab_opt();
 366
 367 #ifdef CONFIG_SPD_EEPROM
 368         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 369 #endif
 370
 371         ddr3_print_version();
 372         DEBUG_INIT_S("4\n");
 373         /* Lib version 5.5.4 */
 374
 375         fab_opt = ddr3_get_fab_opt();
 376
 377         /* Switching CPU to MRVL ID */
 378         soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >>
 379                 SAR1_CPU_CORE_OFFSET;
 380         switch (soc_num) {
 381         case 0x3:
 382                 reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
 383                 reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
 384         case 0x1:
 385                 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
 386         case 0x0:
 387                 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET);
 388         default:
 389                 break;
 390         }
 391
 392         /* Power down deskew PLL */
 393 #if !defined(MV88F672X)
 394         /* 0x18780 [25] */
 395         reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~(1 << 25));
 396         reg_write(REG_DDRPHY_APLL_CTRL_ADDR, reg);
 397 #endif
 398
 399         /*
 400          * Stage 0 - Set board configuration
 401          */
 402         cpu_freq = ddr3_get_cpu_freq();
 403         if (fab_opt > FAB_OPT)
 404                 fab_opt = FAB_OPT - 1;
 405
 406         if (ddr3_get_log_level() > 0)
 407                 print_ddr_target_freq(cpu_freq, fab_opt);
 408
 409 #if defined(MV88F672X)
 410         get_target_freq(cpu_freq, &target_freq, &hclk_time_ps);
 411 #else
 412         target_freq = cpu_ddr_ratios[fab_opt][cpu_freq];
 413         hclk_time_ps = cpu_fab_clk_to_hclk[fab_opt][cpu_freq];
 414 #endif
 415         if ((target_freq == 0) || (hclk_time_ps == 0)) {
 416                 DEBUG_INIT_S("DDR3 Training Sequence - FAILED - Wrong Sample at Reset Configurations\n");
 417                 if (target_freq == 0) {
 418                         DEBUG_INIT_C("target_freq", target_freq, 2);
 419                         DEBUG_INIT_C("fab_opt", fab_opt, 2);
 420                         DEBUG_INIT_C("cpu_freq", cpu_freq, 2);
 421                 } else if (hclk_time_ps == 0) {
 422                         DEBUG_INIT_C("hclk_time_ps", hclk_time_ps, 2);
 423                         DEBUG_INIT_C("fab_opt", fab_opt, 2);
 424                         DEBUG_INIT_C("cpu_freq", cpu_freq, 2);
 425                 }
 426
 427                 return MV_DDR3_TRAINING_ERR_BAD_SAR;
 428         }
 429
 430 #if defined(ECC_SUPPORT)
 431         scrub_offs = U_BOOT_START_ADDR;
 432         scrub_size = U_BOOT_SCRUB_SIZE;
 433 #else
 434         scrub_offs = 0;
 435         scrub_size = 0;
 436 #endif
 437
 438 #if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT)
 439         ecc = DRAM_ECC;
 440 #endif
 441
 442 #if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT)
 443         ecc = 0;
 444         if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_ECC))
 445                 ecc = 1;
 446 #endif
 447
 448 #ifdef DQS_CLK_ALIGNED
 449         dqs_clk_aligned = 1;
 450 #endif
 451
 452         /* Check if DRAM is already initialized  */
 453         if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
 454             (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
 455                 DEBUG_INIT_S("DDR3 Training Sequence - 2nd boot - Skip\n");
 456                 return MV_OK;
 457         }
 458
 459         /*
 460          * Stage 1 - Dunit Setup
 461          */
 462
 463 #ifdef DUNIT_STATIC
 464         /*
 465          * For Static D-Unit Setup use must set the correct static values
 466          * at the ddr3_*soc*_vars.h file
 467          */
 468         DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static MC Init\n");
 469         ddr3_static_mc_init();
 470
 471 #ifdef ECC_SUPPORT
 472         ecc = DRAM_ECC;
 473         if (ecc) {
 474                 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
 475                 reg |= (1 << REG_SDRAM_CONFIG_ECC_OFFS);
 476                 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
 477         }
 478 #endif
 479 #endif
 480
 481 #if defined(MV88F78X60) || defined(MV88F672X)
 482 #if defined(AUTO_DETECTION_SUPPORT)
 483         /*
 484          * Configurations for both static and dynamic MC setups
 485          *
 486          * Dynamically Set 32Bit and ECC for AXP (Relevant only for
 487          * Marvell DB boards)
 488          */
 489         if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_BUS_WIDTH)) {
 490                 ddr_width = 32;
 491                 DEBUG_INIT_S("DDR3 Training Sequence - DRAM bus width 32Bit\n");
 492         }
 493 #endif
 494
 495 #if defined(MV88F672X)
 496         reg = reg_read(REG_SDRAM_CONFIG_ADDR);
 497         if ((reg >> 15) & 1)
 498                 ddr_width = 32;
 499         else
 500                 ddr_width = 16;
 501 #endif
 502 #endif
 503
 504 #ifdef DUNIT_SPD
 505         status = ddr3_dunit_setup(ecc, hclk_time_ps, &ddr_width);
 506         if (MV_OK != status) {
 507                 DEBUG_INIT_S("DDR3 Training Sequence - FAILED (ddr3 Dunit Setup)\n");
 508                 return status;
 509         }
 510 #endif
 511
 512         /* Fix read ready phases for all SOC in reg 0x15C8 */
 513         reg = reg_read(REG_TRAINING_DEBUG_3_ADDR);
 514         reg &= ~(REG_TRAINING_DEBUG_3_MASK);
 515         reg |= 0x4;             /* Phase 0 */
 516         reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS);
 517         reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS));        /* Phase 1 */
 518         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS));
 519         reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS));        /* Phase 3 */
 520         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS));
 521         reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS));
 522         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS));
 523         reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS));
 524         reg_write(REG_TRAINING_DEBUG_3_ADDR, reg);
 525
 526 #if defined(MV88F672X)
 527         /*
 528          * AxiBrespMode[8] = Compliant,
 529          * AxiAddrDecodeCntrl[11] = Internal,
 530          * AxiDataBusWidth[0] = 128bit
 531          */
 532         /* 0x14A8 - AXI Control Register */
 533         reg_write(REG_DRAM_AXI_CTRL_ADDR, 0);
 534 #else
 535         /* 0x14A8 - AXI Control Register */
 536         reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000100);
 537         reg_write(REG_CDI_CONFIG_ADDR, 0x00000006);
 538
 539         if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) &
 540                                   (1 << REG_DDR_IO_CLK_RATIO_OFFS))) {
 541                 /* 0x14A8 - AXI Control Register */
 542                 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000101);
 543                 reg_write(REG_CDI_CONFIG_ADDR, 0x00000007);
 544         }
 545 #endif
 546
 547 #if !defined(MV88F67XX)
 548         /*
 549          * ARMADA-370 activate DLB later at the u-boot,
 550          * Armada38x - No DLB activation at this time
 551          */
 552         reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x18C01E);
 553
 554 #if defined(MV88F78X60)
 555         /* WA according to eratta GL-8672902*/
 556         if (mv_ctrl_rev_get() == MV_78XX0_B0_REV)
 557                 reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0xc19e);
 558 #endif
 559
 560         reg_write(DLB_AGING_REGISTER, 0x0f7f007f);
 561         reg_write(DLB_EVICTION_CONTROL_REG, 0x0);
 562         reg_write(DLB_EVICTION_TIMERS_REGISTER_REG, 0x00FF3C1F);
 563
 564         reg_write(MBUS_UNITS_PRIORITY_CONTROL_REG, 0x55555555);
 565         reg_write(FABRIC_UNITS_PRIORITY_CONTROL_REG, 0xAA);
 566         reg_write(MBUS_UNITS_PREFETCH_CONTROL_REG, 0xffff);
 567         reg_write(FABRIC_UNITS_PREFETCH_CONTROL_REG, 0xf0f);
 568
 569 #if defined(MV88F78X60)
 570         /* WA according to eratta GL-8672902 */
 571         if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) {
 572                 reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
 573                 reg |= DLB_ENABLE;
 574                 reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
 575         }
 576 #endif /* end defined(MV88F78X60) */
 577 #endif /* end !defined(MV88F67XX) */
 578
 579         if (ddr3_get_log_level() >= MV_LOG_LEVEL_1)
 580                 print_dunit_setup();
 581
 582         /*
 583          * Stage 2 - Training Values Setup
 584          */
 585 #ifdef STATIC_TRAINING
 586         /*
 587          * DRAM Init - After all the D-unit values are set, its time to init
 588          * the D-unit
 589          */
 590         /* Wait for '0' */
 591         reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);
 592         do {
 593                 reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
 594                         (1 << REG_SDRAM_INIT_CTRL_OFFS);
 595         } while (reg);
 596
 597         /* ddr3 init using static parameters - HW training is disabled */
 598         DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static Training Parameters\n");
 599         ddr3_static_training_init();
 600
 601 #if defined(MV88F78X60)
 602         /*
 603          * If ECC is enabled, need to scrub the U-Boot area memory region -
 604          * Run training function with Xor bypass just to scrub the memory
 605          */
 606         status = ddr3_hw_training(target_freq, ddr_width,
 607                                   1, scrub_offs, scrub_size,
 608                                   dqs_clk_aligned, DDR3_TRAINING_DEBUG,
 609                                   REG_DIMM_SKIP_WL);
 610         if (MV_OK != status) {
 611                 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");
 612                 return status;
 613         }
 614 #endif
 615 #else
 616         /* Set X-BAR windows for the training sequence */
 617         ddr3_save_and_set_training_windows(win_backup);
 618
 619         /* Run DDR3 Training Sequence */
 620         /* DRAM Init */
 621         reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);
 622         do {
 623                 reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
 624                         (1 << REG_SDRAM_INIT_CTRL_OFFS);
 625         } while (reg);          /* Wait for '0' */
 626
 627         /* ddr3 init using DDR3 HW training procedure */
 628         DEBUG_INIT_FULL_S("DDR3 Training Sequence - HW Training Procedure\n");
 629         status = ddr3_hw_training(target_freq, ddr_width,
 630                                   0, scrub_offs, scrub_size,
 631                                   dqs_clk_aligned, DDR3_TRAINING_DEBUG,
 632                                   REG_DIMM_SKIP_WL);
 633         if (MV_OK != status) {
 634                 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");
 635                 return status;
 636         }
 637 #endif
 638
 639         /*
 640          * Stage 3 - Finish
 641          */
 642 #if defined(MV88F78X60) || defined(MV88F672X)
 643         /* Disable ECC Ignore bit */
 644         reg = reg_read(REG_SDRAM_CONFIG_ADDR) &
 645                 ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
 646         reg_write(REG_SDRAM_CONFIG_ADDR, reg);
 647 #endif
 648
 649 #if !defined(STATIC_TRAINING)
 650         /* Restore and set windows */
 651         ddr3_restore_and_set_final_windows(win_backup);
 652 #endif
 653
 654         /* Update DRAM init indication in bootROM register */
 655         reg = reg_read(REG_BOOTROM_ROUTINE_ADDR);
 656         reg_write(REG_BOOTROM_ROUTINE_ADDR,
 657                   reg | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS));
 658
 659 #if !defined(MV88F67XX)
 660 #if defined(MV88F78X60)
 661         if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) {
 662                 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
 663                 if (ecc == 0)
 664                         reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19));
 665         }
 666 #endif /* end defined(MV88F78X60) */
 667
 668         reg_write(DLB_EVICTION_CONTROL_REG, 0x9);
 669
 670         reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
 671         reg |= (DLB_ENABLE | DLB_WRITE_COALESING | DLB_AXI_PREFETCH_EN |
 672                 DLB_MBUS_PREFETCH_EN | PREFETCH_NLNSZTR);
 673         reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
 674 #endif /* end !defined(MV88F67XX) */
 675
 676 #ifdef STATIC_TRAINING
 677         DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully (S)\n");
 678 #else
 679         DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully\n");
 680 #endif
 681
 682         return MV_OK;
 683 }
 684
 685 /*
 686  * Name:     ddr3_get_cpu_freq
 687  * Desc:     read S@R and return CPU frequency
 688  * Args:
 689  * Notes:
 690  * Returns:  required value
 691  */
 692
 693 u32 ddr3_get_cpu_freq(void)
 694 {
 695         u32 reg, cpu_freq;
 696
 697 #if defined(MV88F672X)
 698         /* Read sample at reset setting */
 699         reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);     /* 0xE8200 */
 700         cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
 701                 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
 702 #else
 703         /* Read sample at reset setting */
 704         reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR);      /* 0x18230 [23:21] */
 705 #if defined(MV88F78X60)
 706         cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
 707                 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
 708         reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);     /* 0x18234 [20] */
 709         cpu_freq |= (((reg >> REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS) & 0x1) << 3);
 710 #elif defined(MV88F67XX)
 711         cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
 712                 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
 713 #endif
 714 #endif
 715
 716         return cpu_freq;
 717 }
 718
 719 /*
 720  * Name:     ddr3_get_fab_opt
 721  * Desc:     read S@R and return CPU frequency
 722  * Args:
 723  * Notes:
 724  * Returns:  required value
 725  */
 726 u32 ddr3_get_fab_opt(void)
 727 {
 728         __maybe_unused u32 reg, fab_opt;
 729
 730 #if defined(MV88F672X)
 731         return 0;               /* No fabric */
 732 #else
 733         /* Read sample at reset setting */
 734         reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR);
 735         fab_opt = (reg & REG_SAMPLE_RESET_FAB_MASK) >>
 736                 REG_SAMPLE_RESET_FAB_OFFS;
 737
 738 #if defined(MV88F78X60)
 739         reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);
 740         fab_opt |= (((reg >> 19) & 0x1) << 4);
 741 #endif
 742
 743         return fab_opt;
 744 #endif
 745 }
 746
 747 /*
 748  * Name:     ddr3_get_vco_freq
 749  * Desc:     read S@R and return VCO frequency
 750  * Args:
 751  * Notes:
 752  * Returns:  required value
 753  */
 754 u32 ddr3_get_vco_freq(void)
 755 {
 756         u32 fab, cpu_freq, ui_vco_freq;
 757
 758         fab = ddr3_get_fab_opt();
 759         cpu_freq = ddr3_get_cpu_freq();
 760
 761         if (fab == 2 || fab == 3 || fab == 7 || fab == 8 || fab == 10 ||
 762             fab == 15 || fab == 17 || fab == 20)
 763                 ui_vco_freq = cpu_freq + CLK_CPU;
 764         else
 765                 ui_vco_freq = cpu_freq;
 766
 767         return ui_vco_freq;
 768 }
 769
 770 #ifdef STATIC_TRAINING
 771 /*
 772  * Name:     ddr3_static_training_init - Init DDR3 Training with
 773  *           static parameters
 774  * Desc:     Use this routine to init the controller without the HW training
 775  *           procedure
 776  *           User must provide compatible header file with registers data.
 777  * Args:     None.
 778  * Notes:
 779  * Returns:  None.
 780  */
 781 void ddr3_static_training_init(void)
 782 {
 783         MV_DRAM_MODES *ddr_mode;
 784         u32 reg;
 785         int j;
 786
 787         ddr_mode = ddr3_get_static_ddr_mode();
 788
 789         j = 0;
 790         while (ddr_mode->vals[j].reg_addr != 0) {
 791                 udelay(10);     /* haim want to delay each write */
 792                 reg_write(ddr_mode->vals[j].reg_addr,
 793                           ddr_mode->vals[j].reg_value);
 794
 795                 if (ddr_mode->vals[j].reg_addr ==
 796                     REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
 797                         do {
 798                                 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
 799                                         REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
 800                         } while (reg);
 801                 j++;
 802         }
 803 }
 804 #endif
 805
 806 /*
 807  * Name:     ddr3_get_static_mc_value - Init Memory controller with static
 808  *           parameters
 809  * Desc:     Use this routine to init the controller without the HW training
 810  *           procedure
 811  *           User must provide compatible header file with registers data.
 812  * Args:     None.
 813  * Notes:
 814  * Returns:  None.
 815  */
 816 u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2,
 817                              u32 mask2)
 818 {
 819         u32 reg, tmp;
 820
 821         reg = reg_read(reg_addr);
 822
 823         tmp = (reg >> offset1) & mask1;
 824         if (mask2)
 825                 tmp |= (reg >> offset2) & mask2;
 826
 827         return tmp;
 828 }
 829
 830 /*
 831  * Name:     ddr3_get_static_ddr_mode - Init Memory controller with static
 832  *           parameters
 833  * Desc:     Use this routine to init the controller without the HW training
 834  *           procedure
 835  *           User must provide compatible header file with registers data.
 836  * Args:     None.
 837  * Notes:
 838  * Returns:  None.
 839  */
 840 __weak MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
 841 {
 842         u32 chip_board_rev, i;
 843         u32 size;
 844
 845         /* Do not modify this code. relevant only for marvell Boards */
 846 #if defined(DB_78X60_PCAC)
 847         chip_board_rev = Z1_PCAC;
 848 #elif defined(DB_78X60_AMC)
 849         chip_board_rev = A0_AMC;
 850 #elif defined(DB_88F6710_PCAC)
 851         chip_board_rev = A0_PCAC;
 852 #elif defined(RD_88F6710)
 853         chip_board_rev = A0_RD;
 854 #elif defined(MV88F672X)
 855         chip_board_rev = mv_board_id_get();
 856 #else
 857         chip_board_rev = A0;
 858 #endif
 859
 860         size = sizeof(ddr_modes) / sizeof(MV_DRAM_MODES);
 861         for (i = 0; i < size; i++) {
 862                 if ((ddr3_get_cpu_freq() == ddr_modes[i].cpu_freq) &&
 863                     (ddr3_get_fab_opt() == ddr_modes[i].fab_freq) &&
 864                     (chip_board_rev == ddr_modes[i].chip_board_rev))
 865                         return &ddr_modes[i];
 866         }
 867
 868         return &ddr_modes[0];
 869 }
 870
 871 #ifdef DUNIT_STATIC
 872 /*
 873  * Name:     ddr3_static_mc_init - Init Memory controller with static parameters
 874  * Desc:     Use this routine to init the controller without the HW training
 875  *           procedure
 876  *           User must provide compatible header file with registers data.
 877  * Args:     None.
 878  * Notes:
 879  * Returns:  None.
 880  */
 881 void ddr3_static_mc_init(void)
 882 {
 883         MV_DRAM_MODES *ddr_mode;
 884         u32 reg;
 885         int j;
 886
 887         ddr_mode = ddr3_get_static_ddr_mode();
 888         j = 0;
 889         while (ddr_mode->regs[j].reg_addr != 0) {
 890                 reg_write(ddr_mode->regs[j].reg_addr,
 891                           ddr_mode->regs[j].reg_value);
 892                 if (ddr_mode->regs[j].reg_addr ==
 893                     REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
 894                         do {
 895                                 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
 896                                         REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
 897                         } while (reg);
 898                 j++;
 899         }
 900 }
 901 #endif
 902
 903 /*
 904  * Name:     ddr3_check_config - Check user configurations: ECC/MultiCS
 905  * Desc:
 906  * Args:     twsi Address
 907  * Notes:    Only Available for ArmadaXP/Armada 370 DB boards
 908  * Returns:  None.
 909  */
 910 int ddr3_check_config(u32 twsi_addr, MV_CONFIG_TYPE config_type)
 911 {
 912 #ifdef AUTO_DETECTION_SUPPORT
 913         u8 data = 0;
 914         int ret;
 915         int offset;
 916
 917         if ((config_type == CONFIG_ECC) || (config_type == CONFIG_BUS_WIDTH))
 918                 offset = 1;
 919         else
 920                 offset = 0;
 921
 922         ret = i2c_read(twsi_addr, offset, 1, (u8 *)&data, 1);
 923         if (!ret) {
 924                 switch (config_type) {
 925                 case CONFIG_ECC:
 926                         if (data & 0x2)
 927                                 return 1;
 928                         break;
 929                 case CONFIG_BUS_WIDTH:
 930                         if (data & 0x1)
 931                                 return 1;
 932                         break;
 933 #ifdef DB_88F6710
 934                 case CONFIG_MULTI_CS:
 935                         if (CFG_MULTI_CS_MODE(data))
 936                                 return 1;
 937                         break;
 938 #else
 939                 case CONFIG_MULTI_CS:
 940                         break;
 941 #endif
 942                 }
 943         }
 944 #endif
 945
 946         return 0;
 947 }
 948
 949 #if defined(DB_88F78X60_REV2)
 950 /*
 951  * Name:     ddr3_get_eprom_fabric - Get Fabric configuration from EPROM
 952  * Desc:
 953  * Args:     twsi Address
 954  * Notes:    Only Available for ArmadaXP DB Rev2 boards
 955  * Returns:  None.
 956  */
 957 u8 ddr3_get_eprom_fabric(void)
 958 {
 959 #ifdef AUTO_DETECTION_SUPPORT
 960         u8 data = 0;
 961         int ret;
 962
 963         ret = i2c_read(NEW_FABRIC_TWSI_ADDR, 1, 1, (u8 *)&data, 1);
 964         if (!ret)
 965                 return data & 0x1F;
 966 #endif
 967
 968         return 0;
 969 }
 970
 971 #endif
 972
 973 /*
 974  * Name:     ddr3_cl_to_valid_cl - this return register matching CL value
 975  * Desc:
 976  * Args:     clValue - the value
 977
 978  * Notes:
 979  * Returns:  required CL value
 980  */
 981 u32 ddr3_cl_to_valid_cl(u32 cl)
 982 {
 983         switch (cl) {
 984         case 5:
 985                 return 2;
 986                 break;
 987         case 6:
 988                 return 4;
 989                 break;
 990         case 7:
 991                 return 6;
 992                 break;
 993         case 8:
 994                 return 8;
 995                 break;
 996         case 9:
 997                 return 10;
 998                 break;
 999         case 10:
1000                 return 12;
1001                 break;
1002         case 11:
1003                 return 14;
1004                 break;
1005         case 12:
1006                 return 1;
1007                 break;
1008         case 13:
1009                 return 3;
1010                 break;
1011         case 14:
1012                 return 5;
1013                 break;
1014         default:
1015                 return 2;
1016         }
1017 }
1018
1019 /*
1020  * Name:     ddr3_cl_to_valid_cl - this return register matching CL value
1021  * Desc:
1022  * Args:     clValue - the value
1023  * Notes:
1024  * Returns:  required CL value
1025  */
1026 u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl)
1027 {
1028         switch (ui_valid_cl) {
1029         case 1:
1030                 return 12;
1031                 break;
1032         case 2:
1033                 return 5;
1034                 break;
1035         case 3:
1036                 return 13;
1037                 break;
1038         case 4:
1039                 return 6;
1040                 break;
1041         case 5:
1042                 return 14;
1043                 break;
1044         case 6:
1045                 return 7;
1046                 break;
1047         case 8:
1048                 return 8;
1049                 break;
1050         case 10:
1051                 return 9;
1052                 break;
1053         case 12:
1054                 return 10;
1055                 break;
1056         case 14:
1057                 return 11;
1058                 break;
1059         default:
1060                 return 0;
1061         }
1062 }
1063
1064 /*
1065  * Name:     ddr3_get_cs_num_from_reg
1066  * Desc:
1067  * Args:
1068  * Notes:
1069  * Returns:
1070  */
1071 u32 ddr3_get_cs_num_from_reg(void)
1072 {
1073         u32 cs_ena = ddr3_get_cs_ena_from_reg();
1074         u32 cs_count = 0;
1075         u32 cs;
1076
1077         for (cs = 0; cs < MAX_CS; cs++) {
1078                 if (cs_ena & (1 << cs))
1079                         cs_count++;
1080         }
1081
1082         return cs_count;
1083 }
1084
1085 /*
1086  * Name:     ddr3_get_cs_ena_from_reg
1087  * Desc:
1088  * Args:
1089  * Notes:
1090  * Returns:
1091  */
1092 u32 ddr3_get_cs_ena_from_reg(void)
1093 {
1094         return reg_read(REG_DDR3_RANK_CTRL_ADDR) &
1095                 REG_DDR3_RANK_CTRL_CS_ENA_MASK;
1096 }
1097
1098 /*
1099  * mv_ctrl_rev_get - Get Marvell controller device revision number
1100  *
1101  * DESCRIPTION:
1102  *       This function returns 8bit describing the device revision as defined
1103  *       in PCI Express Class Code and Revision ID Register.
1104  *
1105  * INPUT:
1106  *       None.
1107  *
1108  * OUTPUT:
1109  *       None.
1110  *
1111  * RETURN:
1112  *       8bit desscribing Marvell controller revision number
1113  *
1114  */
1115 #if !defined(MV88F672X)
1116 u8 mv_ctrl_rev_get(void)
1117 {
1118         u8 rev_num;
1119
1120 #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
1121         /* Check pex power state */
1122         u32 pex_power;
1123         pex_power = mv_ctrl_pwr_clck_get(PEX_UNIT_ID, 0);
1124         if (pex_power == 0)
1125                 mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 1);
1126 #endif
1127         rev_num = (u8)reg_read(PEX_CFG_DIRECT_ACCESS(0,
1128                         PCI_CLASS_CODE_AND_REVISION_ID));
1129
1130 #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
1131         /* Return to power off state */
1132         if (pex_power == 0)
1133                 mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 0);
1134 #endif
1135
1136         return (rev_num & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS;
1137 }
1138
1139 #endif
1140
1141 #if defined(MV88F672X)
1142 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps)
1143 {
1144         u32 tmp, hclk;
1145
1146         switch (freq_mode) {
1147         case CPU_333MHz_DDR_167MHz_L2_167MHz:
1148                 hclk = 84;
1149                 tmp = DDR_100;
1150                 break;
1151         case CPU_266MHz_DDR_266MHz_L2_133MHz:
1152         case CPU_333MHz_DDR_222MHz_L2_167MHz:
1153         case CPU_400MHz_DDR_200MHz_L2_200MHz:
1154         case CPU_400MHz_DDR_267MHz_L2_200MHz:
1155         case CPU_533MHz_DDR_267MHz_L2_267MHz:
1156         case CPU_500MHz_DDR_250MHz_L2_250MHz:
1157         case CPU_600MHz_DDR_300MHz_L2_300MHz:
1158         case CPU_800MHz_DDR_267MHz_L2_400MHz:
1159         case CPU_900MHz_DDR_300MHz_L2_450MHz:
1160                 tmp = DDR_300;
1161                 hclk = 150;
1162                 break;
1163         case CPU_333MHz_DDR_333MHz_L2_167MHz:
1164         case CPU_500MHz_DDR_334MHz_L2_250MHz:
1165         case CPU_666MHz_DDR_333MHz_L2_333MHz:
1166                 tmp = DDR_333;
1167                 hclk = 165;
1168                 break;
1169         case CPU_533MHz_DDR_356MHz_L2_267MHz:
1170                 tmp = DDR_360;
1171                 hclk = 180;
1172                 break;
1173         case CPU_400MHz_DDR_400MHz_L2_200MHz:
1174         case CPU_600MHz_DDR_400MHz_L2_300MHz:
1175         case CPU_800MHz_DDR_400MHz_L2_400MHz:
1176         case CPU_400MHz_DDR_400MHz_L2_400MHz:
1177                 tmp = DDR_400;
1178                 hclk = 200;
1179                 break;
1180         case CPU_666MHz_DDR_444MHz_L2_333MHz:
1181         case CPU_900MHz_DDR_450MHz_L2_450MHz:
1182                 tmp = DDR_444;
1183                 hclk = 222;
1184                 break;
1185         case CPU_500MHz_DDR_500MHz_L2_250MHz:
1186         case CPU_1000MHz_DDR_500MHz_L2_500MHz:
1187         case CPU_1000MHz_DDR_500MHz_L2_333MHz:
1188                 tmp = DDR_500;
1189                 hclk = 250;
1190                 break;
1191         case CPU_533MHz_DDR_533MHz_L2_267MHz:
1192         case CPU_800MHz_DDR_534MHz_L2_400MHz:
1193         case CPU_1100MHz_DDR_550MHz_L2_550MHz:
1194                 tmp = DDR_533;
1195                 hclk = 267;
1196                 break;
1197         case CPU_600MHz_DDR_600MHz_L2_300MHz:
1198         case CPU_900MHz_DDR_600MHz_L2_450MHz:
1199         case CPU_1200MHz_DDR_600MHz_L2_600MHz:
1200                 tmp = DDR_600;
1201                 hclk = 300;
1202                 break;
1203         case CPU_666MHz_DDR_666MHz_L2_333MHz:
1204         case CPU_1000MHz_DDR_667MHz_L2_500MHz:
1205                 tmp = DDR_666;
1206                 hclk = 333;
1207                 break;
1208         default:
1209                 *ddr_freq = 0;
1210                 *hclk_ps = 0;
1211                 break;
1212         }
1213
1214         *ddr_freq = tmp;                /* DDR freq define */
1215         *hclk_ps = 1000000 / hclk;      /* values are 1/HCLK in ps */
1216
1217         return;
1218 }
1219 #endif