3 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <stratixII.h>
19 /* Define FPGA_DEBUG to 1 to get debug printf's */
22 static int altera_validate(Altera_desc *desc, const char *fn)
25 printf("%s: NULL descriptor!\n", fn);
29 if ((desc->family < min_altera_type) ||
30 (desc->family > max_altera_type)) {
31 printf("%s: Invalid family type, %d\n", fn, desc->family);
35 if ((desc->iface < min_altera_iface_type) ||
36 (desc->iface > max_altera_iface_type)) {
37 printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
42 printf("%s: NULL part size\n", fn);
49 /* ------------------------------------------------------------------------- */
50 int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
52 int ret_val = FPGA_FAIL; /* assume a failure */
54 if (altera_validate(desc, (char *)__func__)) {
55 printf("%s: Invalid device descriptor\n", __func__);
59 switch (desc->family) {
62 #if defined(CONFIG_FPGA_ACEX1K)
63 debug_cond(FPGA_DEBUG,
64 "%s: Launching the ACEX1K Loader...\n",
66 ret_val = ACEX1K_load (desc, buf, bsize);
67 #elif defined(CONFIG_FPGA_CYCLON2)
68 debug_cond(FPGA_DEBUG,
69 "%s: Launching the CYCLONE II Loader...\n",
71 ret_val = CYC2_load (desc, buf, bsize);
73 printf("%s: No support for ACEX1K devices.\n",
78 #if defined(CONFIG_FPGA_STRATIX_II)
79 case Altera_StratixII:
80 debug_cond(FPGA_DEBUG,
81 "%s: Launching the Stratix II Loader...\n",
83 ret_val = StratixII_load (desc, buf, bsize);
87 printf("%s: Unsupported family type, %d\n",
88 __func__, desc->family);
94 int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
96 int ret_val = FPGA_FAIL; /* assume a failure */
98 if (altera_validate(desc, (char *)__func__)) {
99 printf("%s: Invalid device descriptor\n", __func__);
103 switch (desc->family) {
105 #if defined(CONFIG_FPGA_ACEX)
106 debug_cond(FPGA_DEBUG,
107 "%s: Launching the ACEX1K Reader...\n",
109 ret_val = ACEX1K_dump (desc, buf, bsize);
111 printf("%s: No support for ACEX1K devices.\n",
116 #if defined(CONFIG_FPGA_STRATIX_II)
117 case Altera_StratixII:
118 debug_cond(FPGA_DEBUG,
119 "%s: Launching the Stratix II Reader...\n",
121 ret_val = StratixII_dump (desc, buf, bsize);
125 printf("%s: Unsupported family type, %d\n",
126 __func__, desc->family);
132 int altera_info(Altera_desc *desc)
134 int ret_val = FPGA_FAIL;
136 if (altera_validate (desc, (char *)__func__)) {
137 printf("%s: Invalid device descriptor\n", __func__);
141 printf("Family: \t");
142 switch (desc->family) {
147 printf("CYCLON II\n");
149 case Altera_StratixII:
150 printf("Stratix II\n");
152 /* Add new family types here */
154 printf("Unknown family type, %d\n", desc->family);
157 printf("Interface type:\t");
158 switch (desc->iface) {
160 printf("Passive Serial (PS)\n");
162 case passive_parallel_synchronous:
163 printf("Passive Parallel Synchronous (PPS)\n");
165 case passive_parallel_asynchronous:
166 printf("Passive Parallel Asynchronous (PPA)\n");
168 case passive_serial_asynchronous:
169 printf("Passive Serial Asynchronous (PSA)\n");
171 case altera_jtag_mode: /* Not used */
172 printf("JTAG Mode\n");
174 case fast_passive_parallel:
175 printf("Fast Passive Parallel (FPP)\n");
177 case fast_passive_parallel_security:
178 printf("Fast Passive Parallel with Security (FPPS)\n");
180 /* Add new interface types here */
182 printf("Unsupported interface type, %d\n", desc->iface);
185 printf("Device Size: \t%zd bytes\n"
186 "Cookie: \t0x%x (%d)\n",
187 desc->size, desc->cookie, desc->cookie);
189 if (desc->iface_fns) {
190 printf("Device Function Table @ 0x%p\n", desc->iface_fns);
191 switch (desc->family) {
194 #if defined(CONFIG_FPGA_ACEX1K)
196 #elif defined(CONFIG_FPGA_CYCLON2)
200 printf("%s: No support for ACEX1K devices.\n",
204 #if defined(CONFIG_FPGA_STRATIX_II)
205 case Altera_StratixII:
206 StratixII_info(desc);
209 /* Add new family types here */
211 /* we don't need a message here - we give one up above */
215 printf("No Device Function Table.\n");
218 ret_val = FPGA_SUCCESS;