2 * Copyright (c) 2012 The Chromium OS Authors.
3 * SPDX-License-Identifier: GPL-2.0+
7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
8 * through the PCI bus. Each PCI device has 256 bytes of configuration space,
9 * consisting of a standard header and a device-specific set of registers. PCI
10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
11 * other things). Within the PCI configuration space, the GPIOBASE register
12 * tells us where in the device's I/O region we can find more registers to
13 * actually access the GPIOs.
15 * PCI bus/device/function 0:1f:0 => PCI config registers
16 * PCI config register "GPIOBASE"
17 * PCI I/O space + [GPIOBASE] => start of GPIO registers
18 * GPIO registers => gpio pin function, direction, value
21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
22 * ICH versions have more, but the decoding the matrix that describes them is
23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
24 * but they will ONLY work for certain unspecified chipsets because the offset
25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
26 * reserved or subject to arcane restrictions.
37 #ifdef CONFIG_X86_RESET_VECTOR
38 #include <asm/arch/pch.h>
39 #define SUPPORT_GPIO_SETUP
42 #define GPIO_PER_BANK 32
44 /* Where in config space is the register that points to the GPIO registers? */
45 #define PCI_CFG_GPIOBASE 0x48
47 struct ich6_bank_priv {
48 /* These are I/O addresses */
54 #ifdef SUPPORT_GPIO_SETUP
55 static void setup_pch_gpios(const struct pch_gpio_map *gpio)
57 u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
61 outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
63 outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
64 if (gpio->set1.direction)
65 outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
67 outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
68 if (gpio->set1.invert)
69 outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
71 outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
75 outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
77 outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
78 if (gpio->set2.direction)
79 outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
81 outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
85 outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
87 outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
88 if (gpio->set3.direction)
89 outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
91 outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
94 /* TODO: Move this to device tree, or platform data */
95 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
97 gd->arch.gpio_map = map;
99 #endif /* SUPPORT_GPIO_SETUP */
101 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
103 struct ich6_bank_platdata *plat = dev_get_platdata(dev);
104 pci_dev_t pci_dev; /* handle for 0:1f:0 */
111 /* Where should it be? */
112 pci_dev = PCI_BDF(0, 0x1f, 0);
114 /* Is the device present? */
115 tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID);
116 if (tmpword != PCI_VENDOR_ID_INTEL) {
117 debug("%s: wrong VendorID\n", __func__);
121 tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID);
122 debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
124 * We'd like to validate the Device ID too, but pretty much any
125 * value is either a) correct with slight differences, or b)
126 * correct but undocumented. We'll have to check a bunch of other
130 /* I/O should already be enabled (it's a RO bit). */
131 tmpword = pci_read_config16(pci_dev, PCI_COMMAND);
132 if (!(tmpword & PCI_COMMAND_IO)) {
133 debug("%s: device IO not enabled\n", __func__);
137 /* Header Type must be normal (bits 6-0 only; see spec.) */
138 tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE);
139 if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
140 debug("%s: invalid Header type\n", __func__);
144 /* Base Class must be a bridge device */
145 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE);
146 if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
147 debug("%s: invalid class\n", __func__);
150 /* Sub Class must be ISA */
151 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE);
152 if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
153 debug("%s: invalid subclass\n", __func__);
157 /* Programming Interface must be 0x00 (no others exist) */
158 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG);
159 if (tmpbyte != 0x00) {
160 debug("%s: invalid interface type\n", __func__);
165 * GPIOBASE moved to its current offset with ICH6, but prior to
166 * that it was unused (or undocumented). Check that it looks
167 * okay: not all ones or zeros, and mapped to I/O space (bit 0).
169 tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
170 if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
171 !(tmplong & 0x00000001)) {
172 debug("%s: unexpected GPIOBASE value\n", __func__);
177 * Okay, I guess we're looking at the right device. The actual
178 * GPIO registers are in the PCI device's I/O space, starting
179 * at the offset that we just read. Bit 0 indicates that it's
180 * an I/O address, not a memory address, so mask that off.
182 gpiobase = tmplong & 0xfffffffe;
183 offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
185 debug("%s: Invalid register offset %d\n", __func__, offset);
188 plat->base_addr = gpiobase + offset;
189 plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
195 static int ich6_gpio_probe(struct udevice *dev)
197 struct ich6_bank_platdata *plat = dev_get_platdata(dev);
198 struct gpio_dev_priv *uc_priv = dev->uclass_priv;
199 struct ich6_bank_priv *bank = dev_get_priv(dev);
201 #ifdef SUPPORT_GPIO_SETUP
202 if (gd->arch.gpio_map) {
203 setup_pch_gpios(gd->arch.gpio_map);
204 gd->arch.gpio_map = NULL;
207 uc_priv->gpio_count = GPIO_PER_BANK;
208 uc_priv->bank_name = plat->bank_name;
209 bank->use_sel = plat->base_addr;
210 bank->io_sel = plat->base_addr + 4;
211 bank->lvl = plat->base_addr + 8;
216 static int ich6_gpio_request(struct udevice *dev, unsigned offset,
219 struct ich6_bank_priv *bank = dev_get_priv(dev);
223 * Make sure that the GPIO pin we want isn't already in use for some
224 * built-in hardware function. We have to check this for every
227 tmplong = inl(bank->use_sel);
228 if (!(tmplong & (1UL << offset))) {
229 debug("%s: gpio %d is reserved for internal use\n", __func__,
237 static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
239 struct ich6_bank_priv *bank = dev_get_priv(dev);
242 tmplong = inl(bank->io_sel);
243 tmplong |= (1UL << offset);
244 outl(bank->io_sel, tmplong);
248 static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
251 struct ich6_bank_priv *bank = dev_get_priv(dev);
254 tmplong = inl(bank->io_sel);
255 tmplong &= ~(1UL << offset);
256 outl(bank->io_sel, tmplong);
260 static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
263 struct ich6_bank_priv *bank = dev_get_priv(dev);
267 tmplong = inl(bank->lvl);
268 r = (tmplong & (1UL << offset)) ? 1 : 0;
272 static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
275 struct ich6_bank_priv *bank = dev_get_priv(dev);
278 tmplong = inl(bank->lvl);
280 tmplong |= (1UL << offset);
282 tmplong &= ~(1UL << offset);
283 outl(bank->lvl, tmplong);
287 static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
289 struct ich6_bank_priv *bank = dev_get_priv(dev);
290 u32 mask = 1UL << offset;
292 if (!(inl(bank->use_sel) & mask))
294 if (inl(bank->io_sel) & mask)
300 static const struct dm_gpio_ops gpio_ich6_ops = {
301 .request = ich6_gpio_request,
302 .direction_input = ich6_gpio_direction_input,
303 .direction_output = ich6_gpio_direction_output,
304 .get_value = ich6_gpio_get_value,
305 .set_value = ich6_gpio_set_value,
306 .get_function = ich6_gpio_get_function,
309 static const struct udevice_id intel_ich6_gpio_ids[] = {
310 { .compatible = "intel,ich6-gpio" },
314 U_BOOT_DRIVER(gpio_ich6) = {
317 .of_match = intel_ich6_gpio_ids,
318 .ops = &gpio_ich6_ops,
319 .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
320 .probe = ich6_gpio_probe,
321 .priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
322 .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),