2 * NVIDIA Tegra20 GPIO handling.
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
11 * Tom Warren (twarren@nvidia.com)
20 #include <asm/bitops.h>
21 #include <asm/arch/tegra.h>
23 #include <dm/device-internal.h>
24 #include <dt-bindings/gpio/gpio.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 struct tegra_gpio_platdata {
29 struct gpio_ctlr_bank *bank;
30 const char *port_name; /* Name of port, e.g. "B" */
31 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
34 /* Information about each port at run-time */
35 struct tegra_port_info {
36 struct gpio_ctlr_bank *bank;
37 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
40 /* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
41 static int get_config(unsigned gpio)
43 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
44 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
48 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
49 type = (u >> GPIO_BIT(gpio)) & 1;
51 debug("get_config: port = %d, bit = %d is %s\n",
52 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
57 /* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
58 static void set_config(unsigned gpio, int type)
60 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
61 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
64 debug("set_config: port = %d, bit = %d, %s\n",
65 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
67 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
69 u |= 1 << GPIO_BIT(gpio);
71 u &= ~(1 << GPIO_BIT(gpio));
72 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
75 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
76 static int get_direction(unsigned gpio)
78 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
79 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
83 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
84 dir = (u >> GPIO_BIT(gpio)) & 1;
86 debug("get_direction: port = %d, bit = %d, %s\n",
87 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
92 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
93 static void set_direction(unsigned gpio, int output)
95 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
96 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
99 debug("set_direction: port = %d, bit = %d, %s\n",
100 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
102 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
104 u |= 1 << GPIO_BIT(gpio);
106 u &= ~(1 << GPIO_BIT(gpio));
107 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
110 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
111 static void set_level(unsigned gpio, int high)
113 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
114 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
117 debug("set_level: port = %d, bit %d == %d\n",
118 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
120 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
122 u |= 1 << GPIO_BIT(gpio);
124 u &= ~(1 << GPIO_BIT(gpio));
125 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
129 * Generic_GPIO primitives.
132 /* set GPIO pin 'gpio' as an input */
133 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
135 struct tegra_port_info *state = dev_get_priv(dev);
137 /* Configure GPIO direction as input. */
138 set_direction(state->base_gpio + offset, 0);
140 /* Enable the pin as a GPIO */
141 set_config(state->base_gpio + offset, 1);
146 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
147 static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
150 struct tegra_port_info *state = dev_get_priv(dev);
151 int gpio = state->base_gpio + offset;
153 /* Configure GPIO output value. */
154 set_level(gpio, value);
156 /* Configure GPIO direction as output. */
157 set_direction(gpio, 1);
159 /* Enable the pin as a GPIO */
160 set_config(state->base_gpio + offset, 1);
165 /* read GPIO IN value of pin 'gpio' */
166 static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
168 struct tegra_port_info *state = dev_get_priv(dev);
169 int gpio = state->base_gpio + offset;
172 debug("%s: pin = %d (port %d:bit %d)\n", __func__,
173 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
175 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
177 return (val >> GPIO_BIT(gpio)) & 1;
180 /* write GPIO OUT value to pin 'gpio' */
181 static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
183 struct tegra_port_info *state = dev_get_priv(dev);
184 int gpio = state->base_gpio + offset;
186 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
187 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
189 /* Configure GPIO output value. */
190 set_level(gpio, value);
195 void gpio_config_table(const struct tegra_gpio_config *config, int len)
199 for (i = 0; i < len; i++) {
200 switch (config[i].init) {
201 case TEGRA_GPIO_INIT_IN:
202 set_direction(config[i].gpio, 0);
204 case TEGRA_GPIO_INIT_OUT0:
205 set_level(config[i].gpio, 0);
206 set_direction(config[i].gpio, 1);
208 case TEGRA_GPIO_INIT_OUT1:
209 set_level(config[i].gpio, 1);
210 set_direction(config[i].gpio, 1);
213 set_config(config[i].gpio, 1);
217 static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
219 struct tegra_port_info *state = dev_get_priv(dev);
220 int gpio = state->base_gpio + offset;
222 if (!get_config(gpio))
224 else if (get_direction(gpio))
230 static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
231 struct fdtdec_phandle_args *args)
235 gpio = args->args[0];
236 port = gpio / TEGRA_GPIOS_PER_PORT;
237 ret = device_get_child(dev, port, &desc->dev);
240 desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
241 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
246 static const struct dm_gpio_ops gpio_tegra_ops = {
247 .direction_input = tegra_gpio_direction_input,
248 .direction_output = tegra_gpio_direction_output,
249 .get_value = tegra_gpio_get_value,
250 .set_value = tegra_gpio_set_value,
251 .get_function = tegra_gpio_get_function,
252 .xlate = tegra_gpio_xlate,
256 * Returns the name of a GPIO port
258 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
260 * @base_port: Base port number (0, 1..n-1)
261 * @return allocated string containing the name
263 static char *gpio_port_name(int base_port)
270 *s++ = 'A' + (base_port % 26);
279 static const struct udevice_id tegra_gpio_ids[] = {
280 { .compatible = "nvidia,tegra30-gpio" },
281 { .compatible = "nvidia,tegra20-gpio" },
285 static int gpio_tegra_probe(struct udevice *dev)
287 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
288 struct tegra_port_info *priv = dev->priv;
289 struct tegra_gpio_platdata *plat = dev->platdata;
291 /* Only child devices have ports */
295 priv->bank = plat->bank;
296 priv->base_gpio = plat->base_gpio;
298 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
299 uc_priv->bank_name = plat->port_name;
305 * We have a top-level GPIO device with no actual GPIOs. It has a child
306 * device for each Tegra port.
308 static int gpio_tegra_bind(struct udevice *parent)
310 struct tegra_gpio_platdata *plat = parent->platdata;
311 struct gpio_ctlr *ctlr;
316 /* If this is a child device, there is nothing to do here */
320 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
321 #ifdef CONFIG_SPL_BUILD
322 ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
323 bank_count = TEGRA_GPIO_BANKS;
329 * This driver does not make use of interrupts, other than to figure
330 * out the number of GPIO banks
332 if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len))
334 bank_count = len / 3 / sizeof(u32);
335 ctlr = (struct gpio_ctlr *)dev_get_addr(parent);
338 for (bank = 0; bank < bank_count; bank++) {
341 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
342 struct tegra_gpio_platdata *plat;
346 plat = calloc(1, sizeof(*plat));
349 plat->bank = &ctlr->gpio_bank[bank];
350 base_port = bank * TEGRA_PORTS_PER_BANK + port;
351 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
352 plat->port_name = gpio_port_name(base_port);
354 ret = device_bind(parent, parent->driver,
355 plat->port_name, plat, -1, &dev);
358 dev->of_offset = parent->of_offset;
365 U_BOOT_DRIVER(gpio_tegra) = {
366 .name = "gpio_tegra",
368 .of_match = tegra_gpio_ids,
369 .bind = gpio_tegra_bind,
370 .probe = gpio_tegra_probe,
371 .priv_auto_alloc_size = sizeof(struct tegra_port_info),
372 .ops = &gpio_tegra_ops,
373 .flags = DM_FLAG_PRE_RELOC,