2 * Xilinx Zynq GPIO device driver
4 * Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu>
6 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
7 * Copyright (C) 2009 - 2014 Xilinx, Inc.
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/errno.h>
19 DECLARE_GLOBAL_DATA_PTR;
22 #define ZYNQ_GPIO_MAX_BANK 4
24 #define ZYNQ_GPIO_BANK0_NGPIO 32
25 #define ZYNQ_GPIO_BANK1_NGPIO 22
26 #define ZYNQ_GPIO_BANK2_NGPIO 32
27 #define ZYNQ_GPIO_BANK3_NGPIO 32
29 #define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
30 ZYNQ_GPIO_BANK1_NGPIO + \
31 ZYNQ_GPIO_BANK2_NGPIO + \
32 ZYNQ_GPIO_BANK3_NGPIO)
34 #define ZYNQ_GPIO_BANK0_PIN_MIN 0
35 #define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
36 ZYNQ_GPIO_BANK0_NGPIO - 1)
37 #define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
38 #define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
39 ZYNQ_GPIO_BANK1_NGPIO - 1)
40 #define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
41 #define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
42 ZYNQ_GPIO_BANK2_NGPIO - 1)
43 #define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
44 #define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
45 ZYNQ_GPIO_BANK3_NGPIO - 1)
47 /* Register offsets for the GPIO device */
48 /* LSW Mask & Data -WO */
49 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
50 /* MSW Mask & Data -WO */
51 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
52 /* Data Register-RW */
53 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
54 /* Direction mode reg-RW */
55 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
56 /* Output enable reg-RW */
57 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
58 /* Interrupt mask reg-RO */
59 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
60 /* Interrupt enable reg-WO */
61 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
62 /* Interrupt disable reg-WO */
63 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
64 /* Interrupt status reg-RO */
65 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
66 /* Interrupt type reg-RW */
67 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
68 /* Interrupt polarity reg-RW */
69 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
70 /* Interrupt on any, reg-RW */
71 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
73 /* Disable all interrupts mask */
74 #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
76 /* Mid pin number of a bank */
77 #define ZYNQ_GPIO_MID_PIN_NUM 16
79 /* GPIO upper 16 bit mask */
80 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
82 struct zynq_gpio_privdata {
87 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
88 * for a given pin in the GPIO device
89 * @pin_num: gpio pin number within the device
90 * @bank_num: an output parameter used to return the bank number of the gpio
92 * @bank_pin_num: an output parameter used to return pin number within a bank
93 * for the given gpio pin
95 * Returns the bank number and pin offset within the bank.
97 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
98 unsigned int *bank_num,
99 unsigned int *bank_pin_num)
102 case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
104 *bank_pin_num = pin_num;
106 case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
108 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
110 case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
112 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
114 case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
116 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
119 printf("invalid GPIO pin number: %u\n", pin_num);
126 static int gpio_is_valid(unsigned gpio)
128 return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS);
131 static int check_gpio(unsigned gpio)
133 if (!gpio_is_valid(gpio)) {
134 printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
140 static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
143 unsigned int bank_num, bank_pin_num;
144 struct zynq_gpio_privdata *priv = dev_get_priv(dev);
146 if (check_gpio(gpio) < 0)
149 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
151 data = readl(priv->base +
152 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
154 return (data >> bank_pin_num) & 1;
157 static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
159 unsigned int reg_offset, bank_num, bank_pin_num;
160 struct zynq_gpio_privdata *priv = dev_get_priv(dev);
162 if (check_gpio(gpio) < 0)
165 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
167 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
168 /* only 16 data bits in bit maskable reg */
169 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
170 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
172 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
176 * get the 32 bit value to be written to the mask/data register where
177 * the upper 16 bits is the mask and lower 16 bits is the data
180 value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
181 ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
183 writel(value, priv->base + reg_offset);
188 static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
191 unsigned int bank_num, bank_pin_num;
192 struct zynq_gpio_privdata *priv = dev_get_priv(dev);
194 if (check_gpio(gpio) < 0)
197 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
199 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
200 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
203 /* clear the bit in direction mode reg to set the pin as input */
204 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
205 reg &= ~BIT(bank_pin_num);
206 writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
211 static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
215 unsigned int bank_num, bank_pin_num;
216 struct zynq_gpio_privdata *priv = dev_get_priv(dev);
218 if (check_gpio(gpio) < 0)
221 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
223 /* set the GPIO pin as output */
224 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
225 reg |= BIT(bank_pin_num);
226 writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
228 /* configure the output enable reg for the pin */
229 reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
230 reg |= BIT(bank_pin_num);
231 writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
233 /* set the state of the pin */
234 gpio_set_value(gpio, value);
238 static const struct dm_gpio_ops gpio_zynq_ops = {
239 .direction_input = zynq_gpio_direction_input,
240 .direction_output = zynq_gpio_direction_output,
241 .get_value = zynq_gpio_get_value,
242 .set_value = zynq_gpio_set_value,
245 static int zynq_gpio_probe(struct udevice *dev)
247 struct zynq_gpio_privdata *priv = dev_get_priv(dev);
249 priv->base = dev_get_addr(dev);
254 static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
256 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
258 uc_priv->gpio_count = ZYNQ_GPIO_NR_GPIOS;
263 static const struct udevice_id zynq_gpio_ids[] = {
264 { .compatible = "xlnx,zynq-gpio-1.0" },
268 U_BOOT_DRIVER(gpio_zynq) = {
271 .ops = &gpio_zynq_ops,
272 .of_match = zynq_gpio_ids,
273 .ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
274 .probe = zynq_gpio_probe,
275 .priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata),