git.sur5r.net Git - u-boot/blob - drivers/i2c/bfin-twi_i2c.c

   1 /*
   2  * i2c.c - driver for Blackfin on-chip TWI/I2C
   3  *
   4  * Copyright (c) 2006-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <common.h>
  10 #include <i2c.h>
  11
  12 #include <asm/blackfin.h>
  13 #include <asm/mach-common/bits/twi.h>
  14
  15 #ifdef DEBUG
  16 # define dmemset(s, c, n) memset(s, c, n)
  17 #else
  18 # define dmemset(s, c, n)
  19 #endif
  20 #define debugi(fmt, args...) \
  21         debug( \
  22                 "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t" \
  23                 "%-20s:%-3i: " fmt "\n", \
  24                 bfin_read_TWI_MASTER_STAT(), bfin_read_TWI_FIFO_STAT(), bfin_read_TWI_INT_STAT(), \
  25                 __func__, __LINE__, ## args)
  26
  27 #ifdef TWI0_CLKDIV
  28 #define bfin_write_TWI_CLKDIV(val)           bfin_write_TWI0_CLKDIV(val)
  29 #define bfin_write_TWI_CONTROL(val)          bfin_write_TWI0_CONTROL(val)
  30 #define bfin_read_TWI_CONTROL(val)           bfin_read_TWI0_CONTROL(val)
  31 #define bfin_write_TWI_MASTER_ADDR(val)      bfin_write_TWI0_MASTER_ADDR(val)
  32 #define bfin_write_TWI_XMT_DATA8(val)        bfin_write_TWI0_XMT_DATA8(val)
  33 #define bfin_read_TWI_RCV_DATA8()            bfin_read_TWI0_RCV_DATA8()
  34 #define bfin_read_TWI_INT_STAT()             bfin_read_TWI0_INT_STAT()
  35 #define bfin_write_TWI_INT_STAT(val)         bfin_write_TWI0_INT_STAT(val)
  36 #define bfin_read_TWI_MASTER_STAT()          bfin_read_TWI0_MASTER_STAT()
  37 #define bfin_write_TWI_MASTER_STAT(val)      bfin_write_TWI0_MASTER_STAT(val)
  38 #define bfin_read_TWI_MASTER_CTL()           bfin_read_TWI0_MASTER_CTL()
  39 #define bfin_write_TWI_MASTER_CTL(val)       bfin_write_TWI0_MASTER_CTL(val)
  40 #define bfin_write_TWI_INT_MASK(val)         bfin_write_TWI0_INT_MASK(val)
  41 #define bfin_write_TWI_FIFO_CTL(val)         bfin_write_TWI0_FIFO_CTL(val)
  42 #endif
  43
  44 #ifdef CONFIG_TWICLK_KHZ
  45 # error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
  46 #endif
  47 #if CONFIG_SYS_I2C_SPEED > 400000
  48 # error The Blackfin I2C hardware can only operate at 400KHz max
  49 #endif
  50
  51 /* All transfers are described by this data structure */
  52 struct i2c_msg {
  53         u8 flags;
  54 #define I2C_M_COMBO             0x4
  55 #define I2C_M_STOP              0x2
  56 #define I2C_M_READ              0x1
  57         int len;                /* msg length */
  58         u8 *buf;                /* pointer to msg data */
  59         int alen;               /* addr length */
  60         u8 *abuf;               /* addr buffer */
  61 };
  62
  63 /* Allow msec timeout per ~byte transfer */
  64 #define I2C_TIMEOUT 10
  65
  66 /**
  67  * wait_for_completion - manage the actual i2c transfer
  68  *      @msg: the i2c msg
  69  */
  70 static int wait_for_completion(struct i2c_msg *msg)
  71 {
  72         uint16_t int_stat;
  73         ulong timebase = get_timer(0);
  74
  75         do {
  76                 int_stat = bfin_read_TWI_INT_STAT();
  77
  78                 if (int_stat & XMTSERV) {
  79                         debugi("processing XMTSERV");
  80                         bfin_write_TWI_INT_STAT(XMTSERV);
  81                         SSYNC();
  82                         if (msg->alen) {
  83                                 bfin_write_TWI_XMT_DATA8(*(msg->abuf++));
  84                                 --msg->alen;
  85                         } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
  86                                 bfin_write_TWI_XMT_DATA8(*(msg->buf++));
  87                                 --msg->len;
  88                         } else {
  89                                 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() |
  90                                         (msg->flags & I2C_M_COMBO ? RSTART | MDIR : STOP));
  91                                 SSYNC();
  92                         }
  93                 }
  94                 if (int_stat & RCVSERV) {
  95                         debugi("processing RCVSERV");
  96                         bfin_write_TWI_INT_STAT(RCVSERV);
  97                         SSYNC();
  98                         if (msg->len) {
  99                                 *(msg->buf++) = bfin_read_TWI_RCV_DATA8();
 100                                 --msg->len;
 101                         } else if (msg->flags & I2C_M_STOP) {
 102                                 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | STOP);
 103                                 SSYNC();
 104                         }
 105                 }
 106                 if (int_stat & MERR) {
 107                         debugi("processing MERR");
 108                         bfin_write_TWI_INT_STAT(MERR);
 109                         SSYNC();
 110                         return msg->len;
 111                 }
 112                 if (int_stat & MCOMP) {
 113                         debugi("processing MCOMP");
 114                         bfin_write_TWI_INT_STAT(MCOMP);
 115                         SSYNC();
 116                         if (msg->flags & I2C_M_COMBO && msg->len) {
 117                                 bfin_write_TWI_MASTER_CTL((bfin_read_TWI_MASTER_CTL() & ~RSTART) |
 118                                         (min(msg->len, 0xff) << 6) | MEN | MDIR);
 119                                 SSYNC();
 120                         } else
 121                                 break;
 122                 }
 123
 124                 /* If we were able to do something, reset timeout */
 125                 if (int_stat)
 126                         timebase = get_timer(0);
 127
 128         } while (get_timer(timebase) < I2C_TIMEOUT);
 129
 130         return msg->len;
 131 }
 132
 133 /**
 134  * i2c_transfer - setup an i2c transfer
 135  *      @return: 0 if things worked, non-0 if things failed
 136  *
 137  *      Here we just get the i2c stuff all prepped and ready, and then tail off
 138  *      into wait_for_completion() for all the bits to go.
 139  */
 140 static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
 141 {
 142         uchar addr_buffer[] = {
 143                 (addr >>  0),
 144                 (addr >>  8),
 145                 (addr >> 16),
 146         };
 147         struct i2c_msg msg = {
 148                 .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
 149                 .buf   = buffer,
 150                 .len   = len,
 151                 .abuf  = addr_buffer,
 152                 .alen  = alen,
 153         };
 154         int ret;
 155
 156         dmemset(buffer, 0xff, len);
 157         debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ",
 158                 chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));
 159
 160         /* wait for things to settle */
 161         while (bfin_read_TWI_MASTER_STAT() & BUSBUSY)
 162                 if (ctrlc())
 163                         return 1;
 164
 165         /* Set Transmit device address */
 166         bfin_write_TWI_MASTER_ADDR(chip);
 167
 168         /* Clear the FIFO before starting things */
 169         bfin_write_TWI_FIFO_CTL(XMTFLUSH | RCVFLUSH);
 170         SSYNC();
 171         bfin_write_TWI_FIFO_CTL(0);
 172         SSYNC();
 173
 174         /* prime the pump */
 175         if (msg.alen) {
 176                 len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
 177                 debugi("first byte=0x%02x", *msg.abuf);
 178                 bfin_write_TWI_XMT_DATA8(*(msg.abuf++));
 179                 --msg.alen;
 180         } else if (!(msg.flags & I2C_M_READ) && msg.len) {
 181                 debugi("first byte=0x%02x", *msg.buf);
 182                 bfin_write_TWI_XMT_DATA8(*(msg.buf++));
 183                 --msg.len;
 184         }
 185
 186         /* clear int stat */
 187         bfin_write_TWI_MASTER_STAT(-1);
 188         bfin_write_TWI_INT_STAT(-1);
 189         bfin_write_TWI_INT_MASK(0);
 190         SSYNC();
 191
 192         /* Master enable */
 193         bfin_write_TWI_MASTER_CTL(
 194                         (bfin_read_TWI_MASTER_CTL() & FAST) |
 195                         (min(len, 0xff) << 6) | MEN |
 196                         ((msg.flags & I2C_M_READ) ? MDIR : 0)
 197         );
 198         SSYNC();
 199         debugi("CTL=0x%04x", bfin_read_TWI_MASTER_CTL());
 200
 201         /* process the rest */
 202         ret = wait_for_completion(&msg);
 203         debugi("ret=%d", ret);
 204
 205         if (ret) {
 206                 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() & ~MEN);
 207                 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA);
 208                 SSYNC();
 209                 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
 210                 SSYNC();
 211         }
 212
 213         return ret;
 214 }
 215
 216 /*
 217  * i2c_init - initialize the i2c bus
 218  *      @speed: bus speed (in HZ)
 219  *      @slaveaddr: address of device in slave mode (0 - not slave)
 220  *
 221  *      Slave mode isn't actually implemented.  It'll stay that way until
 222  *      we get a real request for it.
 223  */
 224 void i2c_init(int speed, int slaveaddr)
 225 {
 226         uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F;
 227
 228         /* Set TWI internal clock as 10MHz */
 229         bfin_write_TWI_CONTROL(prescale);
 230
 231         /* Set TWI interface clock as specified */
 232         bfin_write_TWI_CLKDIV(
 233                 ((5 * 1024 / (speed / 1000)) << 8) |
 234                 ((5 * 1024 / (speed / 1000)) & 0xFF)
 235         );
 236
 237         /* Don't turn it on */
 238         bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0);
 239
 240         /* But enable it */
 241         bfin_write_TWI_CONTROL(TWI_ENA | prescale);
 242         SSYNC();
 243
 244         debugi("CONTROL:0x%04x CLKDIV:0x%04x",
 245                 bfin_read_TWI_CONTROL(), bfin_read_TWI_CLKDIV());
 246
 247 #if CONFIG_SYS_I2C_SLAVE
 248 # error I2C slave support not tested/supported
 249         /* If they want us as a slave, do it */
 250         if (slaveaddr) {
 251                 bfin_write_TWI_SLAVE_ADDR(slaveaddr);
 252                 bfin_write_TWI_SLAVE_CTL(SEN);
 253         }
 254 #endif
 255 }
 256
 257 /**
 258  * i2c_probe - test if a chip exists at a given i2c address
 259  *      @chip: i2c chip addr to search for
 260  *      @return: 0 if found, non-0 if not found
 261  */
 262 int i2c_probe(uchar chip)
 263 {
 264         u8 byte;
 265         return i2c_read(chip, 0, 0, &byte, 1);
 266 }
 267
 268 /**
 269  * i2c_read - read data from an i2c device
 270  *      @chip: i2c chip addr
 271  *      @addr: memory (register) address in the chip
 272  *      @alen: byte size of address
 273  *      @buffer: buffer to store data read from chip
 274  *      @len: how many bytes to read
 275  *      @return: 0 on success, non-0 on failure
 276  */
 277 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 278 {
 279         return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ));
 280 }
 281
 282 /**
 283  * i2c_write - write data to an i2c device
 284  *      @chip: i2c chip addr
 285  *      @addr: memory (register) address in the chip
 286  *      @alen: byte size of address
 287  *      @buffer: buffer holding data to write to chip
 288  *      @len: how many bytes to write
 289  *      @return: 0 on success, non-0 on failure
 290  */
 291 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 292 {
 293         return i2c_transfer(chip, addr, alen, buffer, len, 0);
 294 }