2 * Copyright 2006,2009 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifdef CONFIG_HARD_I2C
24 #include <i2c.h> /* Functional interface */
27 #include <asm/fsl_i2c.h> /* HW definitions */
29 /* The maximum number of microseconds we will wait until another master has
30 * released the bus. If not defined in the board header file, then use a
33 #ifndef CONFIG_I2C_MBB_TIMEOUT
34 #define CONFIG_I2C_MBB_TIMEOUT 100000
37 /* The maximum number of microseconds we will wait for a read or write
38 * operation to complete. If not defined in the board header file, then use a
41 #ifndef CONFIG_I2C_TIMEOUT
42 #define CONFIG_I2C_TIMEOUT 10000
45 #define I2C_READ_BIT 1
46 #define I2C_WRITE_BIT 0
48 DECLARE_GLOBAL_DATA_PTR;
50 /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
51 * Default is bus 0. This is necessary because the DDR initialization
52 * runs from ROM, and we can't switch buses because we can't modify
53 * the global variables.
55 #ifndef CONFIG_SYS_SPD_BUS_NUM
56 #define CONFIG_SYS_SPD_BUS_NUM 0
58 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
59 #if defined(CONFIG_I2C_MUX)
60 static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
63 static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED};
65 static const struct fsl_i2c *i2c_dev[2] = {
66 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET),
67 #ifdef CONFIG_SYS_I2C2_OFFSET
68 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET)
72 /* I2C speed map for a DFSR value of 1 */
75 * Map I2C frequency dividers to FDR and DFSR values
77 * This structure is used to define the elements of a table that maps I2C
78 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
79 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
80 * Sampling Rate (DFSR) registers.
82 * The actual table should be defined in the board file, and it must be called
83 * fsl_i2c_speed_map[].
85 * The last entry of the table must have a value of {-1, X}, where X is same
86 * FDR/DFSR values as the second-to-last entry. This guarantees that any
87 * search through the array will always find a match.
89 * The values of the divider must be in increasing numerical order, i.e.
90 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
92 * For this table, the values are based on a value of 1 for the DFSR
93 * register. See the application note AN2919 "Determining the I2C Frequency
94 * Divider Ratio for SCL"
96 * ColdFire I2C frequency dividers for FDR values are different from
97 * PowerPC. The protocol to use the I2C module is still the same.
98 * A different table is defined and are based on MCF5xxx user manual.
101 static const struct {
102 unsigned short divider;
107 } fsl_i2c_speed_map[] = {
109 {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35},
110 {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2},
111 {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4},
112 {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3},
113 {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7},
114 {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9},
115 {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46},
116 {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12},
117 {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14},
118 {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16},
119 {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19},
120 {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22},
121 {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24},
122 {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27},
123 {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30},
124 {61440, 1, 31}, {-1, 1, 31}
125 #elif defined(__M68K__)
126 {20, 32}, {22, 33}, {24, 34}, {26, 35},
127 {28, 0}, {28, 36}, {30, 1}, {32, 37},
128 {34, 2}, {36, 38}, {40, 3}, {40, 39},
129 {44, 4}, {48, 5}, {48, 40}, {56, 6},
130 {56, 41}, {64, 42}, {68, 7}, {72, 43},
131 {80, 8}, {80, 44}, {88, 9}, {96, 41},
132 {104, 10}, {112, 42}, {128, 11}, {128, 43},
133 {144, 12}, {160, 13}, {160, 48}, {192, 14},
134 {192, 49}, {224, 50}, {240, 15}, {256, 51},
135 {288, 16}, {320, 17}, {320, 52}, {384, 18},
136 {384, 53}, {448, 54}, {480, 19}, {512, 55},
137 {576, 20}, {640, 21}, {640, 56}, {768, 22},
138 {768, 57}, {960, 23}, {896, 58}, {1024, 59},
139 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
140 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
141 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
147 * Set the I2C bus speed for a given I2C device
149 * @param dev: the I2C device
150 * @i2c_clk: I2C bus clock frequency
151 * @speed: the desired speed of the bus
153 * The I2C device must be stopped before calling this function.
155 * The return value is the actual bus speed that is set.
157 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
158 unsigned int i2c_clk, unsigned int speed)
160 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
164 * We want to choose an FDR/DFSR that generates an I2C bus speed that
165 * is equal to or lower than the requested speed. That means that we
166 * want the first divider that is equal to or greater than the
167 * calculated divider.
170 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
171 if (fsl_i2c_speed_map[i].divider >= divider) {
175 dfsr = fsl_i2c_speed_map[i].dfsr;
177 fdr = fsl_i2c_speed_map[i].fdr;
178 speed = i2c_clk / fsl_i2c_speed_map[i].divider;
179 writeb(fdr, &dev->fdr); /* set bus speed */
181 writeb(dfsr, &dev->dfsrr); /* set default filter */
190 i2c_init(int speed, int slaveadd)
195 #ifdef CONFIG_SYS_I2C_INIT_BOARD
196 /* call board specific i2c bus reset routine before accessing the */
197 /* environment, which might be in a chip on that bus. For details */
198 /* about this problem see doc/I2C_Edge_Conditions. */
201 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
203 writeb(0, &dev->cr); /* stop I2C controller */
204 udelay(5); /* let it shutdown in peace */
205 temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
206 if (gd->flags & GD_FLG_RELOC)
207 i2c_bus_speed[0] = temp;
208 writeb(slaveadd << 1, &dev->adr); /* write slave address */
209 writeb(0x0, &dev->sr); /* clear status register */
210 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
212 #ifdef CONFIG_SYS_I2C2_OFFSET
213 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET);
215 writeb(0, &dev->cr); /* stop I2C controller */
216 udelay(5); /* let it shutdown in peace */
217 temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
218 if (gd->flags & GD_FLG_RELOC)
219 i2c_bus_speed[1] = temp;
220 writeb(slaveadd << 1, &dev->adr); /* write slave address */
221 writeb(0x0, &dev->sr); /* clear status register */
222 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
229 unsigned long long timeval = get_ticks();
230 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
232 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
233 if ((get_ticks() - timeval) > timeout)
240 static __inline__ int
244 unsigned long long timeval = get_ticks();
245 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
248 csr = readb(&i2c_dev[i2c_bus_num]->sr);
249 if (!(csr & I2C_SR_MIF))
251 /* Read again to allow register to stabilise */
252 csr = readb(&i2c_dev[i2c_bus_num]->sr);
254 writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
256 if (csr & I2C_SR_MAL) {
257 debug("i2c_wait: MAL\n");
261 if (!(csr & I2C_SR_MCF)) {
262 debug("i2c_wait: unfinished\n");
266 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
267 debug("i2c_wait: No RXACK\n");
272 } while ((get_ticks() - timeval) < timeout);
274 debug("i2c_wait: timed out\n");
278 static __inline__ int
279 i2c_write_addr (u8 dev, u8 dir, int rsta)
281 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
282 | (rsta ? I2C_CR_RSTA : 0),
283 &i2c_dev[i2c_bus_num]->cr);
285 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
287 if (i2c_wait(I2C_WRITE_BIT) < 0)
293 static __inline__ int
294 __i2c_write(u8 *data, int length)
298 for (i = 0; i < length; i++) {
299 writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
301 if (i2c_wait(I2C_WRITE_BIT) < 0)
308 static __inline__ int
309 __i2c_read(u8 *data, int length)
313 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
314 &i2c_dev[i2c_bus_num]->cr);
317 readb(&i2c_dev[i2c_bus_num]->dr);
319 for (i = 0; i < length; i++) {
320 if (i2c_wait(I2C_READ_BIT) < 0)
323 /* Generate ack on last next to last byte */
325 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
326 &i2c_dev[i2c_bus_num]->cr);
328 /* Generate stop on last byte */
330 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
332 data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
339 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
341 int i = -1; /* signal error */
344 if (i2c_wait4bus() >= 0
345 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
346 && __i2c_write(&a[4 - alen], alen) == alen)
347 i = 0; /* No error so far */
350 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
351 i = __i2c_read(data, length);
353 if (length && i2c_wait4bus()) /* Wait until STOP */
354 debug("i2c_read: wait4bus timed out\n");
356 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
365 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
367 int i = -1; /* signal error */
370 if (i2c_wait4bus() >= 0
371 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
372 && __i2c_write(&a[4 - alen], alen) == alen) {
373 i = __i2c_write(data, length);
376 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
377 if (i2c_wait4bus()) /* Wait until STOP */
378 debug("i2c_write: wait4bus timed out\n");
387 i2c_probe(uchar chip)
389 /* For unknow reason the controller will ACK when
390 * probing for a slave with the same address, so skip
393 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
396 return i2c_read(chip, 0, 0, NULL, 0);
399 int i2c_set_bus_num(unsigned int bus)
401 #if defined(CONFIG_I2C_MUX)
402 if (bus < CONFIG_SYS_MAX_I2C_BUS) {
407 ret = i2x_mux_select_mux(bus);
412 i2c_bus_num_mux = bus;
414 #ifdef CONFIG_SYS_I2C2_OFFSET
427 int i2c_set_bus_speed(unsigned int speed)
429 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;
431 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
432 i2c_bus_speed[i2c_bus_num] =
433 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
434 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */
439 unsigned int i2c_get_bus_num(void)
441 #if defined(CONFIG_I2C_MUX)
442 return i2c_bus_num_mux;
448 unsigned int i2c_get_bus_speed(void)
450 return i2c_bus_speed[i2c_bus_num];
453 #endif /* CONFIG_HARD_I2C */