1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductors, Inc.
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <imx_lpi2c.h>
12 #include <asm/arch/sys_proto.h>
17 #define LPI2C_FIFO_SIZE 4
18 #define LPI2C_NACK_TOUT_MS 1
19 #define LPI2C_TIMEOUT_MS 100
21 /* Weak linked function for overridden by some SoC power function */
22 int __weak init_i2c_power(unsigned i2c_num)
27 static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
29 lpi2c_status_t result = LPI2C_SUCESS;
32 status = readl(®s->msr);
34 if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
40 static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
42 lpi2c_status_t result = LPI2C_SUCESS;
45 status = readl(®s->msr);
46 /* errors to check for */
47 status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
48 LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
51 if (status & LPI2C_MSR_PLTF_MASK)
52 result = LPI2C_PIN_LOW_TIMEOUT_ERR;
53 else if (status & LPI2C_MSR_ALF_MASK)
54 result = LPI2C_ARB_LOST_ERR;
55 else if (status & LPI2C_MSR_NDF_MASK)
56 result = LPI2C_NAK_ERR;
57 else if (status & LPI2C_MSR_FEF_MASK)
58 result = LPI2C_FIFO_ERR;
60 /* clear status flags */
61 writel(0x7f00, ®s->msr);
63 val = readl(®s->mcr);
64 val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
65 writel(val, ®s->mcr);
71 static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
73 lpi2c_status_t result = LPI2C_SUCESS;
75 ulong start_time = get_timer(0);
78 txcount = LPI2C_MFSR_TXCOUNT(readl(®s->mfsr));
79 txcount = LPI2C_FIFO_SIZE - txcount;
80 result = imx_lpci2c_check_clear_error(regs);
82 debug("i2c: wait for tx ready: result 0x%x\n", result);
85 if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
86 debug("i2c: wait for tx ready: timeout\n");
94 static int bus_i2c_send(struct imx_lpi2c_reg *regs, u8 *txbuf, int len)
96 lpi2c_status_t result = LPI2C_SUCESS;
103 result = bus_i2c_wait_for_tx_ready(regs);
105 debug("i2c: send wait fot tx ready: %d\n", result);
108 writel(*txbuf++, ®s->mtdr);
114 static int bus_i2c_receive(struct imx_lpi2c_reg *regs, u8 *rxbuf, int len)
116 lpi2c_status_t result = LPI2C_SUCESS;
118 ulong start_time = get_timer(0);
124 result = bus_i2c_wait_for_tx_ready(regs);
126 debug("i2c: receive wait fot tx ready: %d\n", result);
130 /* clear all status flags */
131 writel(0x7f00, ®s->msr);
132 /* send receive command */
133 val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
134 writel(val, ®s->mtdr);
138 result = imx_lpci2c_check_clear_error(regs);
140 debug("i2c: receive check clear error: %d\n",
144 if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
145 debug("i2c: receive mrdr: timeout\n");
148 val = readl(®s->mrdr);
149 } while (val & LPI2C_MRDR_RXEMPTY_MASK);
150 *rxbuf++ = LPI2C_MRDR_DATA(val);
156 static int bus_i2c_start(struct imx_lpi2c_reg *regs, u8 addr, u8 dir)
158 lpi2c_status_t result;
161 result = imx_lpci2c_check_busy_bus(regs);
163 debug("i2c: start check busy bus: 0x%x\n", result);
166 /* clear all status flags */
167 writel(0x7f00, ®s->msr);
168 /* turn off auto-stop condition */
169 val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
170 writel(val, ®s->mcfgr1);
171 /* wait tx fifo ready */
172 result = bus_i2c_wait_for_tx_ready(regs);
174 debug("i2c: start wait for tx ready: 0x%x\n", result);
177 /* issue start command */
178 val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
179 writel(val, ®s->mtdr);
184 static int bus_i2c_stop(struct imx_lpi2c_reg *regs)
186 lpi2c_status_t result;
190 result = bus_i2c_wait_for_tx_ready(regs);
192 debug("i2c: stop wait for tx ready: 0x%x\n", result);
196 /* send stop command */
197 writel(LPI2C_MTDR_CMD(0x2), ®s->mtdr);
199 start_time = get_timer(0);
201 status = readl(®s->msr);
202 result = imx_lpci2c_check_clear_error(regs);
203 /* stop detect flag */
204 if (status & LPI2C_MSR_SDF_MASK) {
205 /* clear stop flag */
206 status &= LPI2C_MSR_SDF_MASK;
207 writel(status, ®s->msr);
211 if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
212 debug("stop timeout\n");
220 static int bus_i2c_read(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len)
222 lpi2c_status_t result;
224 result = bus_i2c_start(regs, chip, 1);
227 result = bus_i2c_receive(regs, buf, len);
234 static int bus_i2c_write(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len)
236 lpi2c_status_t result;
238 result = bus_i2c_start(regs, chip, 0);
241 result = bus_i2c_send(regs, buf, len);
249 static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
251 struct imx_lpi2c_reg *regs;
253 u32 preescale = 0, best_pre = 0, clkhi = 0;
254 u32 best_clkhi = 0, abs_error = 0, rate;
255 u32 error = 0xffffffff;
260 regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
261 clock_rate = imx_get_i2cclk(bus->seq);
265 mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
266 /* disable master mode */
267 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
268 writel(val | LPI2C_MCR_MEN(0), ®s->mcr);
270 for (preescale = 1; (preescale <= 128) &&
271 (error != 0); preescale = 2 * preescale) {
272 for (clkhi = 1; clkhi < 32; clkhi++) {
274 rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
276 rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
278 abs_error = speed > rate ? speed - rate : rate - speed;
280 if (abs_error < error) {
281 best_pre = preescale;
290 /* Standard, fast, fast mode plus and ultra-fast transfers. */
291 val = LPI2C_MCCR0_CLKHI(best_clkhi);
293 val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
295 val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
296 LPI2C_MCCR0_DATAVD(best_clkhi / 2);
297 writel(val, ®s->mccr0);
299 for (i = 0; i < 8; i++) {
300 if (best_pre == (1 << i)) {
306 val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
307 writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), ®s->mcfgr1);
310 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
311 writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
317 static int bus_i2c_init(struct udevice *bus, int speed)
319 struct imx_lpi2c_reg *regs;
323 regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
324 /* reset peripheral */
325 writel(LPI2C_MCR_RST_MASK, ®s->mcr);
326 writel(0x0, ®s->mcr);
327 /* Disable Dozen mode */
328 writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), ®s->mcr);
329 /* host request disable, active high, external pin */
330 val = readl(®s->mcfgr0);
331 val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
332 LPI2C_MCFGR0_HRSEL_MASK));
333 val |= LPI2C_MCFGR0_HRPOL(0x1);
334 writel(val, ®s->mcfgr0);
335 /* pincfg and ignore ack */
336 val = readl(®s->mcfgr1);
337 val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
338 val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
339 val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
340 writel(val, ®s->mcfgr1);
342 ret = bus_i2c_set_bus_speed(bus, speed);
344 /* enable lpi2c in master mode */
345 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
346 writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
348 debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);
353 static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
356 struct imx_lpi2c_reg *regs;
357 lpi2c_status_t result;
359 regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
360 result = bus_i2c_start(regs, chip, 0);
363 bus_i2c_init(bus, 100000);
367 result = bus_i2c_stop(regs);
369 bus_i2c_init(bus, 100000);
374 static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
376 struct imx_lpi2c_reg *regs;
377 int ret = 0, ret_stop;
379 regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
380 for (; nmsgs > 0; nmsgs--, msg++) {
381 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
382 if (msg->flags & I2C_M_RD)
383 ret = bus_i2c_read(regs, msg->addr, msg->buf, msg->len);
385 ret = bus_i2c_write(regs, msg->addr, msg->buf,
393 debug("i2c_write: error sending\n");
395 ret_stop = bus_i2c_stop(regs);
397 debug("i2c_xfer: stop bus error\n");
404 static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
406 return bus_i2c_set_bus_speed(bus, speed);
409 static int imx_lpi2c_probe(struct udevice *bus)
411 struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
415 i2c_bus->driver_data = dev_get_driver_data(bus);
417 addr = devfdt_get_addr(bus);
418 if (addr == FDT_ADDR_T_NONE)
421 i2c_bus->base = addr;
422 i2c_bus->index = bus->seq;
425 /* power up i2c resource */
426 ret = init_i2c_power(bus->seq);
428 debug("init_i2c_power err = %d\n", ret);
432 /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
433 ret = enable_i2c_clk(1, bus->seq);
437 ret = bus_i2c_init(bus, 100000);
441 debug("i2c : controller bus %d at %lu , speed %d: ",
442 bus->seq, i2c_bus->base,
448 static const struct dm_i2c_ops imx_lpi2c_ops = {
449 .xfer = imx_lpi2c_xfer,
450 .probe_chip = imx_lpi2c_probe_chip,
451 .set_bus_speed = imx_lpi2c_set_bus_speed,
454 static const struct udevice_id imx_lpi2c_ids[] = {
455 { .compatible = "fsl,imx7ulp-lpi2c", },
456 { .compatible = "fsl,imx8qm-lpi2c", },
460 U_BOOT_DRIVER(imx_lpi2c) = {
463 .of_match = imx_lpi2c_ids,
464 .probe = imx_lpi2c_probe,
465 .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
466 .ops = &imx_lpi2c_ops,