2 * LPC32xx I2C interface driver
4 * (C) Copyright 2014-2015 DENX Software Engineering GmbH
5 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
7 * SPDX-License-Identifier: GPL-2.0+
9 * NOTE: This driver should be converted to driver model before June 2017.
10 * Please see doc/driver-model/i2c-howto.txt for instructions.
16 #include <linux/errno.h>
17 #include <asm/arch/clk.h>
22 * Provide default speed and slave if target did not
25 #if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
26 #define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
29 #if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
30 #define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
33 /* i2c register set */
34 struct lpc32xx_i2c_base {
53 struct lpc32xx_i2c_dev {
54 struct lpc32xx_i2c_base *base;
58 #endif /* CONFIG_DM_I2C */
60 /* TX register fields */
61 #define LPC32XX_I2C_TX_START 0x00000100
62 #define LPC32XX_I2C_TX_STOP 0x00000200
64 /* Control register values */
65 #define LPC32XX_I2C_SOFT_RESET 0x00000100
67 /* Status register values */
68 #define LPC32XX_I2C_STAT_TFF 0x00000400
69 #define LPC32XX_I2C_STAT_RFE 0x00000200
70 #define LPC32XX_I2C_STAT_DRMI 0x00000008
71 #define LPC32XX_I2C_STAT_NAI 0x00000004
72 #define LPC32XX_I2C_STAT_TDI 0x00000001
75 static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
76 (struct lpc32xx_i2c_base *)I2C1_BASE,
77 (struct lpc32xx_i2c_base *)I2C2_BASE,
78 (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
82 /* Set I2C bus speed */
83 static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
84 unsigned int speed, unsigned int chip)
91 /* OTG I2C clock source and CLK registers are different */
93 half_period = (get_periph_clk_rate() / speed) / 2;
94 if (half_period > 0xFF)
97 half_period = (get_hclk_clk_rate() / speed) / 2;
98 if (half_period > 0x3FF)
102 writel(half_period, &base->clk_hi);
103 writel(half_period, &base->clk_lo);
107 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
108 static void __i2c_init(struct lpc32xx_i2c_base *base,
109 int requested_speed, int slaveadd, unsigned int chip)
111 /* soft reset (auto-clears) */
112 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
113 /* set HI and LO periods for half of the default speed */
114 __i2c_set_bus_speed(base, requested_speed, chip);
117 /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
118 static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
122 /* Soft-reset the controller */
123 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
124 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
126 /* Addre slave for write with start before and stop after */
127 writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
129 /* wait for end of transation */
130 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
132 /* was there no acknowledge? */
133 return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
137 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
138 * Begin write, send address byte(s), begin read, receive data bytes, end.
140 static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
141 int alen, u8 *data, int length)
145 /* Soft-reset the controller */
146 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
147 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
149 /* do we need to write an address at all? */
151 /* Address slave in write mode */
152 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
153 /* write address bytes */
155 /* compute address byte + stop for the last one */
156 int a = (addr >> (8 * alen)) & 0xff;
158 a |= LPC32XX_I2C_TX_STOP;
159 /* Send address byte */
160 writel(a, &base->tx);
162 /* wait for end of transation */
163 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
165 /* clear end-of-transaction flag */
166 writel(1, &base->stat);
168 /* do we have to read data at all? */
170 /* Address slave in read mode */
171 writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
174 while (length | wlen) {
175 /* read status for TFF and RFE */
176 stat = readl(&base->stat);
177 /* must we, can we write a trigger byte? */
179 & (!(stat & LPC32XX_I2C_STAT_TFF))) {
181 /* write trigger byte + stop if last */
183 LPC32XX_I2C_TX_STOP, &base->tx);
185 /* must we, can we read a data byte? */
187 & (!(stat & LPC32XX_I2C_STAT_RFE))) {
190 *(data++) = readl(&base->rx);
193 /* wait for end of transation */
194 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
196 /* clear end-of-transaction flag */
197 writel(1, &base->stat);
204 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
205 * Begin write, send address byte(s), send data bytes, end.
207 static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
208 int alen, u8 *data, int length)
212 /* Soft-reset the controller */
213 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
214 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
216 /* do we need to write anything at all? */
218 /* Address slave in write mode */
219 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
222 /* write address bytes */
224 /* wait for transmit fifo not full */
225 stat = readl(&base->stat);
226 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
228 int a = (addr >> (8 * alen)) & 0xff;
229 if (!(alen | length))
230 a |= LPC32XX_I2C_TX_STOP;
231 /* Send address byte */
232 writel(a, &base->tx);
236 /* wait for transmit fifo not full */
237 stat = readl(&base->stat);
238 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
239 /* compute data byte, add stop if length==0 */
243 d |= LPC32XX_I2C_TX_STOP;
245 writel(d, &base->tx);
248 /* wait for end of transation */
249 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
251 /* clear end-of-transaction flag */
252 writel(1, &base->stat);
256 #ifndef CONFIG_DM_I2C
257 static void lpc32xx_i2c_init(struct i2c_adapter *adap,
258 int requested_speed, int slaveadd)
260 __i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
264 static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
266 return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
269 static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
270 int alen, u8 *data, int length)
272 return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
276 static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
277 int alen, u8 *data, int length)
279 return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
283 static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
286 return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
290 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
291 lpc32xx_i2c_read, lpc32xx_i2c_write,
292 lpc32xx_i2c_set_bus_speed,
293 CONFIG_SYS_I2C_LPC32XX_SPEED,
294 CONFIG_SYS_I2C_LPC32XX_SLAVE,
297 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
298 lpc32xx_i2c_read, lpc32xx_i2c_write,
299 lpc32xx_i2c_set_bus_speed,
300 CONFIG_SYS_I2C_LPC32XX_SPEED,
301 CONFIG_SYS_I2C_LPC32XX_SLAVE,
304 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
305 lpc32xx_i2c_read, lpc32xx_i2c_write,
306 lpc32xx_i2c_set_bus_speed,
310 #else /* CONFIG_DM_I2C */
311 static int lpc32xx_i2c_probe(struct udevice *bus)
313 struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
315 __i2c_init(dev->base, dev->speed, 0, dev->index);
319 static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
322 struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
323 return __i2c_probe_chip(dev->base, chip_addr);
326 static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
329 struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
330 struct i2c_msg *dmsg, *omsg, dummy;
331 uint i = 0, address = 0;
333 memset(&dummy, 0, sizeof(struct i2c_msg));
335 /* We expect either two messages (one with an offset and one with the
336 * actual data) or one message (just data)
338 if (nmsgs > 2 || nmsgs == 0) {
339 debug("%s: Only one or two messages are supported.", __func__);
343 omsg = nmsgs == 1 ? &dummy : msg;
344 dmsg = nmsgs == 1 ? msg : msg + 1;
346 /* the address is expected to be a uint, not a array. */
347 address = omsg->buf[0];
348 for (i = 1; i < omsg->len; i++)
349 address = (address << 8) + omsg->buf[i];
351 if (dmsg->flags & I2C_M_RD)
352 return __i2c_read(dev->base, dmsg->addr, address,
353 omsg->len, dmsg->buf, dmsg->len);
355 return __i2c_write(dev->base, dmsg->addr, address,
356 omsg->len, dmsg->buf, dmsg->len);
359 static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
361 struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
362 return __i2c_set_bus_speed(dev->base, speed, dev->index);
365 static int lpc32xx_i2c_reset(struct udevice *bus)
367 struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
369 __i2c_init(dev->base, dev->speed, 0, dev->index);
373 static const struct dm_i2c_ops lpc32xx_i2c_ops = {
374 .xfer = lpc32xx_i2c_xfer,
375 .probe_chip = lpc32xx_i2c_probe_chip,
376 .deblock = lpc32xx_i2c_reset,
377 .set_bus_speed = lpc32xx_i2c_set_bus_speed,
380 U_BOOT_DRIVER(i2c_lpc32xx) = {
382 .name = "i2c_lpc32xx",
383 .probe = lpc32xx_i2c_probe,
384 .ops = &lpc32xx_i2c_ops,
386 #endif /* CONFIG_DM_I2C */