2 * LPC32xx I2C interface driver
4 * (C) Copyright 2014-2015 DENX Software Engineering GmbH
5 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/errno.h>
14 #include <asm/arch/clk.h>
19 * Provide default speed and slave if target did not
22 #if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
23 #define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
26 #if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
27 #define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
30 /* i2c register set */
31 struct lpc32xx_i2c_base {
50 struct lpc32xx_i2c_dev {
51 struct lpc32xx_i2c_base *base;
55 #endif /* CONFIG_DM_I2C */
57 /* TX register fields */
58 #define LPC32XX_I2C_TX_START 0x00000100
59 #define LPC32XX_I2C_TX_STOP 0x00000200
61 /* Control register values */
62 #define LPC32XX_I2C_SOFT_RESET 0x00000100
64 /* Status register values */
65 #define LPC32XX_I2C_STAT_TFF 0x00000400
66 #define LPC32XX_I2C_STAT_RFE 0x00000200
67 #define LPC32XX_I2C_STAT_DRMI 0x00000008
68 #define LPC32XX_I2C_STAT_NAI 0x00000004
69 #define LPC32XX_I2C_STAT_TDI 0x00000001
72 static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
73 (struct lpc32xx_i2c_base *)I2C1_BASE,
74 (struct lpc32xx_i2c_base *)I2C2_BASE,
75 (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
79 /* Set I2C bus speed */
80 static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
81 unsigned int speed, unsigned int chip)
88 /* OTG I2C clock source and CLK registers are different */
90 half_period = (get_periph_clk_rate() / speed) / 2;
91 if (half_period > 0xFF)
94 half_period = (get_hclk_clk_rate() / speed) / 2;
95 if (half_period > 0x3FF)
99 writel(half_period, &base->clk_hi);
100 writel(half_period, &base->clk_lo);
104 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
105 static void __i2c_init(struct lpc32xx_i2c_base *base,
106 int requested_speed, int slaveadd, unsigned int chip)
108 /* soft reset (auto-clears) */
109 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
110 /* set HI and LO periods for half of the default speed */
111 __i2c_set_bus_speed(base, requested_speed, chip);
114 /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
115 static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
119 /* Soft-reset the controller */
120 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
121 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
123 /* Addre slave for write with start before and stop after */
124 writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
126 /* wait for end of transation */
127 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
129 /* was there no acknowledge? */
130 return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
134 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
135 * Begin write, send address byte(s), begin read, receive data bytes, end.
137 static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
138 int alen, u8 *data, int length)
142 /* Soft-reset the controller */
143 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
144 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
146 /* do we need to write an address at all? */
148 /* Address slave in write mode */
149 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
150 /* write address bytes */
152 /* compute address byte + stop for the last one */
153 int a = (addr >> (8 * alen)) & 0xff;
155 a |= LPC32XX_I2C_TX_STOP;
156 /* Send address byte */
157 writel(a, &base->tx);
159 /* wait for end of transation */
160 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
162 /* clear end-of-transaction flag */
163 writel(1, &base->stat);
165 /* do we have to read data at all? */
167 /* Address slave in read mode */
168 writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
171 while (length | wlen) {
172 /* read status for TFF and RFE */
173 stat = readl(&base->stat);
174 /* must we, can we write a trigger byte? */
176 & (!(stat & LPC32XX_I2C_STAT_TFF))) {
178 /* write trigger byte + stop if last */
180 LPC32XX_I2C_TX_STOP, &base->tx);
182 /* must we, can we read a data byte? */
184 & (!(stat & LPC32XX_I2C_STAT_RFE))) {
187 *(data++) = readl(&base->rx);
190 /* wait for end of transation */
191 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
193 /* clear end-of-transaction flag */
194 writel(1, &base->stat);
201 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
202 * Begin write, send address byte(s), send data bytes, end.
204 static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
205 int alen, u8 *data, int length)
209 /* Soft-reset the controller */
210 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
211 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
213 /* do we need to write anything at all? */
215 /* Address slave in write mode */
216 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
219 /* write address bytes */
221 /* wait for transmit fifo not full */
222 stat = readl(&base->stat);
223 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
225 int a = (addr >> (8 * alen)) & 0xff;
226 if (!(alen | length))
227 a |= LPC32XX_I2C_TX_STOP;
228 /* Send address byte */
229 writel(a, &base->tx);
233 /* wait for transmit fifo not full */
234 stat = readl(&base->stat);
235 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
236 /* compute data byte, add stop if length==0 */
240 d |= LPC32XX_I2C_TX_STOP;
242 writel(d, &base->tx);
245 /* wait for end of transation */
246 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
248 /* clear end-of-transaction flag */
249 writel(1, &base->stat);
253 #ifndef CONFIG_DM_I2C
254 static void lpc32xx_i2c_init(struct i2c_adapter *adap,
255 int requested_speed, int slaveadd)
257 __i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
261 static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
263 return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
266 static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
267 int alen, u8 *data, int length)
269 return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
273 static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
274 int alen, u8 *data, int length)
276 return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
280 static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
283 return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
287 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
288 lpc32xx_i2c_read, lpc32xx_i2c_write,
289 lpc32xx_i2c_set_bus_speed,
290 CONFIG_SYS_I2C_LPC32XX_SPEED,
291 CONFIG_SYS_I2C_LPC32XX_SLAVE,
294 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
295 lpc32xx_i2c_read, lpc32xx_i2c_write,
296 lpc32xx_i2c_set_bus_speed,
297 CONFIG_SYS_I2C_LPC32XX_SPEED,
298 CONFIG_SYS_I2C_LPC32XX_SLAVE,
301 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
302 lpc32xx_i2c_read, lpc32xx_i2c_write,
303 lpc32xx_i2c_set_bus_speed,
307 #else /* CONFIG_DM_I2C */
308 static int lpc32xx_i2c_probe(struct udevice *bus)
310 struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
312 __i2c_init(dev->base, dev->speed, 0, dev->index);
316 static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
319 struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
320 return __i2c_probe_chip(dev->base, chip_addr);
323 static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
326 struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
327 struct i2c_msg *dmsg, *omsg, dummy;
328 uint i = 0, address = 0;
330 memset(&dummy, 0, sizeof(struct i2c_msg));
332 /* We expect either two messages (one with an offset and one with the
333 * actual data) or one message (just data)
335 if (nmsgs > 2 || nmsgs == 0) {
336 debug("%s: Only one or two messages are supported.", __func__);
340 omsg = nmsgs == 1 ? &dummy : msg;
341 dmsg = nmsgs == 1 ? msg : msg + 1;
343 /* the address is expected to be a uint, not a array. */
344 address = omsg->buf[0];
345 for (i = 1; i < omsg->len; i++)
346 address = (address << 8) + omsg->buf[i];
348 if (dmsg->flags & I2C_M_RD)
349 return __i2c_read(dev->base, dmsg->addr, address,
350 omsg->len, dmsg->buf, dmsg->len);
352 return __i2c_write(dev->base, dmsg->addr, address,
353 omsg->len, dmsg->buf, dmsg->len);
356 static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
358 struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
359 return __i2c_set_bus_speed(dev->base, speed, dev->index);
362 static int lpc32xx_i2c_reset(struct udevice *bus)
364 struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
366 __i2c_init(dev->base, dev->speed, 0, dev->index);
370 static const struct dm_i2c_ops lpc32xx_i2c_ops = {
371 .xfer = lpc32xx_i2c_xfer,
372 .probe_chip = lpc32xx_i2c_probe_chip,
373 .deblock = lpc32xx_i2c_reset,
374 .set_bus_speed = lpc32xx_i2c_set_bus_speed,
377 U_BOOT_DRIVER(i2c_lpc32xx) = {
379 .name = "i2c_lpc32xx",
380 .probe = lpc32xx_i2c_probe,
381 .ops = &lpc32xx_i2c_ops,
383 #endif /* CONFIG_DM_I2C */