2 * i2c driver for Freescale i.MX series
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/errno.h>
49 #define I2CR_IEN (1 << 7)
50 #define I2CR_IIEN (1 << 6)
51 #define I2CR_MSTA (1 << 5)
52 #define I2CR_MTX (1 << 4)
53 #define I2CR_TX_NO_AK (1 << 3)
54 #define I2CR_RSTA (1 << 2)
56 #define I2SR_ICF (1 << 7)
57 #define I2SR_IBB (1 << 5)
58 #define I2SR_IIF (1 << 1)
59 #define I2SR_RX_NO_AK (1 << 0)
61 #ifdef CONFIG_SYS_I2C_BASE
62 #define I2C_BASE CONFIG_SYS_I2C_BASE
64 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
67 static u16 i2c_clk_div[50][2] = {
68 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
69 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
70 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
71 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
72 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
73 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
74 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
75 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
76 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
77 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
78 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
79 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
80 { 3072, 0x1E }, { 3840, 0x1F }
84 * Calculate and set proper clock divider
86 static uint8_t i2c_imx_get_clk(unsigned int rate)
88 unsigned int i2c_clk_rate;
92 #if defined(CONFIG_MX31)
93 struct clock_control_regs *sc_regs =
94 (struct clock_control_regs *)CCM_BASE;
96 /* start the required I2C clock */
97 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
101 /* Divider value calculation */
102 i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK);
103 div = (i2c_clk_rate + rate - 1) / rate;
104 if (div < i2c_clk_div[0][0])
106 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
107 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
109 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
112 /* Store divider value */
117 * Reset I2C Controller
121 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
123 writeb(0, &i2c_regs->i2cr); /* Reset module */
124 writeb(0, &i2c_regs->i2sr);
130 void i2c_init(int speed, int unused)
132 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
133 u8 clk_idx = i2c_imx_get_clk(speed);
134 u8 idx = i2c_clk_div[clk_idx][1];
136 /* Store divider value */
137 writeb(idx, &i2c_regs->ifdr);
145 int i2c_set_bus_speed(unsigned int speed)
154 unsigned int i2c_get_bus_speed(void)
156 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
157 u8 clk_idx = readb(&i2c_regs->ifdr);
160 for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
163 return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
166 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
167 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
168 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
170 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
174 ulong start_time = get_timer(0);
176 sr = readb(&i2c_regs->i2sr);
177 if ((sr & (state >> 8)) == (unsigned char)state)
180 elapsed = get_timer(start_time);
181 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
184 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
185 sr, readb(&i2c_regs->i2cr), state);
189 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
193 writeb(0, &i2c_regs->i2sr);
194 writeb(byte, &i2c_regs->i2dr);
195 ret = wait_for_sr_state(i2c_regs, ST_IIF);
198 ret = readb(&i2c_regs->i2sr);
199 if (ret & I2SR_RX_NO_AK)
205 * Start the controller
207 int i2c_imx_start(void)
209 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
210 unsigned int temp = 0;
213 /* Enable I2C controller */
214 writeb(0, &i2c_regs->i2sr);
215 writeb(I2CR_IEN, &i2c_regs->i2cr);
217 /* Wait controller to be stable */
220 /* Start I2C transaction */
221 temp = readb(&i2c_regs->i2cr);
223 writeb(temp, &i2c_regs->i2cr);
225 result = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
229 temp |= I2CR_MTX | I2CR_TX_NO_AK;
230 writeb(temp, &i2c_regs->i2cr);
236 * Stop the controller
238 void i2c_imx_stop(void)
241 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
242 unsigned int temp = 0;
244 /* Stop I2C transaction */
245 temp = readb(&i2c_regs->i2cr);
246 temp &= ~(I2CR_MSTA | I2CR_MTX);
247 writeb(temp, &i2c_regs->i2cr);
249 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
251 printf("%s:trigger stop failed\n", __func__);
252 /* Disable I2C controller */
253 writeb(0, &i2c_regs->i2cr);
257 * Send start signal, chip address and
258 * write register address
260 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
261 uchar chip, uint addr, int alen)
263 int ret = i2c_imx_start();
267 /* write slave address */
268 ret = tx_byte(i2c_regs, chip << 1);
273 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
284 * Read data from I2C device
286 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
288 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
293 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
297 temp = readb(&i2c_regs->i2cr);
299 writeb(temp, &i2c_regs->i2cr);
301 ret = tx_byte(i2c_regs, (chip << 1) | 1);
307 /* setup bus to read data */
308 temp = readb(&i2c_regs->i2cr);
309 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
311 temp |= I2CR_TX_NO_AK;
312 writeb(temp, &i2c_regs->i2cr);
313 writeb(0, &i2c_regs->i2sr);
314 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
317 for (i = 0; i < len; i++) {
318 ret = wait_for_sr_state(i2c_regs, ST_IIF);
325 * It must generate STOP before read I2DR to prevent
326 * controller from generating another clock cycle
328 if (i == (len - 1)) {
329 temp = readb(&i2c_regs->i2cr);
330 temp &= ~(I2CR_MSTA | I2CR_MTX);
331 writeb(temp, &i2c_regs->i2cr);
332 wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
333 } else if (i == (len - 2)) {
334 temp = readb(&i2c_regs->i2cr);
335 temp |= I2CR_TX_NO_AK;
336 writeb(temp, &i2c_regs->i2cr);
338 writeb(0, &i2c_regs->i2sr);
339 buf[i] = readb(&i2c_regs->i2dr);
348 * Write data to I2C device
350 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
352 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
356 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
360 for (i = 0; i < len; i++) {
361 ret = tx_byte(i2c_regs, buf[i]);
372 * Test if a chip at a given address responds (probe the chip)
374 int i2c_probe(uchar chip)
376 return i2c_write(chip, 0, 0, NULL, 0);