1 // SPDX-License-Identifier: GPL-2.0+
3 * i2c driver for Freescale i.MX series
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
8 * Based on i2c-imx.c from linux kernel:
9 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
10 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
11 * Copyright (C) 2007 RightHand Technologies, Inc.
12 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
19 #include <linux/errno.h>
20 #include <asm/mach-imx/mxc_i2c.h>
25 #include <dm/pinctrl.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define I2C_QUIRK_FLAG (1 << 0)
32 #define IMX_I2C_REGSHIFT 2
33 #define VF610_I2C_REGSHIFT 0
35 #define I2C_EARLY_INIT_INDEX 0
36 #ifdef CONFIG_SYS_I2C_IFDR_DIV
37 #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
39 #define I2C_IFDR_DIV_CONSERVATIVE 0x7e
49 #define I2CR_IIEN (1 << 6)
50 #define I2CR_MSTA (1 << 5)
51 #define I2CR_MTX (1 << 4)
52 #define I2CR_TX_NO_AK (1 << 3)
53 #define I2CR_RSTA (1 << 2)
55 #define I2SR_ICF (1 << 7)
56 #define I2SR_IBB (1 << 5)
57 #define I2SR_IAL (1 << 4)
58 #define I2SR_IIF (1 << 1)
59 #define I2SR_RX_NO_AK (1 << 0)
62 #define I2CR_IEN (0 << 7)
63 #define I2CR_IDIS (1 << 7)
64 #define I2SR_IIF_CLEAR (1 << 1)
66 #define I2CR_IEN (1 << 7)
67 #define I2CR_IDIS (0 << 7)
68 #define I2SR_IIF_CLEAR (0 << 1)
72 static u16 i2c_clk_div[60][2] = {
73 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
74 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
75 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
76 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
77 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
78 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
79 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
80 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
81 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
82 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
83 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
84 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
85 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
86 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
87 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
90 static u16 i2c_clk_div[50][2] = {
91 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
92 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
93 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
94 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
95 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
96 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
97 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
98 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
99 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
100 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
101 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
102 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
103 { 3072, 0x1E }, { 3840, 0x1F }
107 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
108 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
110 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
111 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
113 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
114 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
116 #ifndef CONFIG_SYS_MXC_I2C4_SPEED
117 #define CONFIG_SYS_MXC_I2C4_SPEED 100000
120 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
121 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
123 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
124 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
126 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
127 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
129 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
130 #define CONFIG_SYS_MXC_I2C4_SLAVE 0
134 * Calculate and set proper clock divider
136 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
138 unsigned int i2c_clk_rate;
142 #if defined(CONFIG_MX31)
143 struct clock_control_regs *sc_regs =
144 (struct clock_control_regs *)CCM_BASE;
146 /* start the required I2C clock */
147 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
151 /* Divider value calculation */
152 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
153 div = (i2c_clk_rate + rate - 1) / rate;
154 if (div < i2c_clk_div[0][0])
156 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
157 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
159 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
162 /* Store divider value */
169 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
171 ulong base = i2c_bus->base;
172 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
173 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
174 u8 idx = i2c_clk_div[clk_idx][1];
175 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
180 /* Store divider value */
181 writeb(idx, base + (IFDR << reg_shift));
184 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
185 writeb(0, base + (I2SR << reg_shift));
189 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
190 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
191 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
193 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
197 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
198 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
199 ulong base = i2c_bus->base;
200 ulong start_time = get_timer(0);
202 sr = readb(base + (I2SR << reg_shift));
205 writeb(sr | I2SR_IAL, base +
206 (I2SR << reg_shift));
208 writeb(sr & ~I2SR_IAL, base +
209 (I2SR << reg_shift));
210 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
211 __func__, sr, readb(base + (I2CR << reg_shift)),
215 if ((sr & (state >> 8)) == (unsigned char)state)
218 elapsed = get_timer(start_time);
219 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
222 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
223 sr, readb(base + (I2CR << reg_shift)), state);
227 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
230 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
231 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
232 ulong base = i2c_bus->base;
234 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
235 writeb(byte, base + (I2DR << reg_shift));
237 ret = wait_for_sr_state(i2c_bus, ST_IIF);
240 if (ret & I2SR_RX_NO_AK)
246 * Stub implementations for outer i2c slave operations.
248 void __i2c_force_reset_slave(void)
251 void i2c_force_reset_slave(void)
252 __attribute__((weak, alias("__i2c_force_reset_slave")));
255 * Stop I2C transaction
257 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
260 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
261 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
262 ulong base = i2c_bus->base;
263 unsigned int temp = readb(base + (I2CR << reg_shift));
265 temp &= ~(I2CR_MSTA | I2CR_MTX);
266 writeb(temp, base + (I2CR << reg_shift));
267 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
269 printf("%s:trigger stop failed\n", __func__);
273 * Send start signal, chip address and
274 * write register address
276 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
281 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
282 ulong base = i2c_bus->base;
283 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
285 /* Reset i2c slave */
286 i2c_force_reset_slave();
288 /* Enable I2C controller */
290 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
292 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
295 writeb(I2CR_IEN, base + (I2CR << reg_shift));
296 /* Wait for controller to be stable */
300 if (readb(base + (IADR << reg_shift)) == (chip << 1))
301 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
302 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
303 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
307 /* Start I2C transaction */
308 temp = readb(base + (I2CR << reg_shift));
310 writeb(temp, base + (I2CR << reg_shift));
312 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
316 temp |= I2CR_MTX | I2CR_TX_NO_AK;
317 writeb(temp, base + (I2CR << reg_shift));
320 /* write slave address */
321 ret = tx_byte(i2c_bus, chip << 1);
326 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
335 #ifndef CONFIG_DM_I2C
336 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
338 if (i2c_bus && i2c_bus->idle_bus_fn)
339 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
344 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
346 * scl-gpios: specify the gpio related to SCL pin
347 * sda-gpios: specify the gpio related to SDA pin
348 * add pinctrl to configure i2c pins to gpio function for i2c
349 * bus recovery, call it "gpio" state
352 * The i2c_idle_bus is an implementation following Linux Kernel.
354 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
356 struct udevice *bus = i2c_bus->bus;
357 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
358 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
361 ulong elapsed, start_time;
363 if (pinctrl_select_state(bus, "gpio")) {
364 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
366 * GPIO pinctrl for i2c force idle is not a must,
367 * but it is strongly recommended to be used.
368 * Because it can help you to recover from bad
369 * i2c bus state. Do not return failure, because
375 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
376 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
377 scl = dm_gpio_get_value(scl_gpio);
378 sda = dm_gpio_get_value(sda_gpio);
380 if ((sda & scl) == 1)
381 goto exit; /* Bus is idle already */
383 /* Send high and low on the SCL line */
384 for (i = 0; i < 9; i++) {
385 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
386 dm_gpio_set_value(scl_gpio, 0);
388 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
391 start_time = get_timer(0);
393 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
394 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
395 scl = dm_gpio_get_value(scl_gpio);
396 sda = dm_gpio_get_value(sda_gpio);
397 if ((sda & scl) == 1)
400 elapsed = get_timer(start_time);
401 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
403 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
409 pinctrl_select_state(bus, "default");
414 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
419 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
420 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
425 for (retry = 0; retry < 3; retry++) {
426 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
429 i2c_imx_stop(i2c_bus);
430 if (ret == -EREMOTEIO)
433 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
435 if (ret != -ERESTART)
436 /* Disable controller */
437 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
439 if (i2c_idle_bus(i2c_bus) < 0)
442 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
447 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
452 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
453 debug("write_data: ");
454 /* use rc for counter */
455 for (i = 0; i < len; ++i)
456 debug(" 0x%02x", buf[i]);
459 for (i = 0; i < len; i++) {
460 ret = tx_byte(i2c_bus, buf[i]);
462 debug("i2c_write_data(): rc=%d\n", ret);
470 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
476 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
477 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
478 ulong base = i2c_bus->base;
480 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
482 /* setup bus to read data */
483 temp = readb(base + (I2CR << reg_shift));
484 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
486 temp |= I2CR_TX_NO_AK;
487 writeb(temp, base + (I2CR << reg_shift));
488 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
489 /* dummy read to clear ICF */
490 readb(base + (I2DR << reg_shift));
493 for (i = 0; i < len; i++) {
494 ret = wait_for_sr_state(i2c_bus, ST_IIF);
496 debug("i2c_read_data(): ret=%d\n", ret);
497 i2c_imx_stop(i2c_bus);
502 * It must generate STOP before read I2DR to prevent
503 * controller from generating another clock cycle
505 if (i == (len - 1)) {
506 i2c_imx_stop(i2c_bus);
507 } else if (i == (len - 2)) {
508 temp = readb(base + (I2CR << reg_shift));
509 temp |= I2CR_TX_NO_AK;
510 writeb(temp, base + (I2CR << reg_shift));
512 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
513 buf[i] = readb(base + (I2DR << reg_shift));
516 /* reuse ret for counter*/
517 for (ret = 0; ret < len; ++ret)
518 debug(" 0x%02x", buf[ret]);
521 i2c_imx_stop(i2c_bus);
525 #ifndef CONFIG_DM_I2C
527 * Read data from I2C device
529 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
530 int alen, u8 *buf, int len)
534 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
535 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
536 ulong base = i2c_bus->base;
538 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
543 temp = readb(base + (I2CR << reg_shift));
545 writeb(temp, base + (I2CR << reg_shift));
548 ret = tx_byte(i2c_bus, (chip << 1) | 1);
550 i2c_imx_stop(i2c_bus);
554 ret = i2c_read_data(i2c_bus, chip, buf, len);
556 i2c_imx_stop(i2c_bus);
561 * Write data to I2C device
563 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
564 int alen, const u8 *buf, int len)
568 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
572 ret = i2c_write_data(i2c_bus, chip, buf, len);
574 i2c_imx_stop(i2c_bus);
579 #if !defined(I2C2_BASE_ADDR)
580 #define I2C2_BASE_ADDR 0
583 #if !defined(I2C3_BASE_ADDR)
584 #define I2C3_BASE_ADDR 0
587 #if !defined(I2C4_BASE_ADDR)
588 #define I2C4_BASE_ADDR 0
591 #if !defined(I2C5_BASE_ADDR)
592 #define I2C5_BASE_ADDR 0
595 #if !defined(I2C6_BASE_ADDR)
596 #define I2C6_BASE_ADDR 0
599 #if !defined(I2C7_BASE_ADDR)
600 #define I2C7_BASE_ADDR 0
603 #if !defined(I2C8_BASE_ADDR)
604 #define I2C8_BASE_ADDR 0
607 static struct mxc_i2c_bus mxc_i2c_buses[] = {
608 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
609 defined(CONFIG_FSL_LAYERSCAPE)
610 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
611 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
612 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
613 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
614 { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
615 { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
616 { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
617 { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
619 { 0, I2C1_BASE_ADDR, 0 },
620 { 1, I2C2_BASE_ADDR, 0 },
621 { 2, I2C3_BASE_ADDR, 0 },
622 { 3, I2C4_BASE_ADDR, 0 },
623 { 4, I2C5_BASE_ADDR, 0 },
624 { 5, I2C6_BASE_ADDR, 0 },
625 { 6, I2C7_BASE_ADDR, 0 },
626 { 7, I2C8_BASE_ADDR, 0 },
630 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
632 return &mxc_i2c_buses[adap->hwadapnr];
635 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
636 uint addr, int alen, uint8_t *buffer,
639 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
642 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
643 uint addr, int alen, uint8_t *buffer,
646 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
650 * Test if a chip at a given address responds (probe the chip)
652 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
654 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
657 int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
661 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
662 __attribute__((weak, alias("__enable_i2c_clk")));
664 void bus_i2c_init(int index, int speed, int unused,
665 int (*idle_bus_fn)(void *p), void *idle_bus_data)
669 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
670 debug("Error i2c index\n");
675 * Warning: Be careful to allow the assignment to a static
676 * variable here. This function could be called while U-Boot is
677 * still running in flash memory. So such assignment is equal
678 * to write data to flash without erasing.
681 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
683 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
685 ret = enable_i2c_clk(1, index);
687 debug("I2C-%d clk fail to enable.\n", index);
691 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
695 * Early init I2C for prepare read the clk through I2C.
697 void i2c_early_init_f(void)
699 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
700 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
701 & I2C_QUIRK_FLAG ? true : false;
702 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
704 /* Set I2C divider value */
705 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
707 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
708 writeb(0, base + (I2SR << reg_shift));
710 writeb(I2CR_IEN, base + (I2CR << reg_shift));
716 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
718 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
724 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
726 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
730 * Register mxc i2c adapters
732 #ifdef CONFIG_SYS_I2C_MXC_I2C1
733 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
734 mxc_i2c_read, mxc_i2c_write,
735 mxc_i2c_set_bus_speed,
736 CONFIG_SYS_MXC_I2C1_SPEED,
737 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
740 #ifdef CONFIG_SYS_I2C_MXC_I2C2
741 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
742 mxc_i2c_read, mxc_i2c_write,
743 mxc_i2c_set_bus_speed,
744 CONFIG_SYS_MXC_I2C2_SPEED,
745 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
748 #ifdef CONFIG_SYS_I2C_MXC_I2C3
749 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
750 mxc_i2c_read, mxc_i2c_write,
751 mxc_i2c_set_bus_speed,
752 CONFIG_SYS_MXC_I2C3_SPEED,
753 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
756 #ifdef CONFIG_SYS_I2C_MXC_I2C4
757 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
758 mxc_i2c_read, mxc_i2c_write,
759 mxc_i2c_set_bus_speed,
760 CONFIG_SYS_MXC_I2C4_SPEED,
761 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
764 #ifdef CONFIG_SYS_I2C_MXC_I2C5
765 U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
766 mxc_i2c_read, mxc_i2c_write,
767 mxc_i2c_set_bus_speed,
768 CONFIG_SYS_MXC_I2C5_SPEED,
769 CONFIG_SYS_MXC_I2C5_SLAVE, 4)
772 #ifdef CONFIG_SYS_I2C_MXC_I2C6
773 U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
774 mxc_i2c_read, mxc_i2c_write,
775 mxc_i2c_set_bus_speed,
776 CONFIG_SYS_MXC_I2C6_SPEED,
777 CONFIG_SYS_MXC_I2C6_SLAVE, 5)
780 #ifdef CONFIG_SYS_I2C_MXC_I2C7
781 U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
782 mxc_i2c_read, mxc_i2c_write,
783 mxc_i2c_set_bus_speed,
784 CONFIG_SYS_MXC_I2C7_SPEED,
785 CONFIG_SYS_MXC_I2C7_SLAVE, 6)
788 #ifdef CONFIG_SYS_I2C_MXC_I2C8
789 U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
790 mxc_i2c_read, mxc_i2c_write,
791 mxc_i2c_set_bus_speed,
792 CONFIG_SYS_MXC_I2C8_SPEED,
793 CONFIG_SYS_MXC_I2C8_SLAVE, 7)
798 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
800 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
802 return bus_i2c_set_bus_speed(i2c_bus, speed);
805 static int mxc_i2c_probe(struct udevice *bus)
807 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
808 const void *fdt = gd->fdt_blob;
809 int node = dev_of_offset(bus);
813 i2c_bus->driver_data = dev_get_driver_data(bus);
815 addr = devfdt_get_addr(bus);
816 if (addr == FDT_ADDR_T_NONE)
819 i2c_bus->base = addr;
820 i2c_bus->index = bus->seq;
824 ret = enable_i2c_clk(1, bus->seq);
829 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
830 * Use gpio to force bus idle when necessary.
832 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
834 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
836 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
837 "scl-gpios", 0, &i2c_bus->scl_gpio,
839 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
840 "sda-gpios", 0, &i2c_bus->sda_gpio,
842 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
843 !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
845 dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
850 ret = i2c_idle_bus(i2c_bus);
853 enable_i2c_clk(0, bus->seq);
858 * Pinmux settings are in board file now, until pinmux is supported,
859 * we can set pinmux here in probe function.
862 debug("i2c : controller bus %d at %lu , speed %d: ",
863 bus->seq, i2c_bus->base,
869 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
873 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
875 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
877 debug("%s failed, ret = %d\n", __func__, ret);
881 i2c_imx_stop(i2c_bus);
886 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
888 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
890 ulong base = i2c_bus->base;
891 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
892 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
895 * Here the 3rd parameter addr and the 4th one alen are set to 0,
896 * because here we only want to send out chip address. The register
897 * address is wrapped in msg.
899 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
901 debug("i2c_init_transfer error: %d\n", ret);
905 for (; nmsgs > 0; nmsgs--, msg++) {
906 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
907 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
908 if (msg->flags & I2C_M_RD)
909 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
912 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
918 ret = readb(base + (I2CR << reg_shift));
920 writeb(ret, base + (I2CR << reg_shift));
922 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
924 i2c_imx_stop(i2c_bus);
932 debug("i2c_write: error sending\n");
934 i2c_imx_stop(i2c_bus);
939 static const struct dm_i2c_ops mxc_i2c_ops = {
940 .xfer = mxc_i2c_xfer,
941 .probe_chip = mxc_i2c_probe_chip,
942 .set_bus_speed = mxc_i2c_set_bus_speed,
945 static const struct udevice_id mxc_i2c_ids[] = {
946 { .compatible = "fsl,imx21-i2c", },
947 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
951 U_BOOT_DRIVER(i2c_mxc) = {
954 .of_match = mxc_i2c_ids,
955 .probe = mxc_i2c_probe,
956 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),