2 * i2c driver for Freescale i.MX series
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/errno.h>
49 #define I2CR_IEN (1 << 7)
50 #define I2CR_IIEN (1 << 6)
51 #define I2CR_MSTA (1 << 5)
52 #define I2CR_MTX (1 << 4)
53 #define I2CR_TX_NO_AK (1 << 3)
54 #define I2CR_RSTA (1 << 2)
56 #define I2SR_ICF (1 << 7)
57 #define I2SR_IBB (1 << 5)
58 #define I2SR_IAL (1 << 4)
59 #define I2SR_IIF (1 << 1)
60 #define I2SR_RX_NO_AK (1 << 0)
62 #ifdef CONFIG_SYS_I2C_BASE
63 #define I2C_BASE CONFIG_SYS_I2C_BASE
65 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
68 static u16 i2c_clk_div[50][2] = {
69 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
70 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
71 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
72 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
73 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
74 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
75 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
76 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
77 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
78 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
79 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
80 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
81 { 3072, 0x1E }, { 3840, 0x1F }
85 * Calculate and set proper clock divider
87 static uint8_t i2c_imx_get_clk(unsigned int rate)
89 unsigned int i2c_clk_rate;
93 #if defined(CONFIG_MX31)
94 struct clock_control_regs *sc_regs =
95 (struct clock_control_regs *)CCM_BASE;
97 /* start the required I2C clock */
98 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
102 /* Divider value calculation */
103 i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK);
104 div = (i2c_clk_rate + rate - 1) / rate;
105 if (div < i2c_clk_div[0][0])
107 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
108 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
110 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
113 /* Store divider value */
120 void i2c_init(int speed, int unused)
122 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
123 u8 clk_idx = i2c_imx_get_clk(speed);
124 u8 idx = i2c_clk_div[clk_idx][1];
126 /* Store divider value */
127 writeb(idx, &i2c_regs->ifdr);
130 writeb(0, &i2c_regs->i2cr);
131 writeb(0, &i2c_regs->i2sr);
137 int i2c_set_bus_speed(unsigned int speed)
146 unsigned int i2c_get_bus_speed(void)
148 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
149 u8 clk_idx = readb(&i2c_regs->ifdr);
152 for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
155 return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
158 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
159 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
160 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
162 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
166 ulong start_time = get_timer(0);
168 sr = readb(&i2c_regs->i2sr);
170 writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
171 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
172 __func__, sr, readb(&i2c_regs->i2cr), state);
175 if ((sr & (state >> 8)) == (unsigned char)state)
178 elapsed = get_timer(start_time);
179 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
182 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
183 sr, readb(&i2c_regs->i2cr), state);
187 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
191 writeb(0, &i2c_regs->i2sr);
192 writeb(byte, &i2c_regs->i2dr);
193 ret = wait_for_sr_state(i2c_regs, ST_IIF);
196 if (ret & I2SR_RX_NO_AK)
202 * Stop I2C transaction
204 void i2c_imx_stop(void)
207 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
208 unsigned int temp = readb(&i2c_regs->i2cr);
210 temp &= ~(I2CR_MSTA | I2CR_MTX);
211 writeb(temp, &i2c_regs->i2cr);
212 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
214 printf("%s:trigger stop failed\n", __func__);
218 * Send start signal, chip address and
219 * write register address
221 static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
222 uchar chip, uint addr, int alen)
227 /* Enable I2C controller */
228 if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
229 writeb(I2CR_IEN, &i2c_regs->i2cr);
230 /* Wait for controller to be stable */
233 if (readb(&i2c_regs->iadr) == (chip << 1))
234 writeb((chip << 1) ^ 2, &i2c_regs->iadr);
235 writeb(0, &i2c_regs->i2sr);
236 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
240 /* Start I2C transaction */
241 temp = readb(&i2c_regs->i2cr);
243 writeb(temp, &i2c_regs->i2cr);
245 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
249 temp |= I2CR_MTX | I2CR_TX_NO_AK;
250 writeb(temp, &i2c_regs->i2cr);
252 /* write slave address */
253 ret = tx_byte(i2c_regs, chip << 1);
258 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
265 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
266 uchar chip, uint addr, int alen)
270 for (retry = 0; retry < 3; retry++) {
271 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
278 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
280 if (ret != -ERESTART)
281 writeb(0, &i2c_regs->i2cr); /* Disable controller */
284 printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
289 * Read data from I2C device
291 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
293 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
298 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
302 temp = readb(&i2c_regs->i2cr);
304 writeb(temp, &i2c_regs->i2cr);
306 ret = tx_byte(i2c_regs, (chip << 1) | 1);
312 /* setup bus to read data */
313 temp = readb(&i2c_regs->i2cr);
314 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
316 temp |= I2CR_TX_NO_AK;
317 writeb(temp, &i2c_regs->i2cr);
318 writeb(0, &i2c_regs->i2sr);
319 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
322 for (i = 0; i < len; i++) {
323 ret = wait_for_sr_state(i2c_regs, ST_IIF);
330 * It must generate STOP before read I2DR to prevent
331 * controller from generating another clock cycle
333 if (i == (len - 1)) {
335 } else if (i == (len - 2)) {
336 temp = readb(&i2c_regs->i2cr);
337 temp |= I2CR_TX_NO_AK;
338 writeb(temp, &i2c_regs->i2cr);
340 writeb(0, &i2c_regs->i2sr);
341 buf[i] = readb(&i2c_regs->i2dr);
350 * Write data to I2C device
352 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
354 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
358 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
362 for (i = 0; i < len; i++) {
363 ret = tx_byte(i2c_regs, buf[i]);
374 * Test if a chip at a given address responds (probe the chip)
376 int i2c_probe(uchar chip)
378 return i2c_write(chip, 0, 0, NULL, 0);