git.sur5r.net Git - u-boot/blob - drivers/i2c/mxs_i2c.c

   1 /*
   2  * Freescale i.MX28 I2C Driver
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * Partly based on Linux kernel i2c-mxs.c driver:
   8  * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
   9  *
  10  * Which was based on a (non-working) driver which was:
  11  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <malloc.h>
  18 #include <i2c.h>
  19 #include <asm/errno.h>
  20 #include <asm/io.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/imx-regs.h>
  23 #include <asm/arch/sys_proto.h>
  24
  25 #define MXS_I2C_MAX_TIMEOUT     1000000
  26
  27 static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap)
  28 {
  29         return (struct mxs_i2c_regs *)MXS_I2C0_BASE;
  30 }
  31
  32 static unsigned int mxs_i2c_get_bus_speed(void)
  33 {
  34         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(NULL);
  35         uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
  36         uint32_t timing0;
  37
  38         timing0 = readl(&i2c_regs->hw_i2c_timing0);
  39         /*
  40          * This is a reverse version of the algorithm presented in
  41          * i2c_set_bus_speed(). Please refer there for details.
  42          */
  43         return clk / ((((timing0 >> 16) - 3) * 2) + 38);
  44 }
  45
  46 static void mxs_i2c_reset(void)
  47 {
  48         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(NULL);
  49         int ret;
  50         int speed = mxs_i2c_get_bus_speed();
  51
  52         ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
  53         if (ret) {
  54                 debug("MXS I2C: Block reset timeout\n");
  55                 return;
  56         }
  57
  58         writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
  59                 I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
  60                 I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
  61                 &i2c_regs->hw_i2c_ctrl1_clr);
  62
  63         writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
  64
  65         i2c_set_bus_speed(speed);
  66 }
  67
  68 static void mxs_i2c_setup_read(uint8_t chip, int len)
  69 {
  70         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(NULL);
  71
  72         writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
  73                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
  74                 (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
  75                 &i2c_regs->hw_i2c_queuecmd);
  76
  77         writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);
  78
  79         writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
  80                 (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
  81                 I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
  82
  83         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
  84 }
  85
  86 static int mxs_i2c_write(uchar chip, uint addr, int alen,
  87                         uchar *buf, int blen, int stop)
  88 {
  89         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(NULL);
  90         uint32_t data, tmp;
  91         int i, remain, off;
  92         int timeout = MXS_I2C_MAX_TIMEOUT;
  93
  94         if ((alen > 4) || (alen == 0)) {
  95                 debug("MXS I2C: Invalid address length\n");
  96                 return -EINVAL;
  97         }
  98
  99         if (stop)
 100                 stop = I2C_QUEUECMD_POST_SEND_STOP;
 101
 102         writel(I2C_QUEUECMD_PRE_SEND_START |
 103                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
 104                 ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
 105                 &i2c_regs->hw_i2c_queuecmd);
 106
 107         data = (chip << 1) << 24;
 108
 109         for (i = 0; i < alen; i++) {
 110                 data >>= 8;
 111                 data |= ((char *)&addr)[alen - i - 1] << 24;
 112                 if ((i & 3) == 2)
 113                         writel(data, &i2c_regs->hw_i2c_data);
 114         }
 115
 116         off = i;
 117         for (; i < off + blen; i++) {
 118                 data >>= 8;
 119                 data |= buf[i - off] << 24;
 120                 if ((i & 3) == 2)
 121                         writel(data, &i2c_regs->hw_i2c_data);
 122         }
 123
 124         remain = 24 - ((i & 3) * 8);
 125         if (remain)
 126                 writel(data >> remain, &i2c_regs->hw_i2c_data);
 127
 128         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
 129
 130         while (--timeout) {
 131                 tmp = readl(&i2c_regs->hw_i2c_queuestat);
 132                 if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY)
 133                         break;
 134         }
 135
 136         if (!timeout) {
 137                 debug("MXS I2C: Failed transmitting data!\n");
 138                 return -EINVAL;
 139         }
 140
 141         return 0;
 142 }
 143
 144 static int mxs_i2c_wait_for_ack(void)
 145 {
 146         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(NULL);
 147         uint32_t tmp;
 148         int timeout = MXS_I2C_MAX_TIMEOUT;
 149
 150         for (;;) {
 151                 tmp = readl(&i2c_regs->hw_i2c_ctrl1);
 152                 if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
 153                         debug("MXS I2C: No slave ACK\n");
 154                         goto err;
 155                 }
 156
 157                 if (tmp & (
 158                         I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
 159                         I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
 160                         debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
 161                         goto err;
 162                 }
 163
 164                 if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
 165                         break;
 166
 167                 if (!timeout--) {
 168                         debug("MXS I2C: Operation timed out\n");
 169                         goto err;
 170                 }
 171
 172                 udelay(1);
 173         }
 174
 175         return 0;
 176
 177 err:
 178         mxs_i2c_reset();
 179         return 1;
 180 }
 181
 182 static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip,
 183                            uint addr, int alen, uint8_t *buffer,
 184                            int len)
 185 {
 186         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(NULL);
 187         uint32_t tmp = 0;
 188         int timeout = MXS_I2C_MAX_TIMEOUT;
 189         int ret;
 190         int i;
 191
 192         ret = mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
 193         if (ret) {
 194                 debug("MXS I2C: Failed writing address\n");
 195                 return ret;
 196         }
 197
 198         ret = mxs_i2c_wait_for_ack();
 199         if (ret) {
 200                 debug("MXS I2C: Failed writing address\n");
 201                 return ret;
 202         }
 203
 204         mxs_i2c_setup_read(chip, len);
 205         ret = mxs_i2c_wait_for_ack();
 206         if (ret) {
 207                 debug("MXS I2C: Failed reading address\n");
 208                 return ret;
 209         }
 210
 211         for (i = 0; i < len; i++) {
 212                 if (!(i & 3)) {
 213                         while (--timeout) {
 214                                 tmp = readl(&i2c_regs->hw_i2c_queuestat);
 215                                 if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
 216                                         break;
 217                         }
 218
 219                         if (!timeout) {
 220                                 debug("MXS I2C: Failed receiving data!\n");
 221                                 return -ETIMEDOUT;
 222                         }
 223
 224                         tmp = readl(&i2c_regs->hw_i2c_queuedata);
 225                 }
 226                 buffer[i] = tmp & 0xff;
 227                 tmp >>= 8;
 228         }
 229
 230         return 0;
 231 }
 232
 233 static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip,
 234                             uint addr, int alen, uint8_t *buffer,
 235                             int len)
 236 {
 237         int ret;
 238         ret = mxs_i2c_write(chip, addr, alen, buffer, len, 1);
 239         if (ret) {
 240                 debug("MXS I2C: Failed writing address\n");
 241                 return ret;
 242         }
 243
 244         ret = mxs_i2c_wait_for_ack();
 245         if (ret)
 246                 debug("MXS I2C: Failed writing address\n");
 247
 248         return ret;
 249 }
 250
 251 static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 252 {
 253         int ret;
 254         ret = mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
 255         if (!ret)
 256                 ret = mxs_i2c_wait_for_ack();
 257         mxs_i2c_reset();
 258         return ret;
 259 }
 260
 261 static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 262 {
 263         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(NULL);
 264         /*
 265          * The timing derivation algorithm. There is no documentation for this
 266          * algorithm available, it was derived by using the scope and fiddling
 267          * with constants until the result observed on the scope was good enough
 268          * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
 269          * possible to assume the algorithm works for other frequencies as well.
 270          *
 271          * Note it was necessary to cap the frequency on both ends as it's not
 272          * possible to configure completely arbitrary frequency for the I2C bus
 273          * clock.
 274          */
 275         uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
 276         uint32_t base = ((clk / speed) - 38) / 2;
 277         uint16_t high_count = base + 3;
 278         uint16_t low_count = base - 3;
 279         uint16_t rcv_count = (high_count * 3) / 4;
 280         uint16_t xmit_count = low_count / 4;
 281
 282         if (speed > 540000) {
 283                 printf("MXS I2C: Speed too high (%d Hz)\n", speed);
 284                 return -EINVAL;
 285         }
 286
 287         if (speed < 12000) {
 288                 printf("MXS I2C: Speed too low (%d Hz)\n", speed);
 289                 return -EINVAL;
 290         }
 291
 292         writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
 293         writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
 294
 295         writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
 296                 (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
 297                 &i2c_regs->hw_i2c_timing2);
 298
 299         return 0;
 300 }
 301
 302 static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 303 {
 304         mxs_i2c_reset();
 305         i2c_set_bus_speed(speed);
 306
 307         return;
 308 }
 309
 310 U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe,
 311                          mxs_i2c_if_read, mxs_i2c_if_write,
 312                          mxs_i2c_set_bus_speed,
 313                          CONFIG_SYS_I2C_SPEED, 0, 0)