4 * Copyright (c) 2004 Texas Instruments
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
25 #include <asm/arch/i2c.h>
28 #include "omap24xx_i2c.h"
30 DECLARE_GLOBAL_DATA_PTR;
32 #define I2C_STAT_TIMEO (1 << 31)
33 #define I2C_TIMEOUT 10
35 static u32 wait_for_bb(void);
36 static u32 wait_for_status_mask(u16 mask);
37 static void flush_fifo(void);
40 * For SPL boot some boards need i2c before SDRAM is initialised so force
41 * variables to live in SRAM
43 static struct i2c __attribute__((section (".data"))) *i2c_base =
44 (struct i2c *)I2C_DEFAULT_BASE;
45 static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
46 { [0 ... (I2C_BUS_MAX-1)] = 0 };
47 static unsigned int __attribute__((section (".data"))) current_bus = 0;
49 void i2c_init(int speed, int slaveadd)
51 int psc, fsscll, fssclh;
52 int hsscll = 0, hssclh = 0;
55 /* Only handle standard, fast and high speeds */
56 if ((speed != OMAP_I2C_STANDARD) &&
57 (speed != OMAP_I2C_FAST_MODE) &&
58 (speed != OMAP_I2C_HIGH_SPEED)) {
59 printf("Error : I2C unsupported speed %d\n", speed);
63 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
65 if (psc < I2C_PSC_MIN) {
66 printf("Error : I2C unsupported prescalar %d\n", psc);
70 if (speed == OMAP_I2C_HIGH_SPEED) {
73 /* For first phase of HS mode */
74 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
75 (2 * OMAP_I2C_FAST_MODE);
77 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
78 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
79 if (((fsscll < 0) || (fssclh < 0)) ||
80 ((fsscll > 255) || (fssclh > 255))) {
81 puts("Error : I2C initializing first phase clock\n");
85 /* For second phase of HS mode */
86 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
88 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
89 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
90 if (((fsscll < 0) || (fssclh < 0)) ||
91 ((fsscll > 255) || (fssclh > 255))) {
92 puts("Error : I2C initializing second phase clock\n");
96 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
97 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
100 /* Standard and fast speed */
101 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
103 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
104 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
105 if (((fsscll < 0) || (fssclh < 0)) ||
106 ((fsscll > 255) || (fssclh > 255))) {
107 puts("Error : I2C initializing clock\n");
111 scll = (unsigned int)fsscll;
112 sclh = (unsigned int)fssclh;
115 if (gd->flags & GD_FLG_RELOC)
116 bus_initialized[current_bus] = 1;
118 if (readw(&i2c_base->con) & I2C_CON_EN) {
119 writew(0, &i2c_base->con);
123 writew(psc, &i2c_base->psc);
124 writew(scll, &i2c_base->scll);
125 writew(sclh, &i2c_base->sclh);
128 writew(slaveadd, &i2c_base->oa);
129 writew(I2C_CON_EN, &i2c_base->con);
131 /* have to enable intrrupts or OMAP i2c module doesn't work */
132 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
133 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
136 writew(0xFFFF, &i2c_base->stat);
137 writew(0, &i2c_base->cnt);
140 static void flush_fifo(void)
143 /* note: if you try and read data when its not there or ready
144 * you get a bus error
147 stat = readw(&i2c_base->stat);
148 if (stat == I2C_STAT_RRDY) {
149 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
150 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX)
151 readb(&i2c_base->data);
153 readw(&i2c_base->data);
155 writew(I2C_STAT_RRDY, &i2c_base->stat);
162 int i2c_probe(uchar chip)
165 int res = 1; /* default = fail */
167 if (chip == readw(&i2c_base->oa))
170 /* wait until bus not busy */
171 status = wait_for_bb();
172 /* exit on BUS busy */
173 if (status & I2C_STAT_TIMEO)
176 /* try to write one byte */
177 writew(1, &i2c_base->cnt);
178 /* set slave address */
179 writew(chip, &i2c_base->sa);
180 /* stop bit needed here */
181 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT
182 | I2C_CON_STP, &i2c_base->con);
183 /* enough delay for the NACK bit set */
186 if (!(readw(&i2c_base->stat) & I2C_STAT_NACK)) {
187 res = 0; /* success case */
189 writew(0xFFFF, &i2c_base->stat);
191 /* failure, clear sources*/
192 writew(0xFFFF, &i2c_base->stat);
194 writew(readw(&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
195 status = wait_for_bb();
196 /* exit on BUS busy */
197 if (status & I2C_STAT_TIMEO)
201 /* don't allow any more data in... we don't want it. */
202 writew(0, &i2c_base->cnt);
203 writew(0xFFFF, &i2c_base->stat);
207 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
209 int i2c_error = 0, i;
212 if ((alen > 2) || (alen < 0))
216 if (addr + len > 256)
218 } else if (addr + len > 0xFFFF) {
222 /* wait until bus not busy */
223 status = wait_for_bb();
225 /* exit on BUS busy */
226 if (status & I2C_STAT_TIMEO)
229 writew((alen & 0xFF), &i2c_base->cnt);
230 /* set slave address */
231 writew(chip, &i2c_base->sa);
232 /* Clear the Tx & Rx FIFOs */
233 writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR |
234 I2C_TXFIFO_CLEAR), &i2c_base->buf);
235 /* no stop bit needed here */
236 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
237 I2C_CON_STT, &i2c_base->con);
239 /* wait for Transmit ready condition */
240 status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK);
242 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO))
246 if (status & I2C_STAT_XRDY) {
249 /* Send address MSByte */
250 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
251 defined(CONFIG_AM33XX)
252 writew(((addr >> 8) & 0xFF), &i2c_base->data);
254 /* Clearing XRDY event */
255 writew((status & I2C_STAT_XRDY),
257 /* wait for Transmit ready condition */
258 status = wait_for_status_mask(I2C_STAT_XRDY |
261 if (status & (I2C_STAT_NACK |
268 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
269 defined(CONFIG_AM33XX)
270 /* Send address LSByte */
271 writew((addr & 0xFF), &i2c_base->data);
273 /* Send address Short word */
274 writew((addr & 0xFFFF), &i2c_base->data);
276 /* Clearing XRDY event */
277 writew((status & I2C_STAT_XRDY),
279 /*wait for Transmit ready condition */
280 status = wait_for_status_mask(I2C_STAT_ARDY |
283 if (status & (I2C_STAT_NACK |
293 /* Wait for ARDY to set */
294 status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK
298 /* set slave address */
299 writew(chip, &i2c_base->sa);
300 writew((len & 0xFF), &i2c_base->cnt);
301 /* Clear the Tx & Rx FIFOs */
302 writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR |
303 I2C_TXFIFO_CLEAR), &i2c_base->buf);
304 /* need stop bit here */
305 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
308 for (i = 0; i < len; i++) {
309 /* wait for Receive condition */
310 status = wait_for_status_mask(I2C_STAT_RRDY |
312 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO)) {
317 if (status & I2C_STAT_RRDY) {
318 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
319 defined(CONFIG_AM33XX)
320 buffer[i] = readb(&i2c_base->data);
322 *((u16 *)&buffer[i]) =
323 readw(&i2c_base->data) & 0xFFFF;
326 writew((status & I2C_STAT_RRDY),
335 /* Wait for ARDY to set */
336 status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK
340 writew(0, &i2c_base->con);
344 writew(I2C_CON_EN, &i2c_base->con);
346 while (readw(&i2c_base->stat)
347 || (readw(&i2c_base->con) & I2C_CON_MST)) {
349 writew(0xFFFF, &i2c_base->stat);
352 writew(I2C_CON_EN, &i2c_base->con);
354 writew(0xFFFF, &i2c_base->stat);
355 writew(0, &i2c_base->cnt);
360 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
363 int i, i2c_error = 0;
371 if (addr + len > 256)
373 } else if (addr + len > 0xFFFF) {
377 /* wait until bus not busy */
378 status = wait_for_bb();
380 /* exiting on BUS busy */
381 if (status & I2C_STAT_TIMEO)
384 writelen = (len & 0xFFFF) + alen;
387 writew((writelen & 0xFFFF), &i2c_base->cnt);
388 /* Clear the Tx & Rx FIFOs */
389 writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR |
390 I2C_TXFIFO_CLEAR), &i2c_base->buf);
391 /* set slave address */
392 writew(chip, &i2c_base->sa);
393 /* stop bit needed here */
394 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
395 I2C_CON_STP, &i2c_base->con);
397 /* wait for Transmit ready condition */
398 status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK);
400 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO))
404 if (status & I2C_STAT_XRDY) {
406 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
407 defined(CONFIG_AM33XX)
409 /* send out MSB byte */
410 writeb(((addr >> 8) & 0xFF), &i2c_base->data);
412 writeb((addr & 0xFFFF), &i2c_base->data);
415 /* Clearing XRDY event */
416 writew((status & I2C_STAT_XRDY),
418 /*waiting for Transmit ready * condition */
419 status = wait_for_status_mask(I2C_STAT_XRDY |
422 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO)) {
427 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
428 defined(CONFIG_AM33XX)
429 /* send out MSB byte */
430 writeb((addr & 0xFF), &i2c_base->data);
432 writew(((buffer[0] << 8) | (addr & 0xFF)),
437 /* Clearing XRDY event */
438 writew((status & I2C_STAT_XRDY), &i2c_base->stat);
441 /* waiting for Transmit ready condition */
442 status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK);
444 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO))
448 for (i = ((alen > 1) ? 0 : 1); i < len; i++) {
449 if (status & I2C_STAT_XRDY) {
450 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
451 defined(CONFIG_AM33XX)
452 writeb((buffer[i] & 0xFF),
455 writew((((buffer[i] << 8) |
456 buffer[i + 1]) & 0xFFFF),
462 /* Clearing XRDY event */
463 writew((status & I2C_STAT_XRDY),
465 /* waiting for XRDY condition */
466 status = wait_for_status_mask(
470 if (status & (I2C_STAT_NACK |
475 if (status & I2C_STAT_ARDY)
481 status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK |
484 if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO))
488 writew(0, &i2c_base->con);
495 writew(I2C_CON_EN, &i2c_base->con);
496 while ((status = readw(&i2c_base->stat)) ||
497 (readw(&i2c_base->con) & I2C_CON_MST)) {
499 /* have to read to clear intrrupt */
500 writew(0xFFFF, &i2c_base->stat);
502 /* better leave with error than hang */
508 writew(0xFFFF, &i2c_base->stat);
509 writew(0, &i2c_base->cnt);
513 static u32 wait_for_bb(void)
515 int timeout = I2C_TIMEOUT;
518 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
519 writew(stat, &i2c_base->stat);
524 printf("timed out in wait_for_bb: I2C_STAT=%x\n",
525 readw(&i2c_base->stat));
526 stat |= I2C_STAT_TIMEO;
528 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
532 static u32 wait_for_status_mask(u16 mask)
535 int timeout = I2C_TIMEOUT;
539 status = readw(&i2c_base->stat);
540 } while (!(status & mask) && timeout--);
543 printf("timed out in wait_for_status_mask: I2C_STAT=%x\n",
544 readw(&i2c_base->stat));
545 writew(0xFFFF, &i2c_base->stat);
546 status |= I2C_STAT_TIMEO;
551 int i2c_set_bus_num(unsigned int bus)
553 if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
554 printf("Bad bus: %d\n", bus);
560 i2c_base = (struct i2c *)I2C_BASE3;
564 i2c_base = (struct i2c *)I2C_BASE2;
566 i2c_base = (struct i2c *)I2C_BASE1;
570 if (!bus_initialized[current_bus])
571 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
576 int i2c_get_bus_num(void)
578 return (int) current_bus;