2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
3 * Copyright (c) 2010-2011 NVIDIA Corporation
4 * NVIDIA Corporation <www.nvidia.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/clock.h>
30 #include <asm/arch/funcmux.h>
31 #include <asm/arch/gpio.h>
32 #include <asm/arch/pinmux.h>
33 #include <asm/arch-tegra/clk_rst.h>
34 #include <asm/arch-tegra/tegra_i2c.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 /* Information about i2c controller */
41 enum periph_id periph_id;
44 struct i2c_control *control;
45 struct i2c_ctlr *regs;
46 int is_dvc; /* DVC type, rather than I2C */
47 int is_scs; /* single clock source (T114+) */
48 int inited; /* bus is inited */
51 static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS];
53 static void set_packet_mode(struct i2c_bus *i2c_bus)
57 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
59 if (i2c_bus->is_dvc) {
60 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
62 writel(config, &dvc->cnfg);
64 writel(config, &i2c_bus->regs->cnfg);
66 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
67 * issues, i.e., some slaves may be wrongly detected.
69 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
73 static void i2c_reset_controller(struct i2c_bus *i2c_bus)
75 /* Reset I2C controller. */
76 reset_periph(i2c_bus->periph_id, 1);
78 /* re-program config register to packet mode */
79 set_packet_mode(i2c_bus);
82 static void i2c_init_controller(struct i2c_bus *i2c_bus)
85 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
86 * here, in section 23.3.1, but in fact we seem to need a factor of
87 * 16 to get the right frequency.
89 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
90 i2c_bus->speed * 2 * 8);
92 if (i2c_bus->is_scs) {
94 * T114 I2C went to a single clock source for standard/fast and
95 * HS clock speeds. The new clock rate setting calculation is:
96 * SCL = CLK_SOURCE.I2C /
97 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
98 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
100 * NOTE: We do this here, after the initial clock/pll start,
101 * because if we read the clk_div reg before the controller
102 * is running, we hang, and we need it for the new calc.
104 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
105 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
106 clk_div_stdfst_mode);
108 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
109 CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) *
113 /* Reset I2C controller. */
114 i2c_reset_controller(i2c_bus);
116 /* Configure I2C controller. */
117 if (i2c_bus->is_dvc) { /* only for DVC I2C */
118 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
120 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
123 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
126 static void send_packet_headers(
127 struct i2c_bus *i2c_bus,
128 struct i2c_trans_info *trans,
133 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
134 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
135 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
136 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
137 writel(data, &i2c_bus->control->tx_fifo);
138 debug("pkt header 1 sent (0x%x)\n", data);
140 /* prepare header2 */
141 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
142 writel(data, &i2c_bus->control->tx_fifo);
143 debug("pkt header 2 sent (0x%x)\n", data);
145 /* prepare IO specific header: configure the slave address */
146 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
148 /* Enable Read if it is not a write transaction */
149 if (!(trans->flags & I2C_IS_WRITE))
150 data |= PKT_HDR3_READ_MODE_MASK;
152 /* Write I2C specific header */
153 writel(data, &i2c_bus->control->tx_fifo);
154 debug("pkt header 3 sent (0x%x)\n", data);
157 static int wait_for_tx_fifo_empty(struct i2c_control *control)
160 int timeout_us = I2C_TIMEOUT_USEC;
162 while (timeout_us >= 0) {
163 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
164 >> TX_FIFO_EMPTY_CNT_SHIFT;
165 if (count == I2C_FIFO_DEPTH)
174 static int wait_for_rx_fifo_notempty(struct i2c_control *control)
177 int timeout_us = I2C_TIMEOUT_USEC;
179 while (timeout_us >= 0) {
180 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
181 >> TX_FIFO_FULL_CNT_SHIFT;
191 static int wait_for_transfer_complete(struct i2c_control *control)
194 int timeout_us = I2C_TIMEOUT_USEC;
196 while (timeout_us >= 0) {
197 int_status = readl(&control->int_status);
198 if (int_status & I2C_INT_NO_ACK_MASK)
200 if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
202 if (int_status & I2C_INT_XFER_COMPLETE_MASK)
212 static int send_recv_packets(struct i2c_bus *i2c_bus,
213 struct i2c_trans_info *trans)
215 struct i2c_control *control = i2c_bus->control;
222 int is_write = trans->flags & I2C_IS_WRITE;
224 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
225 int_status = readl(&control->int_status);
226 writel(int_status, &control->int_status);
228 send_packet_headers(i2c_bus, trans, 1);
230 words = DIV_ROUND_UP(trans->num_bytes, 4);
231 last_bytes = trans->num_bytes & 3;
235 u32 *wptr = (u32 *)dptr;
238 /* deal with word alignment */
239 if ((unsigned)dptr & 3) {
240 memcpy(&local, dptr, sizeof(u32));
241 writel(local, &control->tx_fifo);
242 debug("pkt data sent (0x%x)\n", local);
244 writel(*wptr, &control->tx_fifo);
245 debug("pkt data sent (0x%x)\n", *wptr);
247 if (!wait_for_tx_fifo_empty(control)) {
252 if (!wait_for_rx_fifo_notempty(control)) {
257 * for the last word, we read into our local buffer,
258 * in case that caller did not provide enough buffer.
260 local = readl(&control->rx_fifo);
261 if ((words == 1) && last_bytes)
262 memcpy(dptr, (char *)&local, last_bytes);
263 else if ((unsigned)dptr & 3)
264 memcpy(dptr, &local, sizeof(u32));
267 debug("pkt data received (0x%x)\n", local);
273 if (wait_for_transfer_complete(control)) {
279 /* error, reset the controller. */
280 i2c_reset_controller(i2c_bus);
285 static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data,
289 struct i2c_trans_info trans_info;
291 trans_info.address = addr;
292 trans_info.buf = data;
293 trans_info.flags = I2C_IS_WRITE;
294 trans_info.num_bytes = len;
295 trans_info.is_10bit_address = 0;
297 error = send_recv_packets(bus, &trans_info);
299 debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
304 static int tegra_i2c_read_data(struct i2c_bus *bus, u32 addr, u8 *data,
308 struct i2c_trans_info trans_info;
310 trans_info.address = addr | 1;
311 trans_info.buf = data;
312 trans_info.flags = 0;
313 trans_info.num_bytes = len;
314 trans_info.is_10bit_address = 0;
316 error = send_recv_packets(bus, &trans_info);
318 debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
323 #ifndef CONFIG_OF_CONTROL
324 #error "Please enable device tree support to use this driver"
328 * Check that a bus number is valid and return a pointer to it
330 * @param bus_num Bus number to check / return
331 * @return pointer to bus, if valid, else NULL
333 static struct i2c_bus *tegra_i2c_get_bus(struct i2c_adapter *adap)
337 bus = &i2c_controllers[adap->hwadapnr];
339 debug("%s: Bus %u not available\n", __func__, adap->hwadapnr);
346 static unsigned int tegra_i2c_set_bus_speed(struct i2c_adapter *adap,
351 bus = tegra_i2c_get_bus(adap);
355 i2c_init_controller(bus);
360 static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus)
362 i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg");
365 * We don't have a binding for pinmux yet. Leave it out for now. So
366 * far no one needs anything other than the default.
368 i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
369 i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0);
370 i2c_bus->periph_id = clock_decode_periph_id(blob, node);
373 * We can't specify the pinmux config in the fdt, so I2C2 will not
374 * work on Seaboard. It normally has no devices on it anyway.
375 * You could add in this little hack if you need to use it.
376 * The correct solution is a pinmux binding in the fdt.
378 * if (i2c_bus->periph_id == PERIPH_ID_I2C2)
379 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
381 if (i2c_bus->periph_id == -1)
382 return -FDT_ERR_NOTFOUND;
388 * Process a list of nodes, adding them to our list of I2C ports.
390 * @param blob fdt blob
391 * @param node_list list of nodes to process (any <=0 are ignored)
392 * @param count number of nodes to process
393 * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
394 * @param is_scs 1 if this HW uses a single clock source (T114+)
395 * @return 0 if ok, -1 on error
397 static int process_nodes(const void *blob, int node_list[], int count,
398 int is_dvc, int is_scs)
400 struct i2c_bus *i2c_bus;
403 /* build the i2c_controllers[] for each controller */
404 for (i = 0; i < count; i++) {
405 int node = node_list[i];
410 i2c_bus = &i2c_controllers[i];
413 if (i2c_get_config(blob, node, i2c_bus)) {
414 printf("i2c_init_board: failed to decode bus %d\n", i);
418 i2c_bus->is_scs = is_scs;
420 i2c_bus->is_dvc = is_dvc;
423 &((struct dvc_ctlr *)i2c_bus->regs)->control;
425 i2c_bus->control = &i2c_bus->regs->control;
427 debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
428 is_dvc ? "dvc" : "i2c", i, i2c_bus->regs,
429 i2c_bus->periph_id, i2c_bus->speed);
430 i2c_init_controller(i2c_bus);
434 /* Mark position as used */
441 /* Sadly there is no error return from this function */
442 void i2c_init_board(void)
444 int node_list[TEGRA_I2C_NUM_CONTROLLERS];
445 const void *blob = gd->fdt_blob;
448 /* First check for newer (T114+) I2C ports */
449 count = fdtdec_find_aliases_for_id(blob, "i2c",
450 COMPAT_NVIDIA_TEGRA114_I2C, node_list,
451 TEGRA_I2C_NUM_CONTROLLERS);
452 if (process_nodes(blob, node_list, count, 0, 1))
455 /* Now get the older (T20/T30) normal I2C ports */
456 count = fdtdec_find_aliases_for_id(blob, "i2c",
457 COMPAT_NVIDIA_TEGRA20_I2C, node_list,
458 TEGRA_I2C_NUM_CONTROLLERS);
459 if (process_nodes(blob, node_list, count, 0, 0))
462 /* Now look for dvc ports */
463 count = fdtdec_add_aliases_for_id(blob, "i2c",
464 COMPAT_NVIDIA_TEGRA20_DVC, node_list,
465 TEGRA_I2C_NUM_CONTROLLERS);
466 if (process_nodes(blob, node_list, count, 1, 0))
470 static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
472 /* This will override the speed selected in the fdt for that port */
473 debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
474 i2c_set_bus_speed(speed);
477 /* i2c write version without the register address */
478 int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
482 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
483 debug("write_data: ");
484 /* use rc for counter */
485 for (rc = 0; rc < len; ++rc)
486 debug(" 0x%02x", buffer[rc]);
489 /* Shift 7-bit address over for lower-level i2c functions */
490 rc = tegra_i2c_write_data(bus, chip << 1, buffer, len);
492 debug("i2c_write_data(): rc=%d\n", rc);
497 /* i2c read version without the register address */
498 int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
502 debug("inside i2c_read_data():\n");
503 /* Shift 7-bit address over for lower-level i2c functions */
504 rc = tegra_i2c_read_data(bus, chip << 1, buffer, len);
506 debug("i2c_read_data(): rc=%d\n", rc);
510 debug("i2c_read_data: ");
511 /* reuse rc for counter*/
512 for (rc = 0; rc < len; ++rc)
513 debug(" 0x%02x", buffer[rc]);
519 /* Probe to see if a chip is present. */
520 static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip)
526 debug("i2c_probe: addr=0x%x\n", chip);
527 bus = tegra_i2c_get_bus(adap);
531 rc = i2c_write_data(bus, chip, ®, 1);
533 debug("Error probing 0x%x.\n", chip);
539 static int i2c_addr_ok(const uint addr, const int alen)
541 /* We support 7 or 10 bit addresses, so one or two bytes each */
542 return alen == 1 || alen == 2;
546 static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
547 int alen, uchar *buffer, int len)
553 debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n",
555 bus = tegra_i2c_get_bus(adap);
558 if (!i2c_addr_ok(addr, alen)) {
559 debug("i2c_read: Bad address %x.%d.\n", addr, alen);
562 for (offset = 0; offset < len; offset++) {
565 for (i = 0; i < alen; i++) {
567 (addr + offset) >> (8 * i);
569 if (i2c_write_data(bus, chip, data, alen)) {
570 debug("i2c_read: error sending (0x%x)\n",
575 if (i2c_read_data(bus, chip, buffer + offset, 1)) {
576 debug("i2c_read: error reading (0x%x)\n", addr);
585 static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
586 int alen, uchar *buffer, int len)
592 debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n",
594 bus = tegra_i2c_get_bus(adap);
597 if (!i2c_addr_ok(addr, alen)) {
598 debug("i2c_write: Bad address %x.%d.\n", addr, alen);
601 for (offset = 0; offset < len; offset++) {
602 uchar data[alen + 1];
603 for (i = 0; i < alen; i++)
604 data[alen - i - 1] = (addr + offset) >> (8 * i);
605 data[alen] = buffer[offset];
606 if (i2c_write_data(bus, chip, data, alen + 1)) {
607 debug("i2c_write: error sending (0x%x)\n", addr);
615 int tegra_i2c_get_dvc_bus_num(void)
619 for (i = 0; i < TEGRA_I2C_NUM_CONTROLLERS; i++) {
620 struct i2c_bus *bus = &i2c_controllers[i];
622 if (bus->inited && bus->is_dvc)
630 * Register soft i2c adapters
632 U_BOOT_I2C_ADAP_COMPLETE(tegra0, tegra_i2c_init, tegra_i2c_probe,
633 tegra_i2c_read, tegra_i2c_write,
634 tegra_i2c_set_bus_speed, 100000, 0, 0)
635 U_BOOT_I2C_ADAP_COMPLETE(tegra1, tegra_i2c_init, tegra_i2c_probe,
636 tegra_i2c_read, tegra_i2c_write,
637 tegra_i2c_set_bus_speed, 100000, 0, 1)
638 U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
639 tegra_i2c_read, tegra_i2c_write,
640 tegra_i2c_set_bus_speed, 100000, 0, 2)
641 U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
642 tegra_i2c_read, tegra_i2c_write,
643 tegra_i2c_set_bus_speed, 100000, 0, 3)