2 * INCA-IP internal switch ethernet driver.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
30 && defined(CONFIG_INCA_IP_SWITCH)
34 #include <asm/inca-ip.h>
35 #include <asm/addrspace.h>
38 #define NUM_RX_DESC PKTBUFSRX
40 #define TOUT_LOOP 1000000
43 #define DELAY udelay(10000)
45 #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
46 #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
47 #define SW_WRITE_REG(reg, value) \
48 *((volatile u32*)reg) = (u32)value;\
50 *((volatile u32*)reg) = (u32)value;
52 #define SW_READ_REG(reg, value) \
53 value = (u32)*((volatile u32*)reg);\
55 value = (u32)*((volatile u32*)reg);
57 #define INCA_DMA_TX_POLLING_TIME 0x07
58 #define INCA_DMA_RX_POLLING_TIME 0x07
60 #define INCA_DMA_TX_HOLD 0x80000000
61 #define INCA_DMA_TX_EOP 0x40000000
62 #define INCA_DMA_TX_SOP 0x20000000
63 #define INCA_DMA_TX_ICPT 0x10000000
64 #define INCA_DMA_TX_IEOP 0x08000000
66 #define INCA_DMA_RX_C 0x80000000
67 #define INCA_DMA_RX_SOP 0x40000000
68 #define INCA_DMA_RX_EOP 0x20000000
70 /************************ Auto MDIX settings ************************/
71 #define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
72 #define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
73 #define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
74 #define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
76 #define WAIT_SIGNAL_RETRIES 100
77 #define WAIT_LINK_RETRIES 100
78 #define LINK_RETRY_DELAY 300 /* ms */
79 /********************************************************************/
88 volatile u32 offset :3;
89 volatile u32 reserved0 :4;
96 volatile u32 nextRxDescPtr;
98 volatile u32 RxDataPtr;
105 volatile u32 reserved3 :12;
106 volatile u32 NBT :17;
112 } inca_rx_descriptor_t;
119 volatile u32 HOLD :1;
122 volatile u32 ICpt :1;
123 volatile u32 IEop :1;
124 volatile u32 reserved0 :5;
125 volatile u32 NBA :22;
131 volatile u32 nextTxDescPtr;
133 volatile u32 TxDataPtr;
136 volatile u32 reserved3 :31;
138 } inca_tx_descriptor_t;
141 static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
142 static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
144 static int tx_new, rx_new, tx_hold, rx_hold;
145 static int tx_old_hold = -1;
146 static int initialized = 0;
149 static int inca_switch_init(struct eth_device *dev, bd_t * bis);
150 static int inca_switch_send(struct eth_device *dev, volatile void *packet,
152 static int inca_switch_recv(struct eth_device *dev);
153 static void inca_switch_halt(struct eth_device *dev);
154 static void inca_init_switch_chip(void);
155 static void inca_dma_init(void);
156 static int inca_amdix(void);
159 int inca_switch_initialize(bd_t * bis)
161 struct eth_device *dev;
164 printf("Entered inca_switch_initialize()\n");
167 if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
168 printf("Failed to allocate memory\n");
171 memset(dev, 0, sizeof(*dev));
175 inca_init_switch_chip();
177 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
181 sprintf(dev->name, "INCA-IP Switch");
182 dev->init = inca_switch_init;
183 dev->halt = inca_switch_halt;
184 dev->send = inca_switch_send;
185 dev->recv = inca_switch_recv;
190 printf("Leaving inca_switch_initialize()\n");
197 static int inca_switch_init(struct eth_device *dev, bd_t * bis)
204 printf("Entering inca_switch_init()\n");
209 wTmp = (u16)dev->enetaddr[0];
210 regValue = (wTmp << 8) | dev->enetaddr[1];
212 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
214 wTmp = (u16)dev->enetaddr[2];
215 regValue = (wTmp << 8) | dev->enetaddr[3];
216 regValue = regValue << 16;
217 wTmp = (u16)dev->enetaddr[4];
218 regValue |= (wTmp<<8) | dev->enetaddr[5];
220 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
222 /* Initialize the descriptor rings.
224 for (i = 0; i < NUM_RX_DESC; i++)
226 inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]);
227 memset(rx_desc, 0, sizeof(rx_ring[i]));
229 /* Set maximum size of receive buffer.
231 rx_desc->params.field.NFB = PKTSIZE_ALIGN;
233 /* Set the offset of the receive buffer. Zero means
234 * that the offset mechanism is not used.
236 rx_desc->params.field.offset = 0;
238 /* Check if it is the last descriptor.
240 if (i == (NUM_RX_DESC - 1)) {
241 /* Let the last descriptor point to the first
244 rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring);
246 /* Set the address of the next descriptor.
248 rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]);
251 rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]);
255 printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
256 printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
259 for (i = 0; i < NUM_TX_DESC; i++) {
260 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]);
262 memset(tx_desc, 0, sizeof(tx_ring[i]));
264 tx_desc->params.word = 0;
265 tx_desc->params.field.HOLD = 1;
268 /* Check if it is the last descriptor.
270 if (i == (NUM_TX_DESC - 1)) {
271 /* Let the last descriptor point to the
274 tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring);
276 /* Set the address of the next descriptor.
278 tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]);
284 DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
286 printf("RX status = 0x%08X\n", v);
289 /* Writing to the FRDA of CHANNEL.
291 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
293 /* Writing to the COMMAND REG.
295 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0,
296 INCA_IP_DMA_DMA_RXCCR0_INIT);
300 DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
302 printf("TX status = 0x%08X\n", v);
305 /* Writing to the FRDA of CHANNEL.
307 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
311 tx_hold = NUM_TX_DESC - 1;
312 rx_hold = NUM_RX_DESC - 1;
315 rx_ring[rx_hold].params.field.HOLD = 1;
317 /* enable spanning tree forwarding, enable the CPU port */
319 * CPS (CPU port status) 0x3 (forwarding)
320 * LPS (LAN port status) 0x3 (forwarding)
321 * PPS (PC port status) 0x3 (forwarding)
323 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
326 printf("Leaving inca_switch_init()\n");
333 static int inca_switch_send(struct eth_device *dev, volatile void *packet,
340 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]);
343 printf("Entered inca_switch_send()\n");
347 printf ("%s: bad packet size: %d\n", dev->name, length);
351 for(i = 0; tx_desc->C == 0; i++) {
352 if (i >= TOUT_LOOP) {
353 printf("%s: tx error buffer not ready\n", dev->name);
358 if (tx_old_hold >= 0) {
359 KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1;
361 tx_old_hold = tx_hold;
363 tx_desc->params.word =
364 (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
367 tx_desc->TxDataPtr = (u32)packet;
368 tx_desc->params.field.NBA = length;
370 KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0;
373 tx_new = (tx_new + 1) % NUM_TX_DESC;
377 command = INCA_IP_DMA_DMA_TXCCR0_INIT;
380 command = INCA_IP_DMA_DMA_TXCCR0_HR;
383 DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
386 printf("regValue = 0x%x\n", regValue);
388 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
391 for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) {
392 if (i >= TOUT_LOOP) {
393 printf("%s: tx buffer not ready\n", dev->name);
401 printf("Leaving inca_switch_send()\n");
407 static int inca_switch_recv(struct eth_device *dev)
410 inca_rx_descriptor_t * rx_desc;
413 printf("Entered inca_switch_recv()\n");
417 rx_desc = KSEG1ADDR(&rx_ring[rx_new]);
419 if (rx_desc->status.field.C == 0) {
424 rx_ring[rx_new].params.field.HOLD = 1;
427 if (! rx_desc->status.field.Eop) {
428 printf("Partly received packet!!!\n");
432 length = rx_desc->status.field.NBT;
433 rx_desc->status.word &=
434 ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
438 for (i=0;i<length - 4;i++) {
439 if (i % 16 == 0) printf("\n%04x: ", i);
440 printf("%02X ", NetRxPackets[rx_new][i]);
448 printf("Received %d bytes\n", length);
450 NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]),
454 printf("Zero length!!!\n");
459 KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0;
463 rx_new = (rx_new + 1) % NUM_RX_DESC;
467 printf("Leaving inca_switch_recv()\n");
474 static void inca_switch_halt(struct eth_device *dev)
477 printf("Entered inca_switch_halt()\n");
484 /* Disable forwarding to the CPU port.
486 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
488 /* Close RxDMA channel.
490 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
492 /* Close TxDMA channel.
494 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
499 printf("Leaving inca_switch_halt()\n");
504 static void inca_init_switch_chip(void)
508 /* To workaround a problem with collision counter
509 * (see Errata sheet).
511 SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
512 SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
515 /* init MDIO configuration:
516 * MDS (Poll speed): 0x01 (4ms)
519 * UEP (Use External PHY): 0x00 (Internal PHY is used)
520 * PS (Port Select): 0x00 (PT/UMM for LAN)
521 * PT (PHY Test): 0x00 (no test mode)
522 * UMM (Use MDIO Mode): 0x00 (state machine is disabled)
524 SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
527 * SL (Auto Neg. Speed for LAN)
528 * SP (Auto Neg. Speed for PC)
529 * LL (Link Status for LAN)
530 * LP (Link Status for PC)
531 * DL (Duplex Status for LAN)
532 * DP (Duplex Status for PC)
533 * PL (Auto Neg. Pause Status for LAN)
534 * PP (Auto Neg. Pause Status for PC)
536 SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
539 * RA (Request/Ack) 0x01 (Request)
540 * RW (Read/Write) 0x01 (Write)
542 * REG_ADDR 0x00 (PHY_BCR: basic control register)
544 * Reset - software reset
545 * LB (loop back) - normal
546 * SS (speed select) - 10 Mbit/s
547 * ANE (auto neg. enable) - enable
548 * PD (power down) - normal
549 * ISO (isolate) - normal
550 * RAN (restart auto neg.) - normal
551 * DM (duplex mode) - half duplex
552 * CT (collision test) - enable
554 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
557 * RA (Request/Ack) 0x01 (Request)
558 * RW (Read/Write) 0x01 (Write)
559 * PHY_ADDR 0x06 (LAN)
560 * REG_ADDR 0x00 (PHY_BCR: basic control register)
562 * Reset - software reset
563 * LB (loop back) - normal
564 * SS (speed select) - 10 Mbit/s
565 * ANE (auto neg. enable) - enable
566 * PD (power down) - normal
567 * ISO (isolate) - normal
568 * RAN (restart auto neg.) - normal
569 * DM (duplex mode) - half duplex
570 * CT (collision test) - enable
572 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
576 /* Make sure the CPU port is disabled for now. We
577 * don't want packets to get stacked for us until
578 * we enable DMA and are prepared to receive them.
580 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
582 SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
584 /* CRC GEN is enabled.
586 regValue |= 0x00000200;
587 SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
589 /* ADD TAG is disabled.
591 SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
592 regValue &= ~0x00000002;
593 SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
597 static void inca_dma_init(void)
599 /* Switch off all DMA channels.
601 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
602 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
604 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
605 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
606 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
608 /* Setup TX channel polling time.
610 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
612 /* Setup RX channel polling time.
614 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
616 /* ERRATA: write reset value into the DMA RX IMR register.
618 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
620 /* Just in case: disable all transmit interrupts also.
622 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
624 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
625 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
628 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
629 static int inca_amdix(void)
637 *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
638 *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
642 retries = WAIT_SIGNAL_RETRIES;
645 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
646 (0x1 << 31) | /* RA */
647 (0x0 << 30) | /* Read */
648 (0x6 << 21) | /* LAN */
649 (17 << 16)); /* PHY_MCSR */
652 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, regValue);
654 while (regValue & (1 << 31));
656 if (regValue & (1 << 1))
658 /* Signal detected */
668 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
673 retries = WAIT_LINK_RETRIES;
676 udelay(LINK_RETRY_DELAY * 1000);
677 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
678 (0x1 << 31) | /* RA */
679 (0x0 << 30) | /* Read */
680 (0x6 << 21) | /* LAN */
681 (1 << 16)); /* PHY_BSR */
684 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, regValue);
686 while (regValue & (1 << 31));
688 if (regValue & (1 << 2))
696 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
702 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
712 #endif /* CONFIG_INCA_IP_SWITCH_AMDIX */